User Guide with the Maximum Permissible Gain and Required Antenna Impedance for Each Antenna Type Indicated

DS90UH948-Q1EVM User's Guide

User's Guide

Literature Number: SNLU165 October 2014 Contents

1 DS90UH948-Q1EVM User's Guide ...... 5 1.1 General Description ...... 5 1.2 Features...... 5 1.3 System Requirements...... 6 1.4 Contents of the Demo Evaluation Kit ...... 6 1.5 Applications Diagram...... 6 1.6 Typical Configuration ...... 7 1.7 Quick Start Guide...... 8 1.8 Demo Board Connections ...... 9 1.9 ALP Software Setup ...... 12 1.9.1 System Requirements ...... 12 1.9.2 Download Contents ...... 12 1.9.3 Installation of the ALP Software ...... 12 1.9.4 Installation of the Device Profiles ...... 12 1.9.5 Startup - Software Description...... 12 1.9.6 Information Tab...... 14 1.9.7 Pattern Generator Tab...... 15 1.9.8 Registers Tab ...... 15 1.9.9 Registers Tab - Address 0x00 selected ...... 16 1.9.10 Registers Tab - Address 0x00 expanded ...... 17 1.9.11 Scripting Tab...... 19 1.10 Troubleshooting ALP Software ...... 20 1.10.1 ALP Loads the Incorrect Profile ...... 20 1.10.2 ALP does not detect the EVM ...... 22 1.11 CMLOUT Outputs for Eye Monitor ...... 24 1.12 Typical Connection and Test Equipment...... 24 1.13 Equipment References ...... 25 1.14 Cable References ...... 25 2 Bill of Materials ...... 26 A EVM PCB Schematics ...... 30 B Board Layout ...... 37

2 Contents SNLU165–October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated www.ti.com List of Figures 1-1. Applications Diagram...... 6 1-2. Typical Configuration ...... 7 1-3. Interfacing to the EVM ...... 8 1-4. Launching ALP ...... 13 1-5. Initial ALP Screen ...... 13 1-6. Follow-up Screen...... 14 1-7. ALP Information Tab ...... 14 1-8. ALP Pattern Generator Tab...... 15 1-9. ALP Registers Tab ...... 16 1-10. ALP Device ID Selected...... 17 1-11. ALP Device ID Expanded ...... 18 1-12. ALP Scripting Tab ...... 19 1-13. USB2ANY Setup ...... 20 1-14. Remove Incorrect Profile ...... 20 1-15. Add Correct Profile...... 21 1-16. Finish Setup...... 21 1-17. ALP No Devices Error ...... 22 1-18. Windows 7, ALP USB Driver ...... 22 1-19. ALP in Demo Mode ...... 23 1-20. ALP Preferences Menu...... 23 1-21. Typical Test Setup for Video Application...... 24 1-22. Typical Test Setup for Evaluation ...... 24 1 Top Layer...... 37 2 Ground Layer ...... 37 3 Power Layer...... 37 4 Bottom Layer...... 37 5 Top Silkscreen ...... 38 6 Bottom Silkscreen ...... 38

SNLU165–October 2014 List of Figures 3 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated www.ti.com List of Tables 1-1. Power Supply...... 9 1-2. OpenLDI Output Signals J15 and J16 ...... 9 1-3. FPD-Link III Input Signals ...... 9 1-4. USB2ANY Connector ...... 9 1-5. I2C/CCI Interface Header J13 ...... 10 1-6. GPIO/Audio Interface Header J17 ...... 10 1-7. SPI/D_GPIO Interface Header J14 ...... 10 1-8. CMLOUT Output Signals...... 10 1-9. Mode_Sel0 SW-DIP8 - S1 ...... 10 1-10. Mode_Sel1 SW-DIP8 - S2 ...... 11 1-11. IDx SW-DIP8 - S4 ...... 11 1-12. BISTEN/PDN Setting SW-DIP3 - S3 ...... 11

DS90UH948-Q1EVM User's Guide

1.1 General Description The Texas Instruments DS90Ux948-Q1EVM evaluation module (EVM) converts FPD-Link III to OpenLDI. This kit will demonstrate the functionality and operation of the DS90UH948-Q1/DS90UB948-Q1. The DS90UH948-Q1 supports HDCP content protection but otherwise is the same as DS90UB948-Q1. The information provided in this document can be applied to both devices. The DS90Ux948-Q1 is a FPD-Link III Deserializer which, in conjunction with the DS90Ux949/929/947-Q1 Serializers, it recovers the data from one or two FPD-Link III serial streams and translates it into either single or dual pixel OpenLDI LVDS supporting video resolutions up to WUXGA and 1080p60 with 24-bit color depth. The FPD-Link III interface supports video and audio data transmission and full duplex control, including GPIOs, I2C, and SPI communication, over the same differential link. In backward compatible mode, the device supports up to WXGA and 720p resolutions with 24-bit color depth over a single differential link. The device supports up to 7.1 audio channels. Audio data received from the FPD-Link III stream is decrypted and regenerated up to 8-channel I2S interface with maximum bit rate of 192 kHz.

NOTE: The demo board is not intended for EMI testing. The demo board was designed for easy accessibility to device pins with tap points for monitoring or applying signals, additional pads for termination, and multiple connector options.

1.2 Features • Supports Pixel Clock Frequency up to 170 MHz for WUXGA (1920x1200) and 1080p60 resolutions with 24-bit Color Depth • 2 lane FPD-Link III interface with De-skew capability • OpenLDI LVDS Transmitter – Selectable Single or Dual Pixel LVDS – Single Channel: Up to 96 MHz Pixel Clock – Dual Channel: Up to 170 MHz Pixel Clock – Configurable 18-bit RGB or 24-bit RGB per Pixel • Capable to recover data up to 15 meters 50Ω Coaxial or Differential Shielded Twisted-Pair (STP) cable • Backwards Compatible to DS90Ux925Q-Q1/925AQ-Q1 and DS90Ux927Q-Q1 FPD-Link III Serializers • Adaptive equalization • @Speed BIST and reporting pin • Supports 7.1 multiple I2S (4 data) channels • Single +12V power supply for EVM • 1.8V or 3.3V compatible LVCMOS I/O interface • Automotive grade product: AEC-Q100 Grade 2 qualified

SNLU165–October 2014 DS90UH948-Q1EVM User's Guide 5 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated System Requirements www.ti.com 1.3 System Requirements In order to demonstrate, the following is required: 1. FPD-Link III compatible Serializer (a) DS90Ux949-Q1, DS90Ux947-Q1 up to 1080p60 (b) DS90Ux929-Q1, DS90Ux925Q-Q1/925AQ-Q1, DS90Ux927Q-Q1 up to 720p60 2. Video source 3. Optional I2C controller 4. Power supply for 12V @ 1A (required)

1.4 Contents of the Demo Evaluation Kit 1. One EVM board with the DS90Ux948-Q1

1.5 Applications Diagram

VDDIO VDDIO

HDMI (1.8V) 1.8V 1.1V 3.3V 1.2V (3.3V / 1.8V) FPD-Link or FPD-Link III (Open LDI) DP++ 2 Lane

CLK1+/- IN_CLK-/+ DOUT0+ RIN0+ D0+/- IN_D0-/+ Mobile DOUT0- RIN0- D1+/- Device IN_D1-/+ or DOUT1+ RIN1+ D2+/- LVDS Graphics Display RIN1- Processor IN_D2-/+ DOUT1- D3+/- 1080p60 DS90Ux949-Q1 DS90Ux948-Q1 or Graphic Serializer CLK2+/- CEC Deserializer Processor DDC HPD D4+/-

D5+/- I2C I2C IDx D6+/- IDx D7+/- D_GPIO D_GPIO (SPI) (SPI) Figure 1-1. Applications Diagram

Video Processor Board (Video Data + Ctrl + PCLK) FPD-Link III Video Processor Serializer (I2C)

Dual FPD-LINK III

Cluster, Head Unit

(OpenLDI) DS90Ux948 Display

(I2C)

Figure 1-2. Typical Configuration

Figure 1-1 and Figure 1-2 illustrate the use of the chipset in a display application.

SNLU165–October 2014 DS90UH948-Q1EVM User's Guide 7 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Quick Start Guide www.ti.com 1.7 Quick Start Guide 1. Connect mini USB J10 to USB port for register programming (optional) 2. Configure switches S1, S2, S3 and S4 to set device’s operating modes 3. Connect J1 (RIN0+/- and RIN1+/-) to 1 lane or 2 lane FPD-Link III serial bit stream 4. Connect OpenLDI output signals (J15 and/or J16) to panel 5. Provide power to board on J18 (12V) (a) Optional +1.2VDC power supply on JP8, +1.8VDC power supply on JP9 and +3.3VDC power supply on JP10 6. For details of pin-names and pin-functions, please refer to the DS90Ux948-Q1 datasheet.

JP8-10 f J18 (Optional) f 1.2V +5%

12V 1.8 V c FPD-LINK III INPUTS +5% +5% d LVCMOS I/O

3.3 V e FUNCTION CONTROLS +5% J10 j f POWER SUPPLY g OpenLDI OUTPUTS h I2C/CCI BUS i CMLOUT OUTPUTS hJ13 j USB CONNECTOR

J3, J4 c (Optional)

J1 c g J15, J16

J8, J9 c (Optional)

dJ14 J17 J5 , J6 i eS1 , S2 , S3 , S4

Figure 1-3. Interfacing to the EVM

Table 1-1. Power Supply

Reference Signal Description 12V ±5% Main Power J18 +12V Single +12V power connector that supplies power to the entire board. 1.2V ±5% JP8 (Optional) +1.2V Alternative to Main Power 1.8V ±5% JP9 (Optional) +1.8V Alternative to Main Power 3.3V ±5% JP10 (Optional) +3.3V Alternative to Main Power

Table 1-2. OpenLDI Output Signals J15 and J16

Reference Port Signal J15.2 D0- J15.3 D0+ J15.6 D1- J15.7 D1+ J15.10 D2- OpenLDI Port 0 J15.11 D2+ J15.14 CLK1- J15.15 CLK1+ J15.18 D3- J15.19 D3+ J16.2 D4- J16.3 D4+ J16.6 D5- J16.7 D5+ J16.10 D6- OpenLDI Port 1 J16.11 D6+ J16.14 CLK2- J16.15 CLK2+ J16.18 D7- J16.19 D7+

Table 1-3. FPD-Link III Input Signals

Reference Signal Description RIN0+/- J1 HSD connector RIN1+/- J3 (Optional) RIN0+ SMA connector J4 (Optional) RIN0- SMA connector J8 (Optional) RIN1+ SMA connector J9 (Optional) RIN1- SMA connector

Table 1-4. USB2ANY Connector

Reference Description J10 mini USB 5 pin

SNLU165–October 2014 DS90UH948-Q1EVM User's Guide 9 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Demo Board Connections www.ti.com Table 1-5. I2C/CCI Interface Header J13

Reference Signal J13.1 VDDI2C J13.2 SCL J13.3 SDA J13.4 GND

Table 1-6. GPIO/Audio Interface Header J17

Reference Signal Description J17.2 SDOUT/GPIO0 Aux I2S Data Output / Remote or Local I/O J17.4 SWC/GPIO1 Aux I2S Word Clock Output / Remote or Local I/O J17.6 I2S_DC/GPIO2 I2S Data Output / Remote or Local I/O J17.8 I2S_DD/GPIO3 I2S Data Output / Remote or Local I/O J17.10 VDDIO GPIO Voltage Level 1.8V or 3.3V J17.12 I2S_DB/GPIO5 I2S Data Output / Local only I/O J17.14 I2S_DA/GPIO6 I2S Data Output / Local only I/O J17.16 I2S_WC/GPIO7 I2S Word Clock Output/ Local only I/O J17.18 I2S_CLK_GPIO8 I2S Clock Output / Local only I/O J17.20 MCLK I2S System Clock Output

Table 1-7. SPI/D_GPIO Interface Header J14

Reference Signal Description J14.2 BISTEN BIST Enable Pin (Shared with S3) J14.4 BISTC BIST Clock Select (Shared with S3) J14.6 VDDIO GPIO Voltage Level 1.8V or 3.3V J14.8 D_GPIO3/SS I/O in 2 lane FPD-Link III mode / Slave Select J14.10 D_GPIO2/SCLK I/O in 2 lane FPD-Link III mode / Serial Clock J14.12 D_GPIO1/MISO I/O in 2 lane FPD-Link III mode / Master In, Slave Out J14.14 D_GPIO0/MOSI I/O in 2 lane FPD-Link III mode / Master Out, Slave In

Table 1-8. CMLOUT Output Signals

Reference Signal Description J5 CMLOUT+ SMA connector J6 CMLOUT- SMA connector

Table 1-9. Mode_Sel0 SW-DIP8 - S1(1)

Reference Map Select Output Mode S1.1 0 Dual OLDI output S1.2 0 Dual SWAP output S1.3 0 Single OLDI output S1.4 0 Replicate S1.5 (Default) 1 Dual OLDI output S1.6 1 Dual SWAP output S1.7 1 Single OLDI output S1.8 1 Replicate (1) Only set one ON.

10 DS90UH948-Q1EVM User's Guide SNLU165–October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated www.ti.com Demo Board Connections Table 1-10. Mode_Sel1 SW-DIP8 - S2(1)

Reference Repeater Mode High Speed Back Channel Input Mode S1.1 0 00 5 Mbps STP (Default) S1.2 0 01 5 Mbps Coax S1.3 0 10 20 Mbps STP S1.4 0 11 20 Mbps Coax S1.5 1 00 5 Mbps STP S1.6 1 01 5 Mbps Coax S1.7 1 10 20 Mbps STP S1.8 1 11 20 Mbps Coax (1) Only set one ON.

Table 1-11. IDx SW-DIP8 - S4(1)

Reference 7-bit Address 8-bit Address S1.1 (Default) 0x2C 0x58 S1.2 0x2E 0x5C S1.3 0x30 0x60 S1.4 0x32 0x64 S1.5 0x34 0x68 S1.6 0x36 0x6C S1.7 0x38 0x70 S1.8 0x3C 0x78 (1) Only set one ON.

Table 1-12. BISTEN/PDN Setting SW-DIP3 - S3

Reference Signal Input = L Input = H Description Normal operating mode. BIST S3.1 BISTEN(1) BIST Mode is enabled. BIST Enable Input is disabled. (Default) S3.2 BISTC External Pixel Clock (Default) Internal Pixel Clock (~50MHz) BIST Clock Select S3.3 PDB Power Down (Disabled) Operational (Default) Power Down Mode Input (1) Before BIST can be enabled, the 948 D_GPIO[0] has to be strapped high and D_GPIO[3:1] strapped low on J14.

1.9.1 System Requirements

Operating System: Windows 7 64-bit USB: USB2ANY USB2ANY Firmware Version: 2.5.2.0

1.9.2 Download Contents TI Analog LaunchPAD can be downloaded from: http://www.ti.com/tool/alp. Download and extract the “snlc048.zip” file to a temporary location that can be deleted later.

NOTE: Make sure J10 on the DS90Ux948-Q1EVM is connected to a PC USB port with USB cable and power is applied to the board.

The following installation instructions are for the Windows 7 64-bit Operating System.

1.9.3 Installation of the ALP Software Execute the ALP Setup Wizard program called “ALPF_setup_v_x_x_x.exe” that was extracted to a temporary location on the local drive of your PC. There are 7 steps to the installation once the setup wizard is started: 1. Select the "Next" button. 2. Select “I accept the agreement” and then select the “Next” button. 3. Select the location to install the ALP software and then select the “Next” button. 4. Select the location for the start menu shortcut and then select the “Next” button. 5. There will then be a screen that allows the creation of a desktop icon. After selecting the desired choices select the “Next” button. 6. Select the “Install” button, and the software will then be installed to the selected location. 7. Uncheck “Launch Analog LaunchPAD” and select the “Finish” button. The ALP software will start if “Launch Analog LaunchPAD” is checked, but it will not be useful until the USB driver is installed and board is attached. Connect J10 USB jack of the DS90Ux948-Q1 EVM board to a PC/laptop USB port using a Type A

12 3 4 A 1 2 3 4 MINI to mini-B USB cable. Power the DS90Ux948-Q1 EVM board with a 12 VDC power supply. The “Found New Hardware Wizard” will open on the PC/laptop.

1.9.4 Installation of the Device Profiles There are 2 steps to add the DS90Ux948 profile: 1. Contact TI for the DS90Ux948 profile 2. Extract the “DS90Ux948.zip” to ALP’s profile folder. The profile folder can be found at: C:\Program Files (x64)\Texas Instruments\Analog LaunchPAD vx.x.x\Profiles\

1.9.5 Startup - Software Description Make sure all the software has been installed and the hardware is powered on and connected to the PC. Execute “Analog LaunchPAD” shortcut from the start menu. The default start menu location is under All Programs > Texas Instruments > Analog LaunchPAD vx.x.x > Analog LaunchPAD to start MainGUI.exe.

Figure 1-4. Launching ALP

The application should come up in the state shown in the figure below. If it does not, see Section 1.10, “Troubleshooting ALP Software”. Under the Devices tab click on “DS90Ux948_ENG” to select the device and open up the device profile and its associated tabs.

Figure 1-5. Initial ALP Screen

After selecting the DS90Ux948, the following screen should appear.

Figure 1-6. Follow-up Screen

1.9.6 Information Tab The Information tab is shown below. Please note the device revision could be different.

Figure 1-7. ALP Information Tab

14 DS90UH948-Q1EVM User's Guide SNLU165–October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated www.ti.com ALP Software Setup 1.9.7 Pattern Generator Tab The DES Pattern Generator tab is shown below.

Figure 1-8. ALP Pattern Generator Tab

1.9.8 Registers Tab The Register tab is shown below.

Figure 1-9. ALP Registers Tab

1.9.9 Registers Tab - Address 0x00 selected

Address 0x00 selected as shown below. Note that the “Value:” box, , will now show the hex value of that register.

Figure 1-10. ALP Device ID Selected

1.9.10 Registers Tab - Address 0x00 expanded By double clicking on the Address bar

or a single click on . Address 0x00 expanded reveals contents by bits. Any register address displayed can be expanded.

Figure 1-11. ALP Device ID Expanded

Any RW Type register, , can be written into by writing the hex value into the “Value:” box, or putting the pointer into the individual register bit(s) box by a left mouse click to put a check mark (indicating a “1”) or unchecking to remove the check mark (indicating a “0”). Click the “Apply” button to write to the register, and “refresh” to see the new value of the selected (highlighted) register.

The box toggles on every mouse click.

18 DS90UH948-Q1EVM User's Guide SNLU165–October 2014 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated www.ti.com ALP Software Setup 1.9.11 Scripting Tab The Scripting tab is shown below.

Figure 1-12. ALP Scripting Tab

The script window provides a full Python scripting environment which can be for running scripts and interacting with the device in an interactive or automated fashion.

WARNING Directly interacting with devices either through register modifications or calling device support library functions can effect the performance and/or functionality of the user interface and may even crash the ALP Framework application.

SNLU165–October 2014 DS90UH948-Q1EVM User's Guide 19 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Troubleshooting ALP Software www.ti.com 1.10 Troubleshooting ALP Software

1.10.1 ALP Loads the Incorrect Profile If ALP opens with the incorrect profile loaded the correct profile can be loaded from the USB2ANY/Aardvark Setup found under the tools menu.

Figure 1-13. USB2ANY Setup

Highlight the incorrect profile in the Defined ALP Devices list and press the remove button.

Figure 1-14. Remove Incorrect Profile

Find the correct profile under the Select a Daughter Board list, highlight the profile and press Add.

Figure 1-15. Add Correct Profile

Select Ok and the correct profile should now be loaded.

Figure 1-16. Finish Setup

SNLU165–October 2014 DS90UH948-Q1EVM User's Guide 21 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Troubleshooting ALP Software www.ti.com 1.10.2 ALP does not detect the EVM If the following window opens after starting the ALP software, double check the hardware setup.

Figure 1-17. ALP No Devices Error

It may also be that the USB driver is not installed. Check the device manager. There should be a “HID- compliant device” under the “Human Interface Devices” as shown below.

Figure 1-18. Windows 7, ALP USB Driver

The software should start with only “DS90UH948_ENG” in the “Devices” pull down menu. If there are more devices then the software is most likely in demo mode. When the ALP is operating in demo mode there is a “(Demo Mode)” indication in the lower left of the application status bar as shown below.

Figure 1-19. ALP in Demo Mode

Disable the demo mode by selecting the “Preferences” pull down menu and un-checking “Enable Demo Mode”.

Figure 1-20. ALP Preferences Menu

After demo mode is disabled, the ALP software will poll the ALP hardware. The ALP software will update and have only “DS90UH948_ENG” under the “Devices” pull down menu.

SNLU165–October 2014 DS90UH948-Q1EVM User's Guide 23 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated CMLOUT Outputs for Eye Monitor www.ti.com 1.11 CMLOUT Outputs for Eye Monitor Connector J5 connects to CMLOUT+ and J6 connects to CMLOUT-, which are present on the bottom right side of DS90Ux948Q Evaluation board. CMLOUT+/- must be enabled by register, 0x56[3] = 1 with 0x57 and 0x52, to be able to monitor the recovered FPD-Link III serial stream (see datasheet for details). • Reg 0x57[2:1] : 10 for channel 1, 01 for channel 0 • Reg 0x52[7] : 1 for channel 1 ; 0 for channel 0

1.12 Typical Connection and Test Equipment The following is a list of typical test equipment that may be used to generate signals for the Serializer inputs: 1. Digital Video Source – for generation of specific display timing such as Digital Video Processor or Graphics Controller (GPU) with HDMI or OpenLDI output. 2. Any other signal generator / video source - This video generator may be used for video signal sources for DVI or DP++ 3. Any other signal / video generator that provides the correct input levels as specified in the datasheet. The picture below shows a typical test set up using a Graphics Controller and display.

Serializer DS90Ux948 Board EVM Board

OpenLDI Display HDMI/DP++ LVDS or FPD-Link III OpenLDI Generator

Contents of Demo Kit

Graphics Controller / Video Processor Board Figure 1-21. Typical Test Setup for Video Application

The picture below shows a typical test set up using a video generator and logic analyzer.

Serializer DS90Ux948 Board EVM Board HDMI/DP++

DIGITAL VIDEO DIGITAL VIDEO GENERATOR GENERATOR or OpenLDI LVDS OpenLDI FPD-Link III Digital Video Source

Logic Analyzer / Oscilloscope Contents of Demo Kit Figure 1-22. Typical Test Setup for Evaluation

NOTE: Please note that the following references are supplied only as a courtesy to our valued customers. It is not intended to be an endorsement of any particular equipment or supplier.

Digital Video Pattern Generator: Astrodesign www.astro-americas.com

Logic Analyzer: Agilent Technologies Inc www.agilent.com

Corelis CAS-1000-I2C/E I2C Bus Analyzer and Exerciser Products: www.corelis.com/products/I2C-Analyzer.htm

Aardvark I2C/SPI Host Adapter Part Number: TP240141 www.totalphase.com/products/aardvark_i2cspi

1.14 Cable References For optimal performance, we recommend Shielded Twisted Pair (STP) 100ohm differential impedance and 24 AWG (or larger diameter) cable for high-speed data applications. Leoni Dacar 535 series cable: www.leoni-automotive-cables.com

Rosenberger HSD connector: www.rosenberger.de/en/Products/35_Automotive_HSD.php

Bill of Materials

Item Qty References Value Part Number Mfr Description C1, C2, C5, C8, C9, C10, C11, C17, C23, C24, C25, C26, C27, C30, C31, C32, C35, CGA2B3X7R1H104K05 CAP CER 0.1UF 50V 1 35 C48, C50, C53, C56, 0.1uF TDK Corporation 0BB 10% X7R 0402 C61, C65, C69, C73, C77, C79, C83, C90, C93, C99, C100, C102, C103, C104 CGA2B3X7R1H333K05 CAP CER 0.033UF 50V 2 4 C3, C4, C6, C7 0.033uF TDK Corporation 0BB 10% X7R 0402 CAP CER 10UF 16V 3 3 C12, C66, C80 10uF C3216X7R1C106K TDK X7R 10% 1206 CAP TANT 2.2UF 20V 4 2 C13, C89 2.2uF T491B225K020AT KEMET 10% 1411 C14, C47, C55, C60, CGA3E1X7R1E105K08 CAP CER 1UF 25V 5 10 C64, C68, C72, 1uF TDK Corporation 0AC 10% X7R 0603 C76,C82, C92 C15, C44, C51, C57, C58, C62, C70, GCM155R71H103KA55 CAP CER 10000PF 6 15 0.01uF Murata Electronics C74,C78, C84, C85, D 50V 10% X7R 0402 C86,C87, C94, C95 CAP TANT 22UF 25V 7 2 C16, C88 22uF F931E226MNC nichicon 20% 2917 CAP CER 220PF 50V 8 2 C18, C21 220PF C1608X7R1H221K TDK 10% X7R 0603 CAP CER 30PF 50V 9 2 C19, C20 30pF C1608C0G1H300J TDK 5% NP0 0603 CAP CER 2200PF 50V 10 1 C22 2200PF C1608X7R1H222K TDK 10% X7R 0603 C28, C46, C49, C52, GRM21BR71C475KA7 CAP CER 4.7UF 16V 11 5 4.7uF Murata Electronics C63 3L 10% X7R 0805 C1608X7R1H474K080 CAP CER 0.47UF 50V 12 1 C29 470nF TDK AC 10% X7R 0603 CAP CER 4.7PF 25V 13 2 C33,C34 4.7pF ECD-G0E4R7C Panasonic NP0 0402 CAP CER 0.022UF 50V 14 1 C36 0.022uF C0805C223K5RACTU Kemet 10% X7R 0805 C3225X7R1E106M250 CAP CER 10UF 25V 15 1 C37 10uF TDK Corporation AC X7R 20% 1210 CAP ALUM 100UF 8V 16 1 C38 100uF EEF-UD0K101R Panasonic 20% SMD APXA100ARA271MHC CAP ALUM 270UF 10V 17 1 C39 270uF United Chemi-Con 0G 20% SMD CAP CER 100UF 6.3V 18 2 C40, C41 100uF JMK325BJ107MM-T Taiyo Yuden 20% X5R 1210 CAP CER 180PF 50V 19 1 C42 180pF CC0805JRNP09BN181 Yageo 5% NPO 0805 CAP CER 150PF 50V 20 1 C43 150pF 08055A151JAT2A AVX Corporation 5% NP0 0805 CAP 560PF 50V 21 1 C45 560pF CC0805KRX7R9BB561 Yageo CERAMIC X7R 0805 C54, C59, C67, C71, CAP CER 10UF 6.3V 22 7 10uF JMK212AB7106KGHT Taiyo Yuden C75, C81, C91 10% X7R 0805

Item Qty References Value Part Number Mfr Description CGA2B2X7R1H222K05 CAP CER 2200PF 50V 23 1 C101 2.2nF TDK Corporation 0BA 10% X7R 0402 DIODE ZENER 7.5V 24 1 D1 1SMB5922 1SMB5922B-13 Diodes Inc 3W SMB DIODE SCHOTTKY 3A 25 1 D3 DIODE B340A-13-F Diodes Inc 40V SMA PTC RESET 15V .500A 26 1 F1 FUSE 1206L050/15YR Littelfuse Inc SMD 1206 CONN HEADER VERT .100 2POS 30AU. DO 27 2 JP1, JP2 2-Pin Header_open 87220-2_open AMP/Tyco NOT PURCHASE, DO NOT MOUNT. CONN HEADER VERT .100 2POS 30AU. DO 28 1 JP3 2-Pin Header_open 87220-2_open AMP/Tyco NOT PURCHASE. DO NOT POPULATE. JP4, JP6, JP7, JP8, CONN HEADER VERT 29 7 2-Pin Header 87220-2 AMP/Tyco JP9, JP10, JP11 .100 2POS 30AU CONN HEADER VERT 30 2 JP5, JP12 3-Pin Header 87224-3 Tyco .100 3POS 15AU Automotive HSD 31 1 J1 HSD_2X2 D4S20D-40ML5-Y Rosenberger Connector - Right Angle Plug for PCB. FAKRA-HF PCB RIGHT 32 2 J2, J7 FAKRA 59S20X-40ML5-Y_open Rosenberger ANGLE PLUG CONN SMA JACK 50 33 6 J3, J4, J5, J6, J8, J9 SMA 142-0701-851 Emerson OHM EDGE MNT CONN RECEPT MINI 34 1 J10 mini USB 5pin UX60-MB-5ST Hirose USB2.0 5POS. CONN HEADER .100 DUAL STR 14POS. DO 35 1 J11 HEADER 7X2_open PBC07DFAN_open Sullins NOT PURCHASE. DO NOT POPULATE. CONN HEADER .100 36 1 J12 HEADER 5X2 PBC05DFAN Sullins DUAL STR 10POS Molex/Waldom CONN HEADER 4POS 37 1 J13 IDC1X4 22-11-2042 Electronics Corp .100 VERT GOLD CONN HEADER .100 38 1 J14 HEADER 7X2 PBC07DFAN Sullins DUAL STR 14POS CONN HEADER 20 39 2 J15, J16 2X10-Pin Header N2520-6002RB 3M POS STRGHT GOLD. CONN HEADER 40 1 J17 2X10-Pin Header 67997-220HLF FCI 20POS .100 STR 15AU CONN POWER JACK 41 1 J18 CONN JACK PWR PJ-002A CUI Inc 2.1MM DIP20 SOCKET - SOCKET IC OPEN 42 1 J19 4820-3004-CP 3M MSP430G2403IN20 FRAME 20POS .3" CONN HEADER LOW- 43 1 J20 JTAG-14 AWHW14G-0202-T-R Assmann PRO 14POS GOLD CONN HEADER VERT 44 1 J21 2X2-Pin Header 87227-2 TEC .100 4POS 15AU LED GREEN CLEAR 45 3 LED1, LED4 0603_green_LED LTST-C191KGKT LITE-ON INC THIN 0603 SMD LED ORANGE CLR RT 46 1 LED2 0603_orange_LED LTST-S270KFKT Lite-On Inc ANG SMD LED SUPER RED 47 1 LED3 0603_red_LED LTST-C190KRKT LITE-ON INC CLEAR 0603 SMD CHOKE COIL COMMON MODE 48 2 L1, L2 Z = 90 ohm DLW21SN900HQ2L Murata 280MA SMD. DO NOT PURCHASE. DO NOT POPULATE. FERRITE BEAD 60 49 1 L3 BK1608HS600-T BK1608HS600-T Taiyo Yuden OHM 0603 INDUCTOR POWER 50 1 L4 15uH SDR1806-150ML Bourns Inc. 15UH SMD

Item Qty References Value Part Number Mfr Description FERRITE CHIP BEAD 51 2 L5, L11 FB 1K@100MHz,0603 MPZ1608S102A TDK Corporation 1000 OHM 0603 FILTER CHIP 120 OHM 52 5 L6, L7, L8, L9, L10 FB 120@100MHz,0603 BLM18SG121TN1D Murata Electronics 3A 0603 MOSFET N-CH 50V 53 1 Q1 BSS138 BSS138 Fairchild 220MA SOT-23 RES 220 OHM 1/10W 54 4 R1, R2, R75, R98 220 Ohm,0402 ERJ-2GEJ221X Panasonic 5% 0402 SMD R12, R20, R37, R38, RES ZERO OHM R47, R63, R64,R73, 1/16W 5% 0402 SMD. 55 13 0 Ohm,0402_open ERJ-2GEJ0R00X_open Panasonic R74, R87, R91, R109, DO NOT PURCHASE, R120 DO NOT LOAD. RES 0.0 OHM 1/10W 56 2 R3, R4 JUMP 0402 SMD RES 0.0 OHM 1/10W 57 4 R97, R107, R115, R116 0 Ohm,0402 ERJ-2GEJ0R00X Panasonic JUMP 0402 SMD RES 45.3k OHM 1/10W 58 3 R5, R13, R40 45.3K Ohm,0402 ERJ-2RKF4532X Panasonic 1% 0402 SMD RES 90.9K OHM 59 3 R6, R14, R41 90.9K Ohm,0402 ERJ-2RKF9092X Panasonic 1/10W 1% 0402 SMD RES 107K OHM 1/10W 60 4 R7, R15, R18, R42 107K Ohm,0402 ERJ-2RKF1073X Panasonic 1% 0402 SMD R8,R9,R16,R17,R22, RES 113K OHM 1/10W 61 9 113K Ohm,0402 ERJ-2RKF1133X Panasonic R30,R43,R44,R53 1% 0402 SMD RES 107K OHM 1/10W 62 2 R10,R45 107K Ohm,0402 ERJ-2RKF1073X Panasonic 1% 0402 SMD RES 232K OHM 1/10W 63 3 R11,R19,R46 232K Ohm,0402 ERJ-2RKF2323X Panasonic 1% 0402 SMD RES 182K OHM 1/10W 64 3 R21,R29,R52 182K Ohm,0402 ERJ-2RKF1823X Panasonic 1% 0402 SMD RES 93.1K OHM 65 3 R23,R31,R54 93.1K Ohm,0402 ERJ-2RKF9312X Panasonic 1/10W 1% 0402 SMD RES 68.1K OHM 66 3 R24,R32,R55 68.1K Ohm,0402 ERJ-2RKF6812X Panasonic 1/10W 1% 0402 SMD R25,R27,R33,R35,R56, RES 47.5K OHM 67 6 47.5K Ohm,0402 ERJ-2RKF4752X Panasonic R58 1/10W 1% 0402 SMD RES 31.6K OHM 68 3 R26,R34,R57 31.6K Ohm,0402 ERJ-2RKF3162X Panasonic 1/10W 1% 0402 SMD RES 40.2K OHM 69 3 R28,R36,R59 40.2K Ohm,0402 ERJ-2RKF4022X Panasonic 1/10W 1% 0402 SMD RES 49.9 OHM 1/10W 1% 0402 SMD. DO 70 4 R48, R49, R50, R65 49.9ohm,0402_open ERJ-2RKF49R9X_open Panasonic NOT PURCHASE. DO NOT POPULATE. R60, R61, R62, R76, RES 10.0K OHM 71 5 10K ERJ-3EKF1002V Panasonic R77 1/10W 1% 0603 SMD RES 33 OHM 1/10W 72 2 R66, R67 33 ohm ERJ-3GEYJ330V Panasonic 5% 0603 SMD R68, R99, R103, R113, RES 0.0 OHM 1/10W 73 5 0 Ohm, 0603 ERJ-3GEY0R00V Panasonic R117 JUMP 0603 SMD RES 1.5K OHM 1/10W 74 3 R69, R78, R79 1.5K ERJ-3GEYJ152V Panasonic 5% 0603 SMD RES 33K OHM 1/10W 75 2 R70, R72 33K ohm ERJ-3GEYJ333V Panasonic 5% 0603 SMD RES 1.2M OHM 1/10W 76 1 R71 1.2M ohm ERJ-3GEYJ125V Panasonic 5% 0603 SMD RES 100 OHM 1/10W R80, R86, R88, 5% 0402 SMD. DO 77 10 R89,R90, R92, R93, 100_open ERJ-2GEJ101X_open Panasonic NOT PURCHASE. DO R94,R95, R96 NOT POPULATE. RES 4.7K OHM 1/10W 78 2 R81, R82 4.7K ERJ-3GEYJ472V Panasonic 5% 0603 SMD RES 0.0 OHM 1/10W 79 3 R83, R84, R85 0 Ohm ERJ-2GEJ0R00X Panasonic JUMP 0402 SMD RES 52.3K OHM 1/8W 80 1 R100 52.3Kohm ERJ-6ENF5232V Panasonic 1% 0805 SMD

Item Qty References Value Part Number Mfr Description RES 9.53K OHM 1/8W 81 1 R101 9.53Kohm RG2012P-9531-B-T5 Panasonic .1% 0805 SMD RES 3.09K OHM 1/8W 82 1 R102 3.09Kohm ERJ-6ENF3091V Panasonic 1% 0805 SMD RES 2.49K OHM 83 1 R104 2.49K ERJ-3EKF2491V Panasonic 1/10W 1% 0603 SMD RES 100K OHM 1/10W 84 3 R105, R111, R114 100K ERJ-3EKF1003V Panasonic 1% 0603 SMD RES 1.0K OHM 1/10W 85 1 R106 1K ERJ-3EKF1001V Panasonic 1% 0603 SMD RES 4.99K OHM 86 1 R108 4.99K ERJ-3EKF4991V Panasonic 1/10W 1% 0603 SMD RES 23.2K OHM 87 1 R110 23.2K ERJ-2RKF2322X Panasonic 1/10W 1% 0402 SMD RES 12.1K OHM 88 1 R112 12.1K ERJ-2RKF1212X Panasonic 1/10W 1% 0402 SMD RES 330 OHM 1/10W 89 1 R118 330ohm ERJ-2RKF3300X Panasonic 1% 0402 SMD RES 47K OHM 1/16W 90 1 R119 47Kohm ERA-3AEB473V Panasonic .1% 0603 SMD SWITCH TACTILE 91 3 SW1, SW2, SW3 SPST ADTSM31NV APEM Components SPST-NO 0.05A 12V CTS SWITCH TAPE SEAL 8 92 4 S1, S2, S4, S5 SW SMD-8 219-8MST Electrocomponents POS SMD 50V SWITCH DIP 93 1 S3 SW DIP-3 78B03ST Grayhill EXTENDED SEALED 3POS TP1, TP2, TP3, TP4,TP5, TP6, TEST POINT. NOT A 94 12 TEST POINT TP7,TP8, TP9, TP10, COMPONENT TP11, TP12 DS90UH948-Q1 DS90UH948-Q1 DS90UH948-Q1 95 1 U1 TI DS90UB948-Q1 DS90UB948-Q1 DS90UB948-Q1 IC REG LDO 3.3V 0.5A 96 1 U2 TPS73533DRB TPS73533DRBT TI 8SON IC 4CH ESD-PROT 97 1 U3 TPD4E004DRY TPD4E004DRYR TI ARRAY 6-SON IC MCU 16BIT 128K 98 1 U4 MSP430F5529IPN MSP430F5529IPN TI FLASH 80LQFP IC 6BIT NON-INV 99 1 U5 TXB0106IPWR TXB0106PWR TI TRANSLTR 16TSSOP IC V-LEVEL XLATR 100 1 U6 TCA9406DCUR TCA9406DCUR TI I2C/SMBUS US8 IC REG BUCK ADJ 3A 101 1 U7 LM25576MH/NOPB LM25576MH/NOPB TI 20TSSOP IC REG LDO ADJ 1.5A 102 1 U8 TPS74801DRC TPS74801DRCT TI 10SON IC REG LDO 1.8V/3.3V 103 1 U9 TPS767D318PWP TPS767D318PWP TI 1A 28HTSSOP Crystal, SMT Quart CRYSTAL 24.000MHZ 104 1 Y1 ECS-240-20-5PX-TR ECS Crystal 20PF SMD DS90UX948_940- DS90UH948-Q1EVM 105 Q1EVM Rev1E Brd SV601029 TI DS90UB948-Q1EVM PCB

PCB A B C D E Schematics

LAYOUT NOTES:

4 1) 4 layer board. 4 2) Use standard FR-406 or FR-370HR. 3) 5% impedance tolerance. 4) Minimum 4 standoffs on each corner of board. (0. 156 X 4).

1 Primary component side, 1.58 MIL (layer 1) 4.5 MIL Copyright 2 Ground plane, 1.4 MIL (layer 2)

Texas 4.5 MIL 4 Secondary component side, 1.58 MIL (layer 4) Instruments Incorporated

2 2 EVM

Core Material PCB

Prepreg Material Submit SNLU165

1 1 Schematics Documentation

SNLU165 Title Board Stackup

Size Document Number Rev Appendix A DS90UBUH948_940-Q1EVM 1E –

Date: Tuesday, September 16, 2014 Sheet 1of 8 October – A B C D E October Feedback 2014 2014 A Submit SNLU165 www.ti.com

5 4 3 2 1 Documentation Approximate layout of major components/connectors –

October Board Block Diagram J18 U8 U9 U7 Power 2014 +12V +5V Options I2S Bank D_GPIO D Connector D Feedback Barrel Aux PDB GPIO0 D_GPIO0 BISTC GPIO1 D_GPIO1 J10 J19 VDD33 U2 Supply BISTEN I2S_DA D_GPIO2 VDD12 VSS J13 INTB I2S_DB D_GPIO3 S5 VDD18 I2S_DC J2/J3 I2S_DD U4 I2S_CLK I2S_WC J4 MCLK J15 SMA /

C C

2014, J7/J8

FPDL3+ Texas J9 HSD LVDSx+ J17 J14 FPDL3- Instruments LVDSx-

J5 SMA / 20-pin IDC S4 Incorporated FAKRA DS90UH948Q J6 S2 S1 S3 B DS90UH940Q B SMA LVDSx+

LVDSx- FPDL3+ 20-pin IDC HSD FPDL3-

FPD (LVDS) Output FPD3 Input EVM

SDA

PCB I2C Status LEDs CAD Connector SCL PASS IDx Schematics A A LOCK MODE_SEL[1:0] Title Block Diagram USB2ANY Appendix Size Document Number Rev USB A DS90UBUH948_940-Q1EVM 1E Date: Tuesday, September 16, 2014 Sheet 2of 8

31 5 4 3 2 1 A 32 Appendix EVM A A B C D E

PCB Layout note: For all differential pairs(CSI-2 and L VDS) in this design follow the guidelines decribed below: VSS JP1 JP2 Route together with controlled differential 100ohm impedance and controlled single ended 50ohm {4,5,6,7} VSS VDD33 1 2 1 2 impedance. Keep away from other high speed signals. Keep lengths within 5mil of each other. Keep {5,6,7} VDD33 VDD33c traces on layers adjacent to the ground plane. Keep the number of VIAS to minimum. If VIAS are used, {3,6} VDD33c VDDIO make it symetrical through all signals. Keep diff p airs separated at least by x3 of the trace width.

Schematics {4,5,6} VDDIO NO STUBS on the signal path, components should be p laced such that the signals can routed in VDDIOc 0603_green_LED LED1 0603_orange_LED LED2 {6} VDDIOc pass-through manner. LOCK 2 R1 1 2 1 GPIO0 2 R2 1 2 1 {3,5} GPIO0 VDDR12_0 220 Ohm,0402 220 Ohm,0402 R3 R4 {5} {5} {5} {5} {5} {5} {6} VDDR12_0 {5} {5} {5} {5}

VDDR12_1 D0- D1- D2- D3- 948 open populated {6} VDDR12_1 D0+ D1+ D2+ D3+

Connect to VSS PDB {4,7} 940 populated open

Connect to VSS CLK1- CLK1+ VDD33c VDDP12_0 {6} VDDP12_0 VDDP12_1 4 {6} VDDP12_1 2 R3 1 VDD12_Pin33 4 VSS VSS VDD12_Pin33 {6} R5 R6 R7 R8 R9 0 Ohm,0402_open R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20

VDDL12c 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 {6} VDDL12c 1 R4 2 0.1uF2 C1 1 I2C_SCL VDDL12c D0- D0+ D1- D1+ D2- D2+ CLK1- CLK1+ D3- D3+ PDB IDx I2C_SDA VSS 0 Ohm,0402 VDDP12_LVDS {6} VDDP12_LVDS U1 VDD12_LVDS 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 {6} VDD12_LVDS 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 107K Ohm,0402 107K Ohm,0402 113K Ohm,0402 113K Ohm,0402 107K Ohm,0402 232K Ohm,0402 107K Ohm,0402 113K Ohm,0402 113K Ohm,0402 107K Ohm,0402 232K 45.3K 45.3K Ohm,0402 90.9K Ohm,0402 45.3K Ohm,0402 90.9K Ohm,0402 D0- D1- D2- D3- IDX D0+ D1+ D2+ D3+ PDB I2C_SDA 0 Ohm,0402_open 0 Ohm,0402_open CLK1-

{4,5,7} I2C_SDA CLK1+ I2C_SCL I2C_SCL {4,5,7} I2C_SCL LAYOUT NOTE: L short pin 1 to I2C_SDA pin 2, short pin 3 and pin 4. Cut VDDL12_1

traces to populate common VSS C21 0.1uF2 VDD25_CAP mode filter. R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 R32 R36 R33 R34 R35 49 32 VDDP12_LVDS 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 RINB+ MODE_SEL1 50 CAP_PLL0 VDDP12_LVDS 31 VDD33c C3 0.033uF VDDP12_0 51 MODE_SEL1 VDD33_B 30 D4-

4 3 D4- {5} RINA+ RINA+ 1 2 VDDR12_0 52 VDDP12_CH0 D4- 29 D4+

5 6 1 2 D4+ {5} L1 53 VDDR12_CH0 D4+ 28 D5- RIN0+ D5- D5- {5} Copyright RINA- Z = 90 ohm C4 0.033uF 100 ohm differential impedance +/-5%. 54 27 D5+ 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 5 6 1 2 RIN0- D5+ D5+ {5} 182K Ohm,0402 182K Ohm,0402 113K Ohm,0402 182K Ohm,0402 113K

J1 1 2 VSS C51 0.1uF2 55 26 D6- 93.1K Ohm,0402 68.1K Ohm,0402 47.5K Ohm,0402 31.6K Ohm,0402 47.5K Ohm,0402 40.2K Ohm,0402 93.1K Ohm,0402 68.1K Ohm,0402 47.5K Ohm,0402 31.6K Ohm,0402 47.5K Ohm,0402 40.2K Ohm,0402

1 2 D6- {5} 8 7 4 3 CMF D6- HSD_2X2 C6 0.033uF VDD33c 56 25 D6+ D6+ {5} RINB- 1 2 {3,6} VDD33c VDDR12_1 57 VDD33_A DS90UH948Q D6+ 24 CLK2- 8 7 4 3

4 3 CLK2- {5} RINB+ 58 VDDR12_CH1 CLK2- 23 CLK2+ RIN+ CLK2+ CLK2+ {5} VSS RINA- L2 C7 0.033uF 100 ohm differential impedance +/-5%. 59 22 D7- D7- {5} RINB- Z = 90 ohm 1 2 VDDP12_1 60 RIN- D7- 21 D7+ 3 D7+ {5} 3 MODE_SEL0 61 VDDP12_CH1 D7+ 20 VDD12_LVDS © 1 2 MODE_SEL0 VDD12_LVDS DOUT+ 62 19 D_GPIO0 VSS 15 13 11 9 7 5 3 1 H 15 13 11 9 7 5 3 1 VSS CMLOUTP D_GPIO0/MOSI D_GPIO0 {5} H

2014, 100 ohm differential impedance +/-5%. DOUT- 63 18 D_GPIO1 D_GPIO1 {5} S1 S2 64 CMLOUTM D_GPIO1/MISO 17 D_GPIO2

CAP_PLL1 D_GPIO2/SPLK D_GPIO2 {5} N

RINA+ VSS C81 0.1uF2 N

O SW SMD-8 SW SMD-8

8 7 6 5 8 7 6 5 4 3 2 1 RINA- 4 3 2 1 MODE_SEL0 MODE_SEL1 VSS VSS L L

Texas J2 J3 VSS 65 8 6 4 2 8 6 4 2 16 14 12 10 16 14 12 10 2 2 DAP MODE_SEL0 MODE_SEL1

5 5 2 2 C102 C103 5 4 5 4 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1

4 4 LOCK CAP_I2S VDDIO BISTC/INTB BISTEN/TESTEN VDDL12_0 SDOUT/GPIO0/PASS SWC/GPIO1 I2S_DD/GPIO3 I2S_DC/GPIO2 I2S_DB/GPIO5_REG I2S_DA/GPIO6_REG I2S_CLK/GPIO8_REG I2S_WC/GPIO7_REG MCLK D_GPIO3/SS 3 3 R37 R38 VSS 3 3 0.1uF 0.1uF 2 2 CMLOUT+ 1 1 1 2 3 4 5 6 7 8 9 Instruments 2 2 10 11 12 13 14 15 16

1 1 0 Ohm,0402_open 0 Ohm,0402_open 5 VDD33c 1 1 VSS 1 1 5 4 VSS FAKRA SMA 4 3 3 R40 R41 R42 R43 R44 R45 R46 R47

SMA 2 C9 0.1uF

2 1 1 1 1 1 1 1 1

Layout note: overlay VSS 1 1 2 LOCK CAPI2S VDDIOc BISTC BISTEN VDDL12c GPIO0 GPIO1 I2S_DD I2S_DC I2S_DB I2S_DA I2S_CLK I2S_WC MCLK D_GPIO3 J4 footprint for SMA and 0.625" J5 1 FAKRA connector - signal 5 VSS 50 ohm C101 0.1uF2 {5} {5} {5} {5} {5} {5} {5} {5} {5} {5} CMLOUT- {5} pin 1 on both is the same 5 single VSS

4 1 R48 2 {3,5}

pad 4 ended MCLK BISTC 3 50 ohm 5 49.9ohm,0402_open GPIO0 GPIO1 2 2 2 2 2 2 2 2

0.625" I2S_DB I2S_DA BISTEN I2S_DD I2S_DC Incorporated impedance 3 5 I2S_WC 2 single ended 4 1 R49 2 I2S_CLK D_GPIO3

traces Ohm,0402 107K Ohm,0402 113K Ohm,0402 113K Ohm,0402 107K Ohm,0402 232K 2 impedance 4 45.3K Ohm,0402 90.9K Ohm,0402

1 3 49.9ohm,0402_open 0 Ohm,0402_open

1 1 traces 3

2 SMA 2 C11 0.1uF 2 SMA 2 1 1 2 J6 1 VSS

R50 R52 R53 R54 R55 R56 R57 R58 R59 49.9ohm,0402_open 1 1 1 1 1 1 1 1 2 VDDIO

VSS 2 2 2 R60 R61 R62 RINB+ 50 ohm single ended 2 2 2 2 2 2 2 2 182K Ohm,0402 182K Ohm,0402 113K RINB- impedance traces 93.1K Ohm,0402 68.1K Ohm,0402 47.5K Ohm,0402 31.6K Ohm,0402 47.5K Ohm,0402 40.2K Ohm,0402

VSS VSS 10K 10K 10K J7 J8 1 1 1 PDB 5 5 2 2 BISTC 5 4 5 4 BISTEN SW1 4 4 VSS 3 3 R63 R64 Silkscreen C12 3 2 3 2 3 2 1 namings SPST 2 2 H 15 13 11 9 7 5 3 1 H 1 1 0 Ohm,0402_open 0 Ohm,0402_open 10uF 1 1

1 1 S3 2 S4 N

FAKRA SMA O JP3

Submit N

L 3 2 1

INTB_IN O SW SMD-8

SW SW DIP-3 8 7 6 5

Layout note: overlay VSS 4 3 2 1 IDX footprint for SMA and J9 4 5 6 1 L

0.625" 8 6 4 2 2

FAKRA connector - signal 5 IDX 16 14 12 10 C104 1 pin 1 on both is the same 5 4 1 pad 4 3 50 ohm VSS VSS VSS 0.1uF 1 78 70 6C 68 64 60 5C 58

Documentation 3 single ended

SNLU165 2 2 1 impedance VSS

1 1 traces SMA Title DS90UBUH948 R65 49.9ohm,0402_open Size Document Number Rev VSS 2 B DS90UBUH948_940-Q1EVM 1E

– Date: Tuesday, September 16, 2014 Sheet 3of 8

October A B C D E www.ti.com Feedback 2014 Submit SNLU165 www.ti.com

A B C D E

Documentation [email protected] UC POWER SUPPLY F1 9 8 VBUS –

9 8 FUSE

October 1 VDD33_UC VBUS 1 2 R66 33 ohm TPS73533DRB 2 DM {4} mini USB 5pin 3 R67 33 ohm DP {4} U2 L3 3 4 1 R68 2 1 8 1 2 4 5 0 Ohm, 0603 2 OUT IN 7 BK1608HS600-T 5 NC1 NC3 1 3 6 1 1 1 J10 6 7 R69 4 NR/FB NC2 5 C14 D1

6 5 4 PUR {4} JP4 1 GND PWPD EN U3 1.5K C13 + C15 1SMB5922 C16 + 6 7 1uF 9 2 2 SW2

2 2.2uF 0.01uF 22uF IO4 IO3 2 2014

4 VCC 4 C17 VUSB 2 2 R70 0.1uF 33K ohm 1 SPST Feedback IO1 IO2 GND TPD4E004DRY VSS R71 C18 VSS 1 2 3 1.2M ohm 220PF

VSS VSS VSS XTAL 24 MHz C19 Crystal, SMT Quart Crystal Y1 30pF C20 VSS

2 4 6 8 10 12 14 30pF J11 VDD_I2C HEADER 7X2_open {5} VDD_I2C C21 VDD33_UC JTAG VDDIO {3,5,6} VDDIO 1 3 5 7 9 VSS 11 13 220PF {3,5,6,7} VSS R72 VSS VUSB 33K ohm VBUS TDO TDI TMS TCK VSS ~RST DM {4} Copyright

PUR {4}

C22 DP {4} 2200PF

3 USB2ANY CONNECTOR 50 ohm single ended 3 impedance traces VSS ~RST TCK TDI TDO TEST1 I2C_SDA J12 {3,5,7} I2C_SDA 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

2014, GPIO2/SPI(SCLK) 3 4 GPIO3/PWM2 V18 PUR

VUSB VBUS VSSU 5 6 AVSS2 GPIO4/SPI(SIMO)/UART(TXD) 7 8 GPIO5/SPI(SOMI)/UART(RXD) PU.0/DP PU.1/DM PJ.3/TCK PJ.0/TDO PJ.2/TMS GPIO6/PWM1/SPI(CS) 9 10 GPIO7/PWM0 P5.2/XT2IN

1 P6.3/CB3/A3 P6.2/CB2/A2 P6.1/CB1/A1 P6.0/CB0/A0 60 AIN_B_0 P5.3/XT2OUT

P6.4/CB4/A4 PJ.1/TDI/TCLK P7.7/TB0CLK/MCLK TEST/SBWTCK 2 59 Texas AIN_B_1 P6.5/CB5/A5 P7.6/TB0.4 HEADER 5X2 3 ~RST/NMI/SBWTDIO 58 VSS GPIO9/ADC2 P6.6/CB6/A6 P7.5/TB0.3 GPIO4/SPI(SIMO)/UART(TXD) 4 57 GPIO8/ADC3 P6.7/CB7/A7 P7.4/TB0.2 GPIO5/SPI(SOMI)/UART(RXD) 5 56

Instruments P7.0/CB8/A12 P5.7/TB0.1 VDD33_UC 6 55 P7.1/CB9/A13 P5.6/TB0.0 GPIO3/PWM2 1 2 PDB_CTRL GPIO11/VEREF+ R73 7 54 0 Ohm,0402_open 2 P7.2/CB10/A14 P4.7/PM_NONE 2 C23 8 53 GPIO7/PWM0 1 R74 2 INTB_CTRL P7.3/CB11/A15 P4.6/PM_NONE 0.1uF 0 Ohm,0402_open 0603_green_LED 1 9 52 LED4 VSS P5.0/A8/VREF+/VeREF+ P4.5/PM_UCA1RXD/PM_UCA1SOMI VDD33_UC VDD33_UC 10 51 GPIO10/VEREF- P5.1/A9/VREF-/VeREF- P4.4/PM_UCA1TXD/PM_UCA1SIMO 50 ohm single ended 1

1 VOLTAGE LEVEL TRANSLATOR 11 50 impedance traces

Incorporated AVCC1 DVCC2 1

R75 12 49 C24 VDDIO U5 VDD33_UC P5.4/XIN MSP430F5529IPN DVSS2 13 48 0.1uF 2 P5.5/XOUT U4 P4.3/PM_UCB1CLK/PM_UCA1STE 2 220 220 Ohm,0402 14 47 {3,7} PDB PDB 1 R120 2 1 16 PDB_CTRL Q1 AVSS1 P4.2/PM_UCB1SOMI/PM_UCB1SCL 0 Ohm,0402_open 2 A1 B1 15 2 2 BSS138 15 46 {7} INTB INTB 3 VCCA VCCB 14 INTB_CTRL P8.0 P4.1/PM_UCB1SIMO/PM_UCB1SDA VSS 2 SS{7} SS 4 A2 B2 13 GPIO6/PWM1/SPI(CS) 2 16 45 C25{7} SPLK SPLK 5 A3 B3 12 GPIO2/SPI(SCLK) C26 P8.1 P4.0/PM_UCB1STE/PM_UCA1CLK A4 B4 0.1uF{7} MISO MISO 6 11 GPIO4/SPI(SIMO)/UART(TXD) 0.1uF 1 1 17 44 {7} MOSI MOSI 7 A5 B5 10 GPIO5/SPI(SOMI)/UART(RXD) VSS P8.2 P3.7/TB0OUTH/SVMOUT 2R76 10K 1 8 A6 B6 9 18 43 OE GND DVCC1 P3.6/TB0.6 2 1 C28 19 42 TXB0106IPWR C27 DVSS1 P3.5/TB0.5 VSS 0.1uF 4.7uF 20 41 1 2 VCORE P3.4/UCA0RXD/UCA0SOMI

C29 470nF VSS 50 ohm single ended impedance traces GPIO1/I2C(SCL) I2C LEVEL TRANSLATOR VDD_I2C VDD33_UC VSS GPIO0/I2C(SDA) U6

GPIO2/SPI(SCLK) GPIO0/I2C(SDA) 1 8 GPIO1/I2C(SCL) 2 SDA_B SCL_B 7 VDD33_UC 3 GND VCCB 6 2R77 10K 1 I2C_SDA 4 VDDA OE 5 I2C_SCL EVM P1.0/TA0CLK/ACLK P1.1/TA0.0 P1.2/TA0.1 P1.3/TA0.2 P1.4/TA0.3 P1.5/TA0.4 P1.6/TA1CLK/CBOUT P1.7/TA1.0 P2.0/TA1.1 P2.1/TA1.2 P2.2/TA2CLK/SMCLK P2.3/TA2.0 P2.4/TA2.1 P2.5/TA2.2 P2.6/RTCCLK/DMAE0 P2.7/UCB0STE/UCA0CLK P3.0/UCB0SIMO/UCB0SDA P3.1/UCB0SOMI/UCB0SCL P3.2/UCB0CLK/UCA0STE P3.3/UCA0TXD/UCA0SIMO SDA_A SCL_A 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 R78 R79 TCA9406DCUR 1.5K 1.5K 2 2 C30 C31

PCB 0.1uF 0.1uF 1 1 GPIO7/PWM0 SCLBRD

GPIO6/PWM1/SPI(CS) SDABRD

GPIO3/PWM2 Schematics 1 VSS 1

NOTE: Float p2.3, p2.5, and p2.6 on MSP430 for USB2ANY detection Appendix

Title USB Controller

Size Document Number Rev C DS90UBUH948_940-Q1EVM 1E

Date: Tuesday, September 16, 2014 Sheet 4of 8

33 A B C D E A 34 Appendix EVM A A B C D E

PCB VSS {3,4,6,7} VSS VDD33 {6,7} VDD33 VDD18 {6} VDD18 VDDIO {3,4,6} VDDIO Schematics 100 ohm diff pair. +/-5%. Resistors have to be placed close to U1. +/- 1 mil for all inter/intra pairs. Place at the board edge VDD_I2C

{4} VDD_I2C 1 1

1 1 TP1 J13 R81 R82 4 R80 TEST POINT TP 4.7K 4.7K 4 JP5 100_open 0603 0603 1 TP2 1.12mm 1 VDD33 0 Ohm R83 1 2 3 4 VSS TEST POINT 2 VDD_I2C 2 1 2 R841 2 2 I2C_SDA 2 Dp 1 I2C_SDA {3,4,7} 3 VDD18 C32 2 0 Ohm R851 I2C_SCL

1 1 I2C_SCL {3,4,7} 1 TP3 0402 pad 0.1uF 0 Ohm R86 J15 TX OUT TEST POINT JP6 1 C33 1 C34

D0-/CSI1_D3+ 2 100_open 1 2 Dn D0+/CSI1_D3- 3 4 D1-/CSI1_D2+ 1 TP4 VSS 4.7pF2 2 4.7pF 2 5 6 TEST POINT 1.12mm VDDIO VSS D0- 2 D1+/CSI1_D2- 7 8 D2-/CSI1_D1+

{3} D0- 1 External I2C connection D0+ 9 10 1 TP5 TP {3} D0+ D1- R88 D2+/CSI1_D1- 11 12 C1-/CSI1_D0+ TEST POINT {3} D1- D1+ 13 14 {3} D1+ 100_open C1+/CSI1_D0- D2- 15 16 D3-/CSI1_C+ 1 TP6 {3} D2- D2+ 17 18 TEST POINT {3} D2+ 2 D3+/CSI1_C- J14 CLK1- 19 20

{3} CLK1- 1

Copyright CLK1+ {3} CLK1+ D3- R89 2X10-Pin Header 1 2 BISTEN TESTEN {3} D3- BISTEN {3} D3+ VSS 50 ohm single ended 3 4 BISTC INT_B {3} D3+ 100_open BISTC {3} impedance traces 5 6 1R87 0 Ohm,0402_open2 VDDIO 7 8 D_GPIO3 D_GPIO3 {3}SS 2 VSS 9 10 D_GPIO2 D_GPIO2 {3}SPLK 1 11 12 D_GPIO1 D_GPIO1 {3}MISO 3 3 R90 VSS 13 14 D_GPIO0 D_GPIO0 {3}MOSI © 100_open 2014, HEADER 7X2 2

J17 1 2 GPIO0 GPIO0 {3}SDOUT Texas 0.5" 3 4 GPIO1 GPIO1 {3}SWC 5 6 I2S_DC I2S_DCDC {3} 7 8 I2S_DD I2S_DDDD {3} 100 ohm diff pair. +/-5%. 50 ohm single ended 9 10 1 R91 2 VDDIO impedance traces Resistors have to be placed close to U1. 11 12 0 Ohm,0402_open I2S_DB I2S_DBDB {3} Instruments +/- 1 mil for all inter/intra pairs. 13 14 I2S_DA I2S_DADA {3} 15 16 I2S_WC I2S_WCWC {3} 17 18 I2S_CLK I2S_CLKCLK {3} 1 TP8 VSS 19 20 MCLK MCLK {3}MCLK 1 TEST POINT 2X10-Pin Header R92 100_open 1 TP7 TEST POINT 2

Incorporated 1 TP9 1 TEST POINT J16 2 R93 TX OUT D4-/CSI0_D3+ 2 100_open 1 2 1 TP10 D4+/CSI0_D3- 3 4 D5-/CSI0_D2+ TEST POINT 5 6 D4- 2 D5+/CSI0_D2- 7 8 D6-/CSI0_D1+ 1 TP11

{3} D4- 1 D4+ 9 10 TEST POINT {3} D4+ D5- R94 D5+/CSI0_D1- 11 12 C2-/CSI0_D0+ {3} D5- D5+ 13 14 1 TP12 {3} D5+ 100_open C2+/CSI0_D0- D6- 15 16 D7-/CSI0_C+ TEST POINT {3} D6- D6+ 17 18 {3} D6+ 2 D7+/CSI0_C- CLK2- 19 20

{3} CLK2- 1 CLK2+ {3} CLK2+ D7- R95 2X10-Pin Header VSS {3} D7- D7+ {3} D7+ 100_open

2 VSS 1 R96 100_open Submit 2

1 1 Documentation SNLU165

Title Output and Termination

Size Document Number Rev B DS90UBUH948_940-Q1EVM 1E

– Date: Tuesday, September 16, 2014 Sheet 5of 8

October A B C D E www.ti.com Feedback 2014 Submit SNLU165 www.ti.com Documentation – October A B C D E VSS {3,4,5,7} VSS

2 VDD33 {5,7} VDD33 LED3

1 VDD_12.0V_EXTERNAL VSS VDD18 {5} VDD18

J18 2 +5V 2 R98 1 2 1 2014 2

3 U7 R97 220 Ohm,0402 0 Ohm,0402 0 1 CONN JACK PWR C35 21 0603_red_LED Feedback 0.1uF C36 0.022uF MAIN 1 1 20 1 2

12V INPUT VCC DAP BST JP7 POWER 2 19 L4 15uH 1 SD PRE CONNECTOR VSS C37 3 18 1 2 1 2 +5V 4 4 VIN SW 17 1 4 10uF 5 VIN SW 16 D3 2 6 SYNC IS_1 15 1 1 7 COMP IS_2 14 DIODE C38 + C39 + C401 C411 1 R99 2 1 8 FB PGND 13 0 Ohm, 0603 9 RT PGND 12 2 100uF 270uF 100uF 100uF

2 2 [email protected] POWER SUPPLY 10 RAMP OUT 11 2 2 R100 1 AGND SS 1 LM25576MH/NOPB

C42 C43 R102 U8 2 52.3Kohm 1 1 180pF 150pF TPS74801DRC R101 1 C44 3.09Kohm Layout note: mount +5V 1 10 1 R103 2 VDD12 IN OUT 2 1 C45 0 Ohm, 0603 2 2 2 2 9.53Kohm

1 C38, C39 on top side of 1 1 1 1 1 560pF MAIN POWER 0.01uF C46 C47 C48 2 9 C49 C50 JP8 2 board. IN OUT R104

2 4.7uF 1uF 0.1uF 2 R105 1 3 8 4.7uF 0.1uF 2 2 2 2 2 2 2 100K PG FB 1 R106 4 7 2.49K BIAS SS Copyright VSS VSS VSS 1K 1 R107 2 5 6 1 C51 2 VSS 1 0 Ohm,0402 EN GND VSS R108 1 PwPd 0.01uF 2 1 C52 1 C53 11 1 4.99K

2014, C54 C55 C56 C57 C58 Place near pin of U1 10uF 1uF 0.1uF 0.01uF 0.01uF VSS 2 2 2 2 2 VSS VSS

Texas +5V L6

1 1 1V8@1A POWER SUPPLY VDD12 VDD12_Pin33 C63 C64 U9 VDD12_Pin33 {3} 3V3@1A POWER SUPPLY FB 120@100MHz,0603 1 C59 1 C60 1 C61 1 C62 4.7uF 1uF 2 2 Instruments Place near pin of U1 2 1 VSS 10uF 1uF 0.1uF 0.01uF 1 28 2 R111 1 R110 23.2K VSS 2 2 2 2 VSS VSS 2 NC1 1RESET 27 100K 2 1 3 NC2 NC13 26 R112 12.1K 4 1GND NC12 25 L7 VDDP12_0 5 1EN 1FB/NC 24 1 R113 2 VDD18

VDDP12_0 {3} 1 VDD12 VDDR12_0 6 1IN 1OUT 23 0 Ohm, 0603

VDDR12_0 {3} 2 FB 120@100MHz,0603 7 1IN 1OUT 22 2 R114 1 C65 C66 JP9 1 C67 1 C68 1 C69 1 C70 1 C86 8 NC3 2RESET 21 100K Incorporated Place near pin of U1 9 NC4 TPS767D318PWP NC11 20 0.1uF 10uF 10uF 1uF 0.1uF 0.01uF 0.01uF 10 2GND NC10 19 1 2 2 2 2 2 2 2EN NC9 2 VSS 11 18 2 2 2 12 2IN 2OUT 17 13 2IN 2OUT 16 VSS L8 VDDP12_1 14 NC5 NC8 15 VDDP12_1 {3} VDD12 VDDR12_1 NC6 NC7 1 R117 2 VDD33

VDDR12_1 {3} 1 FB 120@100MHz,0603 0 Ohm, 0603 1 1 R115 Ohm,0402 0 R116 Ohm,0402 0 2 1 C71 1 C72 1 C73 1 C74 1 C87 C79 C80 JP10

Place near pin of U1 PWPD 10uF 1uF 0.1uF 0.01uF 0.01uF U9 0.1uF 10uF 1 2 2 2 2 2 2

VSS 29

L9 VSS VDD12 VDDL12c VDDL12c {3} FB 120@100MHz,0603 VSS 1 C75 1 C76 1 C77 1 C78 1 C95 Place near pin of U1 10uF 1uF 0.1uF 0.01uF 0.01uF VSS 2 2 2 2 2 VDDIO External input L11 VDDIO VDDIOc

1 1 VDDIOc {3} FB 1K@100MHz,0603 EVM 1 L10 VDD12_LVDS 1 C88 + C89 + 2 C90 1 C91 1 C92 1 C93 C94 VDD12_LVDS {3} VDD12 VDDP12_LVDS JP11 Place near pin of U1 VDDP12_LVDS {3} 1 FB 120@100MHz,0603 22uF 2.2uF 0.1uF 10uF 1uF 0.1uF 0.01uF 1 2 1 2 2 2 1 C81 1 C82 1 C83 1 C84 1 C85 VSS VSS 2 2 2

PCB Place near pin of U1 10uF 1uF 0.1uF 0.01uF 0.01uF VSS 2 2 2 2 2 JP12 VDD18 1 VDDIO=VDD18 Title VDDIO 2 Power and Decoupling Schematics {3,4,5} VDDIO VDD33 3 VDDIO=VDD33 Size Document Number Rev DS90UBUH948_940-Q1EVM 1E

Date: Tuesday, September 16, 2014 Sheet 6of 8 A B C D E Appendix 35 A 36 Appendix

A B C D E EVM

VSS A {3,4,5,6} VSS VDD33 TEST PCB {5,6} VDD33

VDD33 2 R118 2

Schematics 330ohm C99 4 J19 J20 0402 4

1 0.1uF 1 20 VSS 1 2 RST SW0 2 DVCC DVSS 19 SW4 VDD33 3 1 2 4 1 MISO 3 P1.0 P2.6 18 SW5 5 3 4 6 {4} MISO I2C_SDA MOSI 4 P1.1 P2.7 17 TEST TEST 7 5 6 8 {3,4,5} I2C_SDA {4} MOSI SS 5 P1.2 TEST 16 RST 9 7 8 10 VSS {4} SS I2C_SCL SPLK 6 P1.3 RST 15 I2C_SDA 11 9 10 12 {3,4,5} I2C_SCL {4} SPLK SW1 7 P1.4 SDA 14 I2C_SCL 13 11 12 14 SW2 8 P1.5 SCL 13 PDB 2 13 14 PDB {3,4} INTB 9 P2.0 P2.5 12 SW6 C100 JTAG-14 {4} INTB SW3 10 P2.1 P2.4 11 SW7 P2.2 P2.3 1 0.1uF

DIP20 SOCKET - MSP430G2403IN20 Copyright

1 4 3 2 1 2 SW0 47Kohm 3 4 SW1 0603 5 6 SW2 Texas 7 8 SW3 1

RST 9 5 10 SW4

11 6 12 SW5 Instruments

13 7 14 SW6 1

SW3 C101 15 8 16 SW7 RST 2.2nF SPST 2 SW SMD-8 VSS Incorporated

2 2 VSS VSS

Put RST switch at the bottom edge of the board.k downMar every Netname to the position

J21 1 2 RST 3 4 TEST Submit

2X2-Pin Header Documentation SNLU165

1 VSS 1

Title

– External MSP430 Controller October www.ti.com Size Document Number Rev Feedback A DS90UBUH948_940-Q1EVM 1E

Date: Tuesday, September 16, 2014 Sheet 7of 8 2014 A B C D E Appendix B SNLU165–October 2014

Board Layout

Board Layers

ART FILM - 01_TOP ART FILM - 02_GND

ART FILM - 01_TOP ART FILM - 02_GND Figure 1. Top Layer Figure 2. Ground Layer

ART FILM - 03_POWER ART FILM - 04_BOTTOM

ART FILM - 03_POWER ART FILM - 04_BOTTOM Figure 3. Power Layer Figure 4. Bottom Layer

ART FILM - BOTTOM-SILK

ART FILM - TOP-SILK

ART FILM - BOTTOM-SILK Figure 5. Top Silkscreen Figure 6. Bottom Silkscreen

SNLU165–October 2014 Board Layout 39 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated 40 Appendix ART FILM - FAB Board B Layout Copyright © 2014, Texas Instruments Incorporated Submit Documentation SNLU165 – October www.ti.com Feedback 2014

ART FILM - FAB STANDARD TERMS AND CONDITIONS FOR EVALUATION MODULES 1. Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, or documentation (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance with the terms and conditions set forth herein. Acceptance of the EVM is expressly subject to the following terms and conditions. 1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are not finished products. EVMs shall not be directly or indirectly assembled as a part or subassembly in any finished product. For clarification, any software or software tools provided with the EVM (“Software”) shall not be subject to the terms and conditions set forth herein but rather shall be subject to the applicable terms and conditions that accompany such Software 1.2 EVMs are not intended for consumer or household use. EVMs may not be sold, sublicensed, leased, rented, loaned, assigned, or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or production system.

2 Limited Warranty and Related Remedies/Disclaimers: 2.1 These terms and conditions do not apply to Software. The warranty, if any, for Software is covered in the applicable Software License Agreement. 2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM to User. Notwithstanding the foregoing, TI shall not be liable for any defects that are caused by neglect, misuse or mistreatment by an entity other than TI, including improper installation or testing, or for any EVMs that have been altered or modified in any way by an entity other than TI. Moreover, TI shall not be liable for any defects that result from User's design, specifications or instructions for such EVMs. Testing and other quality control techniques are used to the extent TI deems necessary or as mandated by government requirements. TI does not test all parameters of each EVM. 2.3 If any EVM fails to conform to the warranty set forth above, TI's sole liability shall be at its option to repair or replace such EVM, or credit User's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during the warranty period to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects to repair or replace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall be warranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) day warranty period.

3 Regulatory Notices: 3.1 United States 3.1.1 Notice applicable to EVMs not FCC-Approved: This kit is designed to allow product developers to evaluate electronic components, circuitry, or software associated with the kit to determine whether to incorporate such items in a finished product and software developers to write software applications for use with the end product. This kit is not a finished product and when assembled may not be resold or otherwise marketed unless all required FCC equipment authorizations are first obtained. Operation is subject to the condition that this product not cause harmful interference to licensed radio stations and that this product accept harmful interference. Unless the assembled kit is designed to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit must operate under the authority of an FCC license holder or must secure an experimental authorization under part 5 of this chapter. 3.1.2 For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant:

CAUTION This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment.

FCC Interference Statement for Class A EVM devices NOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instruction manual, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense. SPACER SPACER SPACER SPACER SPACER SPACER SPACER SPACER FCC Interference Statement for Class B EVM devices NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures: • Reorient or relocate the receiving antenna. • Increase the separation between the equipment and receiver. • Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. • Consult the dealer or an experienced radio/TV technician for help.

3.2 Canada 3.2.1 For EVMs issued with an Industry Canada Certificate of Conformance to RSS-210 Concerning EVMs Including Radio Transmitters: This device complies with Industry Canada license-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device.

Concernant les EVMs avec appareils radio: Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est autorisée aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.

Concerning EVMs Including Detachable Antennas: Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser) gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for successful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna types listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated. Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited for use with this device.

Concernant les EVMs avec antennes détachables Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage radioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope rayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Le présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le manuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne non inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de l'émetteur 3.3 Japan 3.3.1 Notice for EVMs delivered in Japan: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page 日本国内に輸入される評価用キット、ボードについては、次のところをご覧ください。 http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page

3.3.2 Notice for Users of EVMs Considered “Radio Frequency Products” in Japan: EVMs entering Japan are NOT certified by TI as conforming to Technical Regulations of Radio Law of Japan. If User uses EVMs in Japan, User is required by Radio Law of Japan to follow the instructions below with respect to EVMs: 1. Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for Enforcement of Radio Law of Japan, 2. Use EVMs only after User obtains the license of Test Radio Station as provided in Radio Law of Japan with respect to EVMs, or 3. Use of EVMs only after User obtains the Technical Regulations Conformity Certification as provided in Radio Law of Japan with respect to EVMs. Also, do not transfer EVMs, unless User gives the same notice above to the transferee. Please note that if User does not follow the instructions above, User will be subject to penalties of Radio Law of Japan. SPACER SPACER SPACER SPACER SPACER 【無線電波を送信する製品の開発キットをお使いになる際の注意事項】本開発キットは技術基準適合証明を受けておりません。本製品のご使用に際しては、電波法遵守のため、以下のいずれかの措置を取っていただく必要がありますのでご注意ください。 1. 電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用いただく。 2. 実験局の免許を取得後ご使用いただく。 3. 技術基準適合証明を取得後ご使用いただく。

なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。日本テキサス・インスツルメンツ株式会社東京都新宿区西新宿６丁目２４番１号西新宿三井ビル

3.3.3 Notice for EVMs for Power Line Communication: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page 電力線搬送波通信についての開発キットをお使いになる際の注意事項については、次のところをご覧ください。http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page SPACER 4 EVM Use Restrictions and Warnings: 4.1 EVMS ARE NOT FOR USE IN FUNCTIONAL SAFETY AND/OR SAFETY CRITICAL EVALUATIONS, INCLUDING BUT NOT LIMITED TO EVALUATIONS OF LIFE SUPPORT APPLICATIONS. 4.2 User must read and apply the user guide and other available documentation provided by TI regarding the EVM prior to handling or using the EVM, including without limitation any warning or restriction notices. The notices contain important safety information related to, for example, temperatures and voltages. 4.3 Safety-Related Warnings and Restrictions: 4.3.1 User shall operate the EVM within TI’s recommended specifications and environmental considerations stated in the user guide, other available documentation provided by TI, and any other applicable requirements and employ reasonable and customary safeguards. Exceeding the specified performance ratings and specifications (including but not limited to input and output voltage, current, power, and environmental ranges) for the EVM may cause personal injury or death, or property damage. If there are questions concerning performance ratings and specifications, User should contact a TI field representative prior to connecting interface electronics including input power and intended loads. Any loads applied outside of the specified output range may also result in unintended and/or inaccurate operation and/or possible permanent damage to the EVM and/or interface electronics. Please consult the EVM user guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative. During normal operation, even with the inputs and outputs kept within the specified allowable ranges, some circuit components may have elevated case temperatures. These components include but are not limited to linear regulators, switching transistors, pass transistors, current sense resistors, and heat sinks, which can be identified using the information in the associated documentation. When working with the EVM, please be aware that the EVM may become very warm. 4.3.2 EVMs are intended solely for use by technically qualified, professional electronics experts who are familiar with the dangers and application risks associated with handling electrical mechanical components, systems, and subsystems. User assumes all responsibility and liability for proper and safe handling and use of the EVM by User or its employees, affiliates, contractors or designees. User assumes all responsibility and liability to ensure that any interfaces (electronic and/or mechanical) between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electrical shock hazard. User assumes all responsibility and liability for any improper or unsafe handling or use of the EVM by User or its employees, affiliates, contractors or designees. 4.4 User assumes all responsibility and liability to determine whether the EVM is subject to any applicable international, federal, state, or local laws and regulations related to User’s handling and use of the EVM and, if applicable, User assumes all responsibility and liability for compliance in all respects with such laws and regulations. User assumes all responsibility and liability for proper disposal and recycling of the EVM consistent with all applicable international, federal, state, and local requirements.

5. Accuracy of Information: To the extent TI provides information on the availability and function of EVMs, TI attempts to be as accurate as possible. However, TI does not warrant the accuracy of EVM descriptions, EVM availability or other information on its websites as accurate, complete, reliable, current, or error-free. SPACER SPACER SPACER SPACER SPACER SPACER SPACER 6. Disclaimers: 6.1 EXCEPT AS SET FORTH ABOVE, EVMS AND ANY WRITTEN DESIGN MATERIALS PROVIDED WITH THE EVM (AND THE DESIGN OF THE EVM ITSELF) ARE PROVIDED "AS IS" AND "WITH ALL FAULTS." TI DISCLAIMS ALL OTHER WARRANTIES, EXPRESS OR IMPLIED, REGARDING SUCH ITEMS, INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF ANY THIRD PARTY PATENTS, COPYRIGHTS, TRADE SECRETS OR OTHER INTELLECTUAL PROPERTY RIGHTS. 6.2 EXCEPT FOR THE LIMITED RIGHT TO USE THE EVM SET FORTH HEREIN, NOTHING IN THESE TERMS AND CONDITIONS SHALL BE CONSTRUED AS GRANTING OR CONFERRING ANY RIGHTS BY LICENSE, PATENT, OR ANY OTHER INDUSTRIAL OR INTELLECTUAL PROPERTY RIGHT OF TI, ITS SUPPLIERS/LICENSORS OR ANY OTHER THIRD PARTY, TO USE THE EVM IN ANY FINISHED END-USER OR READY-TO-USE FINAL PRODUCT, OR FOR ANY INVENTION, DISCOVERY OR IMPROVEMENT MADE, CONCEIVED OR ACQUIRED PRIOR TO OR AFTER DELIVERY OF THE EVM.

7. USER'S INDEMNITY OBLIGATIONS AND REPRESENTATIONS. USER WILL DEFEND, INDEMNIFY AND HOLD TI, ITS LICENSORS AND THEIR REPRESENTATIVES HARMLESS FROM AND AGAINST ANY AND ALL CLAIMS, DAMAGES, LOSSES, EXPENSES, COSTS AND LIABILITIES (COLLECTIVELY, "CLAIMS") ARISING OUT OF OR IN CONNECTION WITH ANY HANDLING OR USE OF THE EVM THAT IS NOT IN ACCORDANCE WITH THESE TERMS AND CONDITIONS. THIS OBLIGATION SHALL APPLY WHETHER CLAIMS ARISE UNDER STATUTE, REGULATION, OR THE LAW OF TORT, CONTRACT OR ANY OTHER LEGAL THEORY, AND EVEN IF THE EVM FAILS TO PERFORM AS DESCRIBED OR EXPECTED.

8. Limitations on Damages and Liability: 8.1 General Limitations. IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL, OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF THESE TERMS ANDCONDITIONS OR THE USE OF THE EVMS PROVIDED HEREUNDER, REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO, COST OF REMOVAL OR REINSTALLATION, ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, RETESTING, OUTSIDE COMPUTER TIME, LABOR COSTS, LOSS OF GOODWILL, LOSS OF PROFITS, LOSS OF SAVINGS, LOSS OF USE, LOSS OF DATA, OR BUSINESS INTERRUPTION. NO CLAIM, SUIT OR ACTION SHALL BE BROUGHT AGAINST TI MORE THAN ONE YEAR AFTER THE RELATED CAUSE OF ACTION HAS OCCURRED. 8.2 Specific Limitations. IN NO EVENT SHALL TI'S AGGREGATE LIABILITY FROM ANY WARRANTY OR OTHER OBLIGATION ARISING OUT OF OR IN CONNECTION WITH THESE TERMS AND CONDITIONS, OR ANY USE OF ANY TI EVM PROVIDED HEREUNDER, EXCEED THE TOTAL AMOUNT PAID TO TI FOR THE PARTICULAR UNITS SOLD UNDER THESE TERMS AND CONDITIONS WITH RESPECT TO WHICH LOSSES OR DAMAGES ARE CLAIMED. THE EXISTENCE OF MORE THAN ONE CLAIM AGAINST THE PARTICULAR UNITS SOLD TO USER UNDER THESE TERMS AND CONDITIONS SHALL NOT ENLARGE OR EXTEND THIS LIMIT.

9. Return Policy. Except as otherwise provided, TI does not offer any refunds, returns, or exchanges. Furthermore, no return of EVM(s) will be accepted if the package has been opened and no return of the EVM(s) will be accepted if they are damaged or otherwise not in a resalable condition. If User feels it has been incorrectly charged for the EVM(s) it ordered or that delivery violates the applicable order, User should contact TI. All refunds will be made in full within thirty (30) working days from the return of the components(s), excluding any postage or packaging costs.

10. Governing Law: These terms and conditions shall be governed by and interpreted in accordance with the laws of the State of Texas, without reference to conflict-of-laws principles. User agrees that non-exclusive jurisdiction for any dispute arising out of or relating to these terms and conditions lies within courts located in the State of Texas and consents to venue in Dallas County, Texas. Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive relief in any United States or foreign court.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2014, Texas Instruments Incorporated spacer IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. 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