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NAND Flash Basics & Error Characteristics

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NAND Flash Basics & Error Characteristics NAND Flash Basics & Error Characteristics Why Do We Need Smart Controllers? Thomas Parnell, Roman Pletka IBM Research - Zurich Flash Memory Summit 2017 Santa Clara, CA 1 Agenda • Part I. NAND Flash Basics • Device Architecture (2D + 3D) • SLC, MLC & TLC • Program/Read/Erase Procedure • Part II. Error Characteristics • Program/erase cycling stress • Cell-to-cell Interference • Data Retention / Read Disturb • Programming Errors • 2D vs. 3D Reliability Comparison Flash Memory Summit 2017 Santa Clara, CA 2 Part I: NAND Flash Basics Flash Memory Summit 2017 Santa Clara, CA 3 Flash Fundamentals N-Channel MOSFET transistor ▪ Applying a gate-to-source voltage generates an electric field through insulator and creates a conduction channel through which current can pass from drain to source. Floating Gate N-Channel MOSFET ▪ The fundamental storage cell for Flash memory. ▪ Electrons can be stored onto and removed from the isolated floating gate (tunneling effect). ▪ Electrons residing on the floating gate remain there when power is removed ▪ The tunneling effect is destructive (e- get stuck in the insulator), hence limiting the number of program erase cycles. ▪ Electrons may “fall off” the floating gate over time, especially with Flash Memory Summit 2017 increased temperature. Santa Clara, CA 4 NAND Flash Architecture (2D) BL[0] BL[1] BL[2] BL[3] BL[N-2] BL[N-1] • A block of planar NAND Flash consists of WL[M-1] a grid of cells connected by word lines (WLs) and bit lines (BLs) WL[M-2] • Data is programmed/read from the device page-by-page (~16KB) • Every WL in the block contains: WL[2] • 1 page (SLC) • 2 pages (MLC) WL[1] • 3 pages (TLC) • Within a WL, pages can be further WL[0] interleaved so that each WL contains 2/4/6 pages (“Even-Odd BL Architecture”) Flash Memory Summit 2017 Santa Clara, CA 5 NAND Flash Architecture (3D) Layer L Layer 3 Layer 2 Layer 1 A block consists of vertically-stacked Each layer consists of a grid of cells layers of NAND Flash cells connected by WLs and BLS Flash Memory Summit 2017 Santa Clara, CA 6 Flash Memory Organization Multi-plane NAND Flash cell Erase operation operations 3D Architecture Source: Applied Materials Block Die 2015 512 – 1.5k 2 – 4 Pages Planes 32 – 96 Layers Page Plane Target 512 – 1024 16k+ Bytes 1/2/4/8 dies Blocks Read/write Data & cache Separate operations registers I/O Interfaces Flash Memory Summit 2017 Santa Clara, CA 7 SLC vs. MLC Upper Page Data Lower Page Data 1 0 0 1 1 0 1 1 0 0 VTH VTH Single Level Cell (SLC) Multi Level Cell (MLC) 2 States (1 Erase + 1 Pgm) 4 States (1 Erase + 3 Pgm) = 1 bit of information per cell = 2 bits of information per cell = 2x capacity of SLC! Flash Memory Summit 2017 Santa Clara, CA 8 TLC Extra Page Data Upper Page Data Lower Page Data 1 0 0 1 1 0 0 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 0 0 VTH Triple Level Cell (TLC) 8 States (1 Erase + 7 Pgm) = 3 bits of information per cell = 1.5x capacity of MLC = 3.0x capacity of SLC Flash Memory Summit 2017 Santa Clara, CA 9 Incremental Programming ISPP Procedure (a) Erased State START E VTH VTARG Electrons tunnel into FG Apply Programming (b) First Pulse programming pulse VTH FAIL … Verify most cells have VTARG VTH higher than VTARG (c) N PASS programming pulses V TH END tPROG~1500us Flash Memory Summit 2017 Santa Clara, CA 10 MLC Two-Pass Programming (a) Erased Data is programmed to the device State E VTH one page at a time LP=1 LP=0 VLPONLY The cells are either left in the erased (b) Program state of programmed to an Lower Page intermediate state depending on the x1 x0 V TH lower page data. UP=1 UP=0 UP=0 UP=1 An intermediate read determines the (c) Program previously programmed lower page Upper Page data and the cell distribution for the WL 11 01 00 10 V TH is “finalized” using the upper page data Flash Memory Summit 2017 Santa Clara, CA 11 Reading Data Back (MLC) Lower Page Read Upper Page Read VB VA VC Detect LP =1 Detect LP =0 Detect UP=1 Detect UP =0 Detect UP=1 11 01 00 10 VTH 11 01 00 10 VTH • Lower page can be read using a single read voltage (VB) • Upper page can be read using a pair of read voltages (VA,VC) • A page read typically takes up to 100us Flash Memory Summit 2017 Santa Clara, CA 12 Erasing Data is erased one block at a time. (a) Fully An individual page cannot be erased. prog. State VTH START VEV (b) First erase Apply Erase Pulse pulse VTH FAIL … Verify most cells have VEV VTH less than VEV (c) N erase PASS pulses VTH END tERASE~5000us Flash Memory Summit 2017 Santa Clara, CA 13 Part II: Error Characteristics Flash Memory Summit 2017 Santa Clara, CA 14 Read Errors • Broadening of VTH distributions due to noise can lead to read errors • What are the main sources of noise? VB VA VC Detect LP =1 Detect LP =0 Detect UP=1 Detect UP =0 Detect UP=1 11 01 00 10 11 01 00 10 VTH VTH Lower page read errors Upper page read errors Flash Memory Summit 2017 Santa Clara, CA 15 Program/Erase Cycling Stress • Repeated application of RBER of different flash blocks in the same device as a function of P/E cycles program/erase (P/E) pulses leads to degraded reliability of the underlying NAND flash cells 1 in 100 bits are in error • The measured raw bit error rate (RBER) increases as a function of P/E cycles • Low RBER at early life does not Different blocks exhibit indicate a good block, and an early different trajectories high RBER not a weak one! • Strong error-correction codes must be implemented on the controller to be able to deal with increased RBER Flash Memory Summit 2017 Santa Clara, CA 16 Cell-to-Cell Interference • Threshold voltage of “victim” cell is strongly affected by programming of neighboring “aggressor” cells can the controller compensate? 11 10 X 11 i , j 11 10 10 11 10 Flash Memory Summit 2017 Santa Clara, CA 17 Data Retention • Over time electrons can escape Before Data Retention from the programmed flash 2 Months @ 40C cells, causing a loss of threshold voltage • This can cause a large increase in RBER unless the controller can shift the read voltage to compensate for charge loss • The data retention effect is temperature dependent (charge escapes faster at higher temperature) Flash Memory Summit 2017 Santa Clara, CA 18 Read Disturb Before Read Disturb After N Reads • When reading a particular page in a block of NAND Flash, a voltage is applied to all other WL in order to “deselect” them • This applied voltage can affect the VTH distributed of the unselected WLs • If a block is read from too many times, the RBER will increase to a point that the ECC is no longer able to correct • The controller must be able to manage such effects Dominant effect of read disturb is seen on Erase state Flash Memory Summit 2017 Santa Clara, CA 19 Programming Errors • Degradation of erase state can cause error propagation during the two- pass programming procedure switch to 1-pass? Cells are programmed to the wrong state! Flash Memory Summit 2017 Santa Clara, CA 20 2D vs. 3D Reliability Scorecard Reliability Issue 2D 3D Comment TLC endurance: TLC endurance: Increased cell dimensions enable Program/Erase Cycling ~100 cycles >1000 cycles new applications for TLC Flash Cell-to-cell Interference X/Y-direction Z-direction Controller management required Years (consumer) Fast Initial Data Retention Controller management required Months (enterprise) Charge Loss Read Disturb Affects both Controller management required Improved algorithm can remove Programming Errors 2-pass programming 1-pass programming programming errors entirely Flash Memory Summit 2017 Santa Clara, CA 21 Conclusions • NAND Flash is currently unrivalled technology in terms of the performance/cost trade-off • However, it is inherently unreliable and cannot be used without a controller providing additional functionality • What do we require of a controller? • Media management / signal processing • Powerful error-correction • Data placement and garbage collection algorithms • Wear-leveling algorithms • Efficient FPGA/ASIC/firmware implementations Flash Memory Summit 2017 Santa Clara, CA 22.
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