MIPS R-format Instructions
op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits n Instruction fields
n op: operation code (opcode)
n rs: first source register number
n rt: second source register number
n rd: destination register number
n shamt: shift amount (00000 for now)
n funct: function code (extends opcode)
Chapter 2 — Instructions: Language of the Computer — 1 R-format Example
op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
add $t0, $s1, $s2
special $s1 $s2 $t0 0 add
0 17 18 8 0 32
000000 10001 10010 01000 00000 100000
000000100011001001000000001000002 = 0232402016
Chapter 2 — Instructions: Language of the Computer — 2 MIPS I-format Instructions
op rs rt constant or address 6 bits 5 bits 5 bits 16 bits n Immediate arithmetic and load/store instructions
n rt: destination or source register number 15 15 n Constant: –2 to +2 – 1 n Address: offset added to base address in rs n Design Principle 4: Good design demands good compromises
n Different formats complicate decoding, but allow 32-bit instructions uniformly n Keep formats as similar as possible
Chapter 2 — Instructions: Language of the Computer — 3 Branch Addressing n Branch instructions specify
n Opcode, two registers, target address n Most branch targets are near branch
n Forward or backward
op rs rt constant or address 6 bits 5 bits 5 bits 16 bits
n PC-relative addressing
n Target address = PC + offset × 4
n PC already incremented by 4 by this time
Chapter 2 — Instructions: Language of the Computer — 4 Jump Addressing n Jump (j and jal) targets could be anywhere in text segment
n Encode full address in instruction
op address 6 bits 26 bits n (Pseudo)Direct jump addressing
n Target address = PC31…28 : (address × 4)
Chapter 2 — Instructions: Language of the Computer — 5 Addressing Mode Summary
Chapter 2 — Instructions: Language of the Computer — 6 §2.11 Instructions: Synchronization and Parallelism Synchronization
n Two processors sharing an area of memory n P1 writes, then P2 reads n Data race if P1 and P2 don’t synchronize n Result depends of order of accesses n Hardware support required n Atomic read/write memory operation n No other access to the location allowed between the read and write n Could be a single instruction n E.g., atomic swap of register ↔ memory n Or an atomic pair of instructions
Chapter 2 — Instructions: Language of the Computer — 7 Synchronization in MIPS n Load linked: ll rt, offset(rs) n Store conditional: sc rt, offset(rs) n Succeeds if location not changed since the ll n Returns 1 in rt n Fails if location is changed n Returns 0 in rt n Example: atomic swap (to test/set lock variable) try: add $t0,$zero,$s4 ;copy exchange value ll $t1,0($s1) ;load linked sc $t0,0($s1) ;store conditional beq $t0,$zero,try ;branch store fails add $s4,$zero,$t1 ;put load value in $s4
Chapter 2 — Instructions: Language of the Computer — 8 §2.16 Real Stuff: Real §2.16 ARM Instructions ARM & MIPS Similarities n ARM: the most popular embedded core n Similar basic set of instructions to MIPS
ARM MIPS Date announced 1985 1985 Instruction size 32 bits 32 bits Address space 32-bit flat 32-bit flat Data alignment Aligned Aligned Data addressing modes 9 3 Registers 15 × 32-bit 31 × 32-bit Input/output Memory Memory mapped mapped
Chapter 2 — Instructions: Language of the Computer — 9 Compare and Branch in ARM n Uses condition codes for result of an arithmetic/logical instruction
n Negative, zero, carry, overflow
n Compare instructions to set condition codes without keeping the result n Each instruction can be conditional
n Top 4 bits of instruction word: condition value
n Can avoid branches over single instructions
Chapter 2 — Instructions: Language of the Computer — 10 Instruction Encoding
Chapter 2 — Instructions: Language of the Computer — 11 §2.17 Real Stuff: Real §2.17 Instructions x86 The Intel x86 ISA n Evolution with backward compatibility
n 8080 (1974): 8-bit microprocessor
n Accumulator, plus 3 index-register pairs
n 8086 (1978): 16-bit extension to 8080
n Complex instruction set (CISC)
n 8087 (1980): floating-point coprocessor
n Adds FP instructions and register stack
n 80286 (1982): 24-bit addresses, MMU
n Segmented memory mapping and protection
n 80386 (1985): 32-bit extension (now IA-32)
n Additional addressing modes and operations
n Paged memory mapping as well as segments
Chapter 2 — Instructions: Language of the Computer — 12 The Intel x86 ISA n Further evolution… n i486 (1989): pipelined, on-chip caches and FPU
n Compatible competitors: AMD, Cyrix, … n Pentium (1993): superscalar, 64-bit datapath
n Later versions added MMX (Multi-Media eXtension) instructions n The infamous FDIV bug n Pentium Pro (1995), Pentium II (1997)
n New microarchitecture (see Colwell, The Pentium Chronicles) n Pentium III (1999)
n Added SSE (Streaming SIMD Extensions) and associated registers n Pentium 4 (2001)
n New microarchitecture
n Added SSE2 instructions
Chapter 2 — Instructions: Language of the Computer — 13 The Intel x86 ISA n And further… n AMD64 (2003): extended architecture to 64 bits n EM64T – Extended Memory 64 Technology (2004)
n AMD64 adopted by Intel (with refinements)
n Added SSE3 instructions n Intel Core (2006)
n Added SSE4 instructions, virtual machine support n AMD64 (announced 2007): SSE5 instructions
n Intel declined to follow, instead… n Advanced Vector Extension (announced 2008) n Longer SSE registers, more instructions n If Intel didn’t extend with compatibility, its competitors would! n Technical elegance ≠ market success
Chapter 2 — Instructions: Language of the Computer — 14 x86 Instruction Encoding
n Variable length encoding
n Postfix bytes specify addressing mode
n Prefix bytes modify operation
n Operand length, repetition, locking, …
Chapter 2 — Instructions: Language of the Computer — 15 §2.18 Fallacies and Pitfalls Pitfalls and Fallacies §2.18 Fallacies n Powerful instruction ⇒ higher performance
n Fewer instructions required
n But complex instructions are hard to implement
n May slow down all instructions, including simple ones
n Compilers are good at making fast code from simple instructions n Use assembly code for high performance
n But modern compilers are better at dealing with modern processors
n More lines of code ⇒ more errors and less productivity
Chapter 2 — Instructions: Language of the Computer — 16 Fallacies n Backward compatibility ⇒ instruction set doesn’t change
n But they do accrete more instructions
x86 instruction set
Chapter 2 — Instructions: Language of the Computer — 17 Concluding Remarks
n Measure MIPS instruction executions in benchmark programs
n Consider making the common case fast
n Consider compromises
Instruction class MIPS examples SPEC2006 Int SPEC2006 FP Arithmetic add, sub, addi 16% 48% Data transfer lw, sw, lb, lbu, 35% 36% lh, lhu, sb, lui Logical and, or, nor, andi, 12% 4% ori, sll, srl Cond. Branch beq, bne, slt, 34% 8% slti, sltiu Jump j, jr, jal 2% 0%
Chapter 2 — Instructions: Language of the Computer — 18 Chapter 3
Arithmetic for Computers §3.1 Introduction Introduction §3.1 Arithmetic for Computers n Operations on integers
n Addition and subtraction
n Multiplication and division
n Dealing with overflow n Floating-point real numbers
n Representation and operations
Chapter 3 — Arithmetic for Computers — 20 §3.2 §3.2 Subtraction and Addition Integer Addition n Example: 7 + 6
n Overflow if result out of range
n Adding +ve and –ve operands, no overflow
n Adding two +ve operands
n Overflow if result sign is 1
n Adding two –ve operands
n Overflow if result sign is 0
Chapter 3 — Arithmetic for Computers — 21 Integer Subtraction n Add negation of second operand n Example: 7 – 6 = 7 + (–6) +7: 0000 0000 … 0000 0111 –6: 1111 1111 … 1111 1010 +1: 0000 0000 … 0000 0001 n Overflow if result out of range
n Subtracting two +ve or two –ve operands, no overflow
n Subtracting +ve from –ve operand
n Overflow if result sign is 0
n Subtracting –ve from +ve operand
n Overflow if result sign is 1
Chapter 3 — Arithmetic for Computers — 22 Dealing with Overflow n Some languages (e.g., C) ignore overflow
n Use MIPS addu, addui, subu instructions n Other languages (e.g., Ada, Fortran) require raising an exception
n Use MIPS add, addi, sub instructions
n On overflow, invoke exception handler
n Save PC in exception program counter (EPC) register
n Jump to predefined handler address
n mfc0 (move from coprocessor reg) instruction can retrieve EPC value, to return after corrective action
Chapter 3 — Arithmetic for Computers — 23 Other Adders n BASICS of ADDING LOGIC
n Carry-out
n Sum Generation
n Ripple Add n Carry Bypass n Carry Select n Carry Lookahead
Chapter 3 — Arithmetic for Computers — 24 The Ripple-Carry Adder
A0 B0 A1 B1 A2 B2 A3 B3
Ci,0 Co,0 Co,1 Co,2 Co,3 FA FA FA FA (= Ci,1)
S0 S1 S2 S3
Worst case delay linear with the number of bits
td = O(N)
tadder = (N-1)tcarry + tsum
Goal: Make the fastest possible carry path circuit
25 Carry-Bypass Adder
P0 G1 P0 G1 P2 G2 P3 G3 Also called Carry-Skip Ci,0 Co,0 Co,1 Co,2 Co,3 FA FA FA FA
P0 G1 P0 G1 P2 G2 P3 G3 BP=PoP1P2P3
Ci,0 Co,0 Co,1 Co,2 r
FA FA FA FA e x e
l Co,3 p i t l u M
Idea: If (P0 and P1 and P2 and P3 = 1) then Co3 = C0, else “kill” or “generate”.
26 Linear Carry Select
Bit 0-3 Bit 4-7 Bit 8-11 Bit 12-15
Setup Setup Setup Setup
(1)
"0" Carry "0" Carry "0" Carry "0" Carry "0" "0" "0" "0" (1)
"1" Carry "1" Carry "1" Carry "1" Carry "1" "1" "1" "1" (5) (5) (5) (5) (5) (6) (7) (8) Multiplexer Multiplexer Multiplexer Multiplexer Ci,0 (9)
Sum Generation Sum Generation Sum Generation Sum Generation
S0-3 S4-7 S8-11 S12-15 (10)
27 LookAhead - Basic Idea
A0, B0 A1, B1 • • • AN-1, BN-1
Ci,0 P Ci,1 P 0 1 C i, N-1 PN-1
S0 S1 • • • SN-1
Cok, ==fA()k,,Bk Cok, – 1 Gk + PkCok, – 1
28 Look-Ahead: Topology
Expanding Lookahead equations: VDD Cok, = Gk + Pk ()Gk1– + Pk1– Cok, – 2 G3
G2
All the way: G1 C = G + P ()G + P ()… + P ()G + P C ok, k k k1– k1– 1 0 0 i0, G0
Ci,0 Co,3
P0
P1
P2
P3
29 Carry Lookahead Trees
Co0, = G0 + P0Ci0,
Co1, = G1 ++P1 G0 P1P0 Ci0,
Co2, = G2 ++P2G1 P2 P1G0 + P2 P1P0Ci0,
= ()G2 + P2G1 + ()P2P1 ()G0 + P0Ci0, = G 2:1 + P2:1Co0,
Can continue building the tree hierarchically.
30 §3.3 Multiplication Multiplication §3.3 Multiplication
n Start with long-multiplication approach multiplicand 1000 multiplier × 1001 1000 0000 0000 1000 product 1001000
Length of product is the sum of operand lengths
Chapter 3 — Arithmetic for Computers — 31 Multiplication Hardware
Initially 0
Chapter 3 — Arithmetic for Computers — 32 Optimized Multiplier (ignore) n Perform steps in parallel: add/shift
n One cycle per partial-product addition
n That’s ok, if frequency of multiplications is low
Chapter 3 — Arithmetic for Computers — 33 Faster Multiplier n Uses multiple adders
n Cost/performance tradeoff
n Can be pipelined
n Several multiplication performed in parallel
Chapter 3 — Arithmetic for Computers — 34 MIPS Multiplication n Two 32-bit registers for product
n HI: most-significant 32 bits
n LO: least-significant 32-bits n Instructions
n mult rs, rt / multu rs, rt
n 64-bit product in HI/LO
n mfhi rd / mflo rd
n Move from HI/LO to rd
n Can test HI value to see if product overflows 32 bits
n mul rd, rs, rt
n Least-significant 32 bits of product –> rd
Chapter 3 — Arithmetic for Computers — 35 §3.4 Division Division §3.4 Division (IGNORE THIS)
n Check for 0 divisor n Long division approach quotient n If divisor ≤ dividend bits dividend n 1 bit in quotient, subtract 1001 n Otherwise 1000 1001010 n 0 bit in quotient, bring down next -1000 dividend bit divisor 10 n Restoring division
101 n Do the subtract, and if remainder 1010 goes < 0, add divisor back -1000 n Signed division remainder 10 n Divide using absolute values
n Adjust sign of quotient and remainder n-bit operands yield n-bit as required quotient and remainder
Chapter 3 — Arithmetic for Computers — 36 §3.5 Floating Point Point Floating §3.5 Floating Point n Representation for non-integral numbers
n Including very small and very large numbers n Like scientific notation 56 n –2.34 × 10 normalized –4 n +0.002 × 10 not normalized 9 n +987.02 × 10 n In binary yyyy n ±1.xxxxxxx2 × 2 n Types float and double in C
Chapter 3 — Arithmetic for Computers — 37 Floating Point Standard n Defined by IEEE Std 754-1985 n Developed in response to divergence of representations
n Portability issues for scientific code n Now almost universally adopted n Two representations
n Single precision (32-bit)
n Double precision (64-bit)
Chapter 3 — Arithmetic for Computers — 38 IEEE Floating-Point Format
single: 8 bits single: 23 bits double: 11 bits double: 52 bits S Exponent Fraction
x = (−1)S ×(1+Fraction)×2(Exponent−Bias) n S: sign bit (0 ⇒ non-negative, 1 ⇒ negative) n Normalize significand: 1.0 ≤ |significand| < 2.0 n Always has a leading pre-binary-point 1 bit, so no need to represent it explicitly (hidden bit) n Significand is Fraction with the “1.” restored n Exponent: excess representation: actual exponent + Bias n Ensures exponent is unsigned n Single: Bias = 127; Double: Bias = 1203
Chapter 3 — Arithmetic for Computers — 39 Single-Precision Range n Exponents 00000000 and 11111111 reserved n Smallest value
n Exponent: 00000001 ⇒ actual exponent = 1 – 127 = –126
n Fraction: 000…00 ⇒ significand = 1.0 –126 –38 n ±1.0 × 2 ≈ ±1.2 × 10 n Largest value
n exponent: 11111110 ⇒ actual exponent = 254 – 127 = +127
n Fraction: 111…11 ⇒ significand ≈ 2.0 +127 +38 n ±2.0 × 2 ≈ ±3.4 × 10
Chapter 3 — Arithmetic for Computers — 40 Double-Precision Range n Exponents 0000…00 and 1111…11 reserved n Smallest value
n Exponent: 00000000001 ⇒ actual exponent = 1 – 1023 = –1022
n Fraction: 000…00 ⇒ significand = 1.0 –1022 –308 n ±1.0 × 2 ≈ ±2.2 × 10 n Largest value
n Exponent: 11111111110 ⇒ actual exponent = 2046 – 1023 = +1023
n Fraction: 111…11 ⇒ significand ≈ 2.0 +1023 +308 n ±2.0 × 2 ≈ ±1.8 × 10
Chapter 3 — Arithmetic for Computers — 41 Floating-Point Precision n Relative precision
n all fraction bits are significant –23 n Single: approx 2
n Equivalent to 23 × log102 ≈ 23 × 0.3 ≈ 6 decimal digits of precision –52 n Double: approx 2
n Equivalent to 52 × log102 ≈ 52 × 0.3 ≈ 16 decimal digits of precision
Chapter 3 — Arithmetic for Computers — 42 Floating-Point Example n Represent –0.75 1 –1 n –0.75 = (–1) × 1.12 × 2 n S = 1
n Fraction = 1000…002 n Exponent = –1 + Bias
n Single: –1 + 127 = 126 = 011111102
n Double: –1 + 1023 = 1022 = 011111111102 n Single: 1011111101000…00 n Double: 1011111111101000…00
Chapter 3 — Arithmetic for Computers — 43 Floating-Point Example n What number is represented by the single- precision float 11000000101000…00
n S = 1
n Fraction = 01000…002 n Fxponent = 100000012 = 129 1 (129 – 127) n x = (–1) × (1 + 012) × 2 = (–1) × 1.25 × 22 = –5.0
Chapter 3 — Arithmetic for Computers — 44 Denormal Numbers n Exponent = 000...0 ⇒ hidden bit is 0 x = (−1)S ×(0+Fraction)×2−Bias n Smaller than normal numbers
n allow for gradual underflow, with diminishing precision n Denormal with fraction = 000...0 x = (−1)S ×(0+ 0)×2−Bias = ±0.0
Two representations of 0.0!
Chapter 3 — Arithmetic for Computers — 45 Infinities and NaNs n Exponent = 111...1, Fraction = 000...0
n ±Infinity
n Can be used in subsequent calculations, avoiding need for overflow check n Exponent = 111...1, Fraction ≠ 000...0
n Not-a-Number (NaN)
n Indicates illegal or undefined result
n e.g., 0.0 / 0.0
n Can be used in subsequent calculations
Chapter 3 — Arithmetic for Computers — 46 Floating-Point Addition (IGNORE) n Consider a 4-digit decimal example 1 –1 n 9.999 × 10 + 1.610 × 10 n 1. Align decimal points
n Shift number with smaller exponent 1 1 n 9.999 × 10 + 0.016 × 10 n 2. Add significands 1 1 1 n 9.999 × 10 + 0.016 × 10 = 10.015 × 10 n 3. Normalize result & check for over/underflow 2 n 1.0015 × 10 n 4. Round and renormalize if necessary 2 n 1.002 × 10
Chapter 3 — Arithmetic for Computers — 47 FP Adder Hardware (ignore)
Step 1
Step 2
Step 3
Step 4
Chapter 3 — Arithmetic for Computers — 48 Floating-Point Multiplication (ignore) n Consider a 4-digit decimal example 10 –5 n 1.110 × 10 × 9.200 × 10 n 1. Add exponents
n For biased exponents, subtract bias from sum
n New exponent = 10 + –5 = 5 n 2. Multiply significands 5 n 1.110 × 9.200 = 10.212 ⇒ 10.212 × 10 n 3. Normalize result & check for over/underflow 6 n 1.0212 × 10 n 4. Round and renormalize if necessary 6 n 1.021 × 10 n 5. Determine sign of result from signs of operands 6 n +1.021 × 10
Chapter 3 — Arithmetic for Computers — 49 FP Arithmetic Hardware (ignore) n FP multiplier is of similar complexity to FP adder
n But uses a multiplier for significands instead of an adder n FP arithmetic hardware usually does
n Addition, subtraction, multiplication, division, reciprocal, square-root n FP ↔ integer conversion n Operations usually takes several cycles
n Can be pipelined
Chapter 3 — Arithmetic for Computers — 50 FP Instructions in MIPS n Single-precision arithmetic n add.s, sub.s, mul.s, div.s
n e.g., add.s $f0, $f1, $f6 n Double-precision arithmetic n add.d, sub.d, mul.d, div.d
n e.g., mul.d $f4, $f4, $f6 n Single- and double-precision comparison n c.xx.s, c.xx.d (xx is eq, lt, le, …) n Sets or clears FP condition-code bit
n e.g. c.lt.s $f3, $f4 n Branch on FP condition code true or false n bc1t, bc1f
n e.g., bc1t TargetLabel
Chapter 3 — Arithmetic for Computers — 51 FP Example: °F to °C n C code: float f2c (float fahr) { return ((5.0/9.0)*(fahr - 32.0)); }
n fahr in $f12, result in $f0, literals in global memory space n Compiled MIPS code: f2c: lwc1 $f16, const5($gp) lwc2 $f18, const9($gp) div.s $f16, $f16, $f18 lwc1 $f18, const32($gp) sub.s $f18, $f12, $f18 mul.s $f0, $f16, $f18 jr $ra
Chapter 3 — Arithmetic for Computers — 52 Accurate Arithmetic n IEEE Std 754 specifies additional rounding control
n Extra bits of precision (guard, round, sticky)
n Choice of rounding modes
n Allows programmer to fine-tune numerical behavior of a computation n Not all FP units implement all options
n Most programming languages and FP libraries just use defaults n Trade-off between hardware complexity, performance, and market requirements
Chapter 3 — Arithmetic for Computers — 53 §3.7 Real Stuff: Real §3.7 the x86 in Point Floating x86 FP Architecture (ignore) n Originally based on 8087 FP coprocessor
n 8 × 80-bit extended-precision registers
n Used as a push-down stack
n Registers indexed from TOS: ST(0), ST(1), … n FP values are 32-bit or 64 in memory
n Converted on load/store of memory operand
n Integer operands can also be converted on load/store n Very difficult to generate and optimize code
n Result: poor FP performance
Chapter 3 — Arithmetic for Computers — 54 x86 FP Instructions (ignore)
Data transfer Arithmetic Compare Transcendental FILD mem/ST(i) FIADDP mem/ST(i) FICOMP FPATAN FISTP mem/ST(i) FISUBRP mem/ST(i) FIUCOMP F2XMI FLDPI FIMULP mem/ST(i) FSTSW AX/mem FCOS FLD1 FIDIVRP mem/ST(i) FPTAN FLDZ FSQRT FPREM FABS FPSIN FRNDINT FYL2X n Optional variations n I: integer operand n P: pop operand from stack n R: reverse operand order n But not all combinations allowed
Chapter 3 — Arithmetic for Computers — 55 Who Cares About FP Accuracy? n Important for scientific code
n But for everyday consumer use?
n “My bank balance is out by 0.0002¢!” L n The Intel Pentium FDIV bug
n The market expects accuracy
n See Colwell, The Pentium Chronicles
Chapter 3 — Arithmetic for Computers — 56 §3.9 Concluding Remarks Remarks Concluding §3.9 Concluding Remarks n ISAs support arithmetic
n Signed and unsigned integers
n Floating-point approximation to reals n Bounded range and precision
n Operations can overflow and underflow n MIPS ISA
n Core instructions: 54 most frequently used
n 100% of SPECINT, 97% of SPECFP
n Other instructions: less frequent
Chapter 3 — Arithmetic for Computers — 57