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Doctoral Thesis Doctoral Thesis A study on interface traps and near interfacial bulk traps at the interfaces of dielectric/semiconductor and semiconductor heterojunction 誘電体/半導体と半導体ヘテロ接合界面における界面トラップおよび 界面近傍のバルクトラップに関する研究 by Chunmeng Dou Supervisor: Prof. Hiroshi Iwai, Co-supervisor: Associate Prof. Kuniyuki Kakushima A dissertation submitted to Department of Electronics and Applied Physics, Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology for the degree of doctor of engineering February, 2014 Acknowledgements First and foremost, I would like to express deepest gratitude to my advisor Prof. Hiroshi Iwai from Tokyo Institute of Technology (TIT) for all of his dedicated guidance and attentive support on my studies and life. He also provides me many invaluable chances for participating research program in world-leading universities/institutes outside TIT, which greatly broaden my horizon and deepen my interest on my research field. I am also deeply indebted to Associate Prof. Kuniyuki Kakushima of TIT, who intelligently and patiently guides me to overcome many crucial challenges in my laboratory studies and daily life through my Ph.D. journey. Likewise, I am very grateful to Prof. Takeo Hattori, Prof. Kenji Natori, Prof. Kazuo Tsutsui, Prof. Hiroshi Wakabayashi, Prof. Nobuyuki Sugii, Prof. Akira Nishiyama, Prof. Yoshinori Kataoka, and Prof. Parhat Ahmet from TIT for their tireless mentoring and valuable advices. Besides, I sincerely acknowledge Prof. Keisaku Yamada, Prof. Kenji Ohmori, Prof. Masaaki Niwa, and Dr. Wei Feng from Tsukuba University for their strong guidance on fabrication and characterization multi-gate MOSFETs devices after I joined the Tsukuba Nanotechnology Human Resource Development Program (honors graduate program), Tsukuba University. Additionally, I would like to express my appreciation to Prof. Guido Groeseneken, Dr. Aaron Thean, Dr. Dennis Lin from IMEC and Prof. Yuan Taur from University of California, San Diego, for their cordial guidance on characterizing the oxide traps in III-V MOS capacitors during my intern at IMEC. I also indebted to many members of the LDD team of IMEC for many fruitful discussions and kind assistance. I also significantly benefited from the kindest help from Ms. Akiko Matsumoto and Ms. i Masako Nishizawa from Iwai/Kakushima laboratories, Prof. Yogaku Iwamoto, and Ms. Yumiko Yuzawa from the Innovative Platform for Education and Research (IPER) of TIT, Prof. Kikuo Yamabe, Prof. Kiyoshi Asakawa, Prof. Yasuhiro Horiike, Ms. Namiko Suzuki, Ms. Midori Hirano, and Mr. Masaya Oouchi from the honors graduate program of Tsukuba University. Due to their kind arrangements, I could conduct my studies smoothly at TIT and Tsukuba University, and also participate in an intern at IMEC. I would also like to thank Dr. Daniel Berrar from IPER of TIT for proofreading my journal publications. I would also like to express my deep gratitude to all of other research staff and student members in Iwai/Kakushima Lab for their help from many aspects, and I will always recall my time at Japan with fondness. I would also like to gratefully appreciate Prof. Ming Liu (The Institute of Microelectronics of Chinese Academy of Sciences), Prof. Yi Shi (Nanjing University), Prof. Zhenchao Dong (University of Science and Technology of China), Prof. Hei Wong (City University of Hong Kong), for evaluating the qualification of this thesis and their valuable advices. Lastly, many thanks to my parents and all of my family members for their constant support and firm encouragement. ii Abstract In order to avoid CMOS down-scaling limit due to the short-channel effect, multi-gate structure, such as fin-FETs or Tri-gate has been introduced. In addition, MOSFETs with new channel materials such as InGaAs (III-V) and Ge are studied for low power application under low voltage. Also, HEMT (High Electron Mobility Transistor) devices using AlGaN/GaN hetero-junction for the channel are being developed for power and high- frequency applications. For the development of these emerging device technologies, it is important to accurately evaluate the distribution of interface and near-interface traps at the gate dielectrics/semiconductor interfaces and the semiconductor hetero-junction interfaces and thus, to understand the behavior of those traps. In this thesis, the results of the systematic studies for the distribution of interface and near-nterface traps at SiO2/Si interfaces with fin structure, high-k/InGaAs interfaces, and AlGaN/GaN hetero-interfaces are described. We have proposed methodologies for trap characterization and revealed in-depth understanding of the distributions, origins, species, and trapping mechanisms. These methodologies and discoveries can be also easily extended for studying other dielectric/semiconductor interfaces and semiconductor hetero-interfaces, and thus provide a guideline for trap characterization for future development of advanced FETs. In particular, following characterizing methodologies were proposed: (1) extraction of trap densities in the different regions of fin surface by the measurement of trap densities with different fin width, (2) extraction of near-interface traps (or border traps) for high-k/III-V MOS structures, from the C-V characteristics measured at different temperatures, and (3) extraction of the distribution and species of the interface traps by comparative study on conductance spectra of AlGaN/GaN hetero-junctions with different electrodes. The major results are listed as follows; At the SiO2/Si interface with fin structure, a high concentration of interface traps tend to locate at the corners. In high-k/III-V MOS systems, there are a large amount of electrically active oxide border traps, whose concentration is likely to increase with increasing energy level and distance from the interface into the oxide. These traps seem to be caused by accumulated defectives during high-k material growth. Besides, the trapping process of oxide border traps is found to be caused by thermal activation. At last, for AlGaN/GaN hetero-interfaces, it is confirmed that there are no distributed bulk traps in the near interfacial region of the hetero-interface. Besides, the different properties of deep trap levels and shallow trap levels at the hetero-interface are also presented. iii Table of Contents Acknowledgements ............................................................................................................................... i Abstract .............................................................................................................................................. iii Table of Contents ............................................................................................................................... iv Symbols and Abbreviation ................................................................................................................. vii List of figures ..................................................................................................................................... xii List of Tables ................................................................................................................................... xxii Chapter 1: Introduction ...................................................................................................................... 1 1.1 Moore’s law and Dennard Scaling ............................................................................................ 2 1.1.1 Moore’s law – history and current status ........................................................................... 2 1.1.2 Dennard scaling law and its challenges .............................................................................. 3 1.2 Overcoming the challenges faced by CMOS scaling .............................................................. 13 1.2.1 “More Moore” and “More than Moore” ........................................................................... 13 1.2.2 Multi-gate FETs for gate-to-channel electrostatic control ............................................... 15 1.2.3 High-k/Metal gate for EOT scaling .................................................................................. 18 1.2.4 III-V/Ge based FETs for mobility boosting ..................................................................... 19 1.2.5 AlGaN/GaN based HEMT for high-frequency, high-power application ......................... 22 1.3 Interface traps and near interfacial bulk traps: origin, properties and influences. ................... 26 1.3.1 Interface traps at dielectric/semiconductor interface ........................................................ 27 1.3.2 Near interfacial oxide traps: emerging issues in MOS device with high mobility substrate ................................................................................................................................................... 32 1.3.3 Interface and near interface traps in semiconductor hetero-junction ............................... 35 1.4 Purpose and Organization of this study ................................................................................... 37 References ..................................................................................................................................... 41 Chapter 2: Review of the techniques for characterizing interface and near interface traps .............. 47 2.1 Admittance analysis for interfacial traps chracterization ........................................................ 48 2.1.1 Low-frequency
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