A Compute Unified System Architecture for Graphics Clusters Incorporating Data-Locality
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Parallel Rendering on Hybrid Multi-GPU Clusters
Eurographics Symposium on Parallel Graphics and Visualization (2012) H. Childs and T. Kuhlen (Editors) Parallel Rendering on Hybrid Multi-GPU Clusters S. Eilemann†1, A. Bilgili1, M. Abdellah1, J. Hernando2, M. Makhinya3, R. Pajarola3, F. Schürmann1 1Blue Brain Project, EPFL; 2CeSViMa, UPM; 3Visualization and MultiMedia Lab, University of Zürich Abstract Achieving efficient scalable parallel rendering for interactive visualization applications on medium-sized graphics clusters remains a challenging problem. Framerates of up to 60hz require a carefully designed and fine-tuned parallel rendering implementation that fits all required operations into the 16ms time budget available for each rendered frame. Furthermore, modern commodity hardware embraces more and more a NUMA architecture, where multiple processor sockets each have their locally attached memory and where auxiliary devices such as GPUs and network interfaces are directly attached to one of the processors. Such so called fat NUMA processing and graphics nodes are increasingly used to build cost-effective hybrid shared/distributed memory visualization clusters. In this paper we present a thorough analysis of the asynchronous parallelization of the rendering stages and we derive and implement important optimizations to achieve highly interactive framerates on such hybrid multi-GPU clusters. We use both a benchmark program and a real-world scientific application used to visualize, navigate and interact with simulations of cortical neuron circuit models. Categories and Subject Descriptors (according to ACM CCS): I.3.2 [Computer Graphics]: Graphics Systems— Distributed Graphics; I.3.m [Computer Graphics]: Miscellaneous—Parallel Rendering 1. Introduction Hybrid GPU clusters are often build from so called fat render nodes using a NUMA architecture with multiple The decomposition of parallel rendering systems across mul- CPUs and GPUs per machine. -
Contention-Free Periodic Message Scheduler Medium Access Control in Wireless Sensor / Actuator Networks
Contention-Free Periodic Message Scheduler Medium Access Control in Wireless Sensor / Actuator Networks Thomas W. Carley Moussa A. Ba Rajeev Barua David B. Stewart ECE Department Embedded Research ECE Department Embedded Research University of Maryland Solutions University of Maryland Solutions [email protected] mba@embedded- [email protected] dstewart@embedded- zone.com zone.com Abstract actuator network applications have timeliness constrains, both on activities on individual nodes, and across multiple This paper presents a time division multiple access nodes. This results in timeliness constraints on both tasks medium access control protocol for wireless sensor / running on nodes and messages exchanged by nodes. actuator networks implemented with a contention-free Medium access control (MAC) is one of the most message scheduler. A message scheduler is used to important, and most studied, protocol layers in wireless determine which message has access to the medium at sensor / actuator networks. Wireless sensor / actuator any time. A set of messages is contention-free if only one networks are often characterized by extreme constraints message is ready at a time. Otherwise, some other on size, cost, power, and timeliness. This imposes criterion such as priority must be used to resolve constraints on every aspect of the design of these contention. In this case the message scheduler at each networks, especially the protocol stack. Wireless node in the network must schedule all messages in order networks are inherently broadcast media; all nodes in the to resolve contention. If the schedule is contention-free network share one common communication medium. however, then each node only schedules the messages that Therefore, a method for resolving contention when interest it. -
Parallel Texture-Based Vector Field Visualization on Curved Surfaces Using GPU Cluster Computers
Eurographics Symposium on Parallel Graphics and Visualization (2006) Alan Heirich, Bruno Raffin, and Luis Paulo dos Santos (Editors) Parallel Texture-Based Vector Field Visualization on Curved Surfaces Using GPU Cluster Computers S. Bachthaler1, M. Strengert1, D. Weiskopf2, and T. Ertl1 1Institute of Visualization and Interactive Systems, University of Stuttgart, Germany 2School of Computing Science, Simon Fraser University, Canada Abstract We adopt a technique for texture-based visualization of flow fields on curved surfaces for parallel computation on a GPU cluster. The underlying LIC method relies on image-space calculations and allows the user to visualize a full 3D vector field on arbitrary and changing hypersurfaces. By using parallelization, both the visualization speed and the maximum data set size are scaled with the number of cluster nodes. A sort-first strategy with image-space decomposition is employed to distribute the workload for the LIC computation, while a sort-last approach with an object-space partitioning of the vector field is used to increase the total amount of available GPU memory. We specifically address issues for parallel GPU-based vector field visualization, such as reduced locality of memory accesses caused by particle tracing, dynamic load balancing for changing camera parameters, and the combination of image-space and object-space decomposition in a hybrid approach. Performance measurements document the behavior of our implementation on a GPU cluster with AMD Opteron CPUs, NVIDIA GeForce 6800 Ultra GPUs, and Infiniband network connection. Categories and Subject Descriptors (according to ACM CCS): I.3.3 [Computer Graphics]: Viewing algorithms I.3.3 [Three-Dimensional Graphics and Realism]: Color, shading, shadowing, and texture 1. -
Evolution of the Graphical Processing Unit
University of Nevada Reno Evolution of the Graphical Processing Unit A professional paper submitted in partial fulfillment of the requirements for the degree of Master of Science with a major in Computer Science by Thomas Scott Crow Dr. Frederick C. Harris, Jr., Advisor December 2004 Dedication To my wife Windee, thank you for all of your patience, intelligence and love. i Acknowledgements I would like to thank my advisor Dr. Harris for his patience and the help he has provided me. The field of Computer Science needs more individuals like Dr. Harris. I would like to thank Dr. Mensing for unknowingly giving me an excellent model of what a Man can be and for his confidence in my work. I am very grateful to Dr. Egbert and Dr. Mensing for agreeing to be committee members and for their valuable time. Thank you jeffs. ii Abstract In this paper we discuss some major contributions to the field of computer graphics that have led to the implementation of the modern graphical processing unit. We also compare the performance of matrix‐matrix multiplication on the GPU to the same computation on the CPU. Although the CPU performs better in this comparison, modern GPUs have a lot of potential since their rate of growth far exceeds that of the CPU. The history of the rate of growth of the GPU shows that the transistor count doubles every 6 months where that of the CPU is only every 18 months. There is currently much research going on regarding general purpose computing on GPUs and although there has been moderate success, there are several issues that keep the commodity GPU from expanding out from pure graphics computing with limited cache bandwidth being one. -
Open Dissertation Draft Revised Final.Pdf
The Pennsylvania State University The Graduate School ICT AND STEM EDUCATION AT THE COLONIAL BORDER: A POSTCOLONIAL COMPUTING PERSPECTIVE OF INDIGENOUS CULTURAL INTEGRATION INTO ICT AND STEM OUTREACH IN BRITISH COLUMBIA A Dissertation in Information Sciences and Technology by Richard Canevez © 2020 Richard Canevez Submitted in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy December 2020 ii The dissertation of Richard Canevez was reviewed and approved by the following: Carleen Maitland Associate Professor of Information Sciences and Technology Dissertation Advisor Chair of Committee Daniel Susser Assistant Professor of Information Sciences and Technology and Philosophy Lynette (Kvasny) Yarger Associate Professor of Information Sciences and Technology Craig Campbell Assistant Teaching Professor of Education (Lifelong Learning and Adult Education) Mary Beth Rosson Professor of Information Sciences and Technology Director of Graduate Programs iii ABSTRACT Information and communication technologies (ICTs) have achieved a global reach, particularly in social groups within the ‘Global North,’ such as those within the province of British Columbia (BC), Canada. It has produced the need for a computing workforce, and increasingly, diversity is becoming an integral aspect of that workforce. Today, educational outreach programs with ICT components that are extending education to Indigenous communities in BC are charting a new direction in crossing the cultural barrier in education by tailoring their curricula to distinct Indigenous cultures, commonly within broader science, technology, engineering, and mathematics (STEM) initiatives. These efforts require examination, as they integrate Indigenous cultural material and guidance into what has been a largely Euro-Western-centric domain of education. Postcolonial computing theory provides a lens through which this integration can be investigated, connecting technological development and education disciplines within the parallel goals of cross-cultural, cross-colonial humanitarian development. -
Slate XNS TSN Network Scheduler with Browser-Based Topology Modeling
Slate XNS TSN Network Scheduler with Browser-based Topology Modeling Key Benefits Intuitive graphical topology modeling Incremental scheduling of new components and data streams Open, standard configuration for any TSN device One-click scheduling for complex networks Optimized bandwidth use for non-scheduled traffic Slate XNS is a browser-based, user-friendly software that makes it easy to model topologies, create schedules and deploy configurations for TSN networks. Offline network configuration is made possible by the intuitive GUI which provides a topology view or table-based editor for managing components and data streams. Schedules are calculated with just one click via TTTech’s built-in scheduling engine, and network components are configured using open, standard YANG models. Topology Modeling Network Scheduler Graphical One-Click Scheduling The graphical view is ideal for modeling small and TTTech’s high performance scheduling engine is medium sized network topologies. New components built-in to the Slate XNS software. After building the can be added by dragging and dropping into the topology and defining the data streams, the schedule topology. Data streams can also be represented as can be created with just one click. Schedules can logical connections between components. even be updated incrementally when new components or data streams are added. Table-Based Slate XNS schedules IEEE 802.1Qbv and 802.1Qbu The table editor is designed for modeling large traffic as well as supporting cut-through data network topologies and mass editing. Components, streams. Scheduling can be adjusted to optimize data streams and other parameters can be inputted bandwidth for non-scheduled traffic. -
Hybrid Event-Time-Triggered Networked Control Systems: Scheduling-Event
Information Sciences 305 (2015) 269–284 Contents lists available at ScienceDirect Information Sciences journal homepage: www.elsevier.com/locate/ins Hybrid event-time-triggered networked control systems: Scheduling-event-control co-design ⇑ Shixi Wen a, Ge Guo a, , Wing Shing Wong b a School of Information Science and Technology, Dalian Maritime University, Dalian 116026, China b Department of Information Engineering, The Chinese University of Hong Kong, Hong Kong, China article info abstract Article history: This paper is concerned with the simultaneous stabilization of a collection of plants Received 19 August 2014 remotely controlled via a wireless network. The so-called most regular binary sequences Received in revised form 21 December 2014 (MRBSs) are used to allocate the limited network channels. To further reduce unnecessary Accepted 27 January 2015 transmissions, an event-triggered transmitter is introduced at each plant. Under the hybrid Available online 7 February 2015 event-time-triggered transmission strategy, a sufficient stability condition is derived for each plant. Then, a unified co-design framework is presented with which the scheduling Keywords: functions (i.e., the MRBSs), the event-triggering condition and the controller gains can be Networked control systems determined simultaneously. The main results are established using piecewise Lyapunov Capacity limitation Event-triggered transmission functional method and average dwell time technique. The effectiveness of the co-design Protocol sequence method is demonstrated by a numerical example. Scheduling-event-control co-design Ó 2015 Elsevier Inc. All rights reserved. 1. Introduction In wireless networked systems (such as wireless sensor networks) consisting of a large number of nodes, network capa- city limitation is often a serious issue. -
Literature Review and Implementation Overview: High Performance
LITERATURE REVIEW AND IMPLEMENTATION OVERVIEW: HIGH PERFORMANCE COMPUTING WITH GRAPHICS PROCESSING UNITS FOR CLASSROOM AND RESEARCH USE APREPRINT Nathan George Department of Data Sciences Regis University Denver, CO 80221 [email protected] May 18, 2020 ABSTRACT In this report, I discuss the history and current state of GPU HPC systems. Although high-power GPUs have only existed a short time, they have found rapid adoption in deep learning applications. I also discuss an implementation of a commodity-hardware NVIDIA GPU HPC cluster for deep learning research and academic teaching use. Keywords GPU · Neural Networks · Deep Learning · HPC 1 Introduction, Background, and GPU HPC History High performance computing (HPC) is typically characterized by large amounts of memory and processing power. HPC, sometimes also called supercomputing, has been around since the 1960s with the introduction of the CDC STAR-100, and continues to push the limits of computing power and capabilities for large-scale problems [1, 2]. However, use of graphics processing unit (GPU) in HPC supercomputers has only started in the mid to late 2000s [3, 4]. Although graphics processing chips have been around since the 1970s, GPUs were not widely used for computations until the 2000s. During the early 2000s, GPU clusters began to appear for HPC applications. Most of these clusters were designed to run large calculations requiring vast computing power, and many clusters are still designed for that purpose [5]. GPUs have been increasingly used for computations due to their commodification, following Moore’s Law (demonstrated arXiv:2005.07598v1 [cs.DC] 13 May 2020 in Figure 1), and usage in specific applications like neural networks. -
Graphpulse: an Event-Driven Hardware Accelerator for Asynchronous Graph Processing
2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) GraphPulse: An Event-Driven Hardware Accelerator for Asynchronous Graph Processing Shafiur Rahman Nael Abu-Ghazaleh Rajiv Gupta Computer Science and Engineering Computer Science and Engineering Computer Science and Engineering University of California, Riverside University of California, Riverside University of California, Riverside Riverside, USA Riverside, USA Riverside, USA [email protected] [email protected] [email protected] Abstract—Graph processing workloads are memory intensive GraphLab [31], GraphX [16], PowerGraph [17], Galois [37], with irregular access patterns and large memory footprint result- Giraph [4], GraphChi [28], and Ligra [49]. ing in low data locality. Their popular software implementations Large scale graph processing introduces a number of chal- typically employ either Push or Pull style propagation of changes through the graph over multiple iterations that follow the Bulk lenges that limit performance on traditional computing systems. Synchronous Model. The performance of these algorithms on First, memory-intensive processing stresses the memory system. traditional computing systems is limited by random reads/writes Not only is the frequency of memory operations relative of vertex values, synchronization overheads, and additional over- to compute operations high, the memory footprints of the heads for tracking active sets of vertices or edges across iterations. graph computations are large. Standard techniques in modern In this paper, we present GraphPulse, a hardware framework for asynchronous graph processing with event-driven schedul- processors for tolerating high memory latency, such as caching ing that overcomes the performance limitations of software and prefetching, have limited impact because irregular graph frameworks. Event-driven computation model enables a parallel computations lack data locality. -
GPU Accelerated Approach to Numerical Linear Algebra and Matrix Analysis with CFD Applications
University of Central Florida STARS HIM 1990-2015 2014 GPU Accelerated Approach to Numerical Linear Algebra and Matrix Analysis with CFD Applications Adam Phillips University of Central Florida Part of the Mathematics Commons Find similar works at: https://stars.library.ucf.edu/honorstheses1990-2015 University of Central Florida Libraries http://library.ucf.edu This Open Access is brought to you for free and open access by STARS. It has been accepted for inclusion in HIM 1990-2015 by an authorized administrator of STARS. For more information, please contact [email protected]. Recommended Citation Phillips, Adam, "GPU Accelerated Approach to Numerical Linear Algebra and Matrix Analysis with CFD Applications" (2014). HIM 1990-2015. 1613. https://stars.library.ucf.edu/honorstheses1990-2015/1613 GPU ACCELERATED APPROACH TO NUMERICAL LINEAR ALGEBRA AND MATRIX ANALYSIS WITH CFD APPLICATIONS by ADAM D. PHILLIPS A thesis submitted in partial fulfilment of the requirements for the Honors in the Major Program in Mathematics in the College of Sciences and in The Burnett Honors College at the University of Central Florida Orlando, Florida Spring Term 2014 Thesis Chair: Dr. Bhimsen Shivamoggi c 2014 Adam D. Phillips All Rights Reserved ii ABSTRACT A GPU accelerated approach to numerical linear algebra and matrix analysis with CFD applica- tions is presented. The works objectives are to (1) develop stable and efficient algorithms utilizing multiple NVIDIA GPUs with CUDA to accelerate common matrix computations, (2) optimize these algorithms through CPU/GPU memory allocation, GPU kernel development, CPU/GPU communication, data transfer and bandwidth control to (3) develop parallel CFD applications for Navier Stokes and Lattice Boltzmann analysis methods. -
Introduction to Gpus for HPC
CSC 391/691: GPU Programming Fall 2011 Introduction to GPUs for HPC Copyright © 2011 Samuel S. Cho High Performance Computing • Speed: Many problems that are interesting to scientists and engineers would take a long time to execute on a PC or laptop: months, years, “never”. • Size: Many problems that are interesting to scientists and engineers can’t fit on a PC or laptop with a few GB of RAM or a few 100s of GB of disk space. • Supercomputers or clusters of computers can make these problems practically numerically solvable. Scientific and Engineering Problems • Simulations of physical phenomena such as: • Weather forecasting • Earthquake forecasting • Galaxy formation • Oil reservoir management • Molecular dynamics • Data Mining: Finding needles of critical information in a haystack of data such as: • Bioinformatics • Signal processing • Detecting storms that might turn into hurricanes • Visualization: turning a vast sea of data into pictures that scientists can understand. • At its most basic level, all of these problems involve many, many floating point operations. Hardware Accelerators • In HPC, an accelerator is hardware component whose role is to speed up some aspect of the computing workload. • In the olden days (1980s), Not an accelerator* supercomputers sometimes had array processors, which did vector operations on arrays • PCs sometimes had floating point accelerators: little chips that did the floating point calculations in hardware rather than software. Not an accelerator* *Okay, I lied. To Accelerate Or Not To Accelerate • Pro: • They make your code run faster. • Cons: • They’re expensive. • They’re hard to program. • Your code may not be cross-platform. Why GPU for HPC? • Graphics Processing Units (GPUs) were originally designed to accelerate graphics tasks like image rendering. -
RCD: Rapid Close to Deadline Scheduling for Datacenter Networks
RCD: Rapid Close to Deadline Scheduling for Datacenter Networks Mohammad Noormohammadpour1, Cauligi S. Raghavendra1, Sriram Rao2, Asad M. Madni3 1Ming Hsieh Department of Electrical Engineering, University of Southern California 2Cloud and Information Services Lab, Microsoft 3Department of Electrical Engineering, University of California, Los Angeles Abstract—Datacenter-based Cloud Computing services provide platform runs on multiple datacenters located in different a flexible, scalable and yet economical infrastructure to host continents. online services such as multimedia streaming, email and bulk Many applications require traffic exchange between data- storage. Many such services perform geo-replication to provide necessary quality of service and reliability to users resulting centers to synchronize data, access backup copies or perform in frequent large inter-datacenter transfers. In order to meet geo-replication; examples of which include content delivery tenant service level agreements (SLAs), these transfers have to networks (CDNs), cloud storage and search and indexing be completed prior to a deadline. In addition, WAN resources services. Most of these transfers have to be completed prior are quite scarce and costly, meaning they should be fully utilized. to a deadline which is usually within the range of an hour to Several recently proposed schemes, such as B4 [1], TEMPUS [2], and SWAN [3] have focused on improving the utilization of inter- a couple of days and can also be as large as petabytes [2]. datacenter transfers through centralized scheduling, however, In addition, links that connect these datacenters are expensive they fail to provide a mechanism to guarantee that admitted to build and maintain. As a result, for any algorithm used to requests meet their deadlines.