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1 1 1 1 11X1 1 US005740098A United States Patent [191 [11] Patent Number: 5,740,098 Adams et al. [45] Date of Patent: Apr. 14, 1998 [54] USING ONE NIEMORY TO SUPPLY 5,258,986 11/1993 Zerbe . .. 371/212 ADDRESSES TO AN ASSOCIATED MEMORY 5,311,520 5/1994 Raghavach?? 371/21-6 DURING TESTING 5,329,471 7/1994 Swoboda et a1. 364/578 5,377,148 12/1994 Rajsuman .... .. 365/201 Inventors: RobertJohl} Connor’ Dean Adams, BPl'l-ingtom Essex James Junction; J- Primary Examiner—A. MaguireZarabian .................................. .. Covmo; Roy Ch?ds Flaker, both of Attorney, Agent, or Firm—Calfee. Halter & Griswold LLP Essex Junction; Garrett Stephen Koch, Cambridge; Alan Lee Roberts. Jericho; [57] ABSTRACT ggs?f 2033;112:215 211mg; gimme’ Jr" An associated memory structure having a plurality of memo ’ ' ries amenable for testing and a method of testing the - : - - bin memories is provided. First and second memories are [73] As Slgne? [£22322]? 2111;215:5132‘; es formed, wherein data in the ?rst memory provides a basis for ' ’ ' ' at least a portion of the input to the second memory during I functional operation of two memories. Preferably, an output [21] App 1' No" 671’279 latch for receiving the output test data from the ?rst memory [22] Filed: Jun. 27, 1996 is provided. Means are provided for loading the ?rst memory with data which is utilized as a basis for providing at least Related US, Application Data a portion of the input to the second memory. An access path from the output port of the ?rst memory to the input port of [62] Division of Ser. No. 398,465, Mar. 3, 1995, Pat. No. the second memory allows use of the data in the ?rst 5,563,333‘ memory to generate at least a portion of the input to the [51] Int. GL6 _____ " Gllc 15/00 second memory. The ?rst memory is ?rst tested indepen [52] U S C1 3654} 365/201 dently of the second memory. Thereafter, the ?rst memory is [58] FIeI'd I201 49’ 189 O5 loaded with preconditioned data that is used as a basis for l 0 ea """"""" 02 3,;1/2’1 1 inputs to the second memory during testing of the second ' ’ ' ’ ' memory. The second memory is then tested by generating ~ inputs to the ?rst memory during testing of the second [56] References Clted memory. Thus, outputs of the ?rst memory constitute at least U.S. PATENT DOCUMENTS a portion of test data inputted to the second memory. Alatch 5 099 481 311992 Miner 371/22 1 is provided to capture the output of the test data from the 5Z1071501 4/1992 Zon'an .......... .. 371/213 Second memory 5,138,619 8/1992 Fasang et a1. .. 371/211 5,224,101 6/1993 Popyack, Jr. ......................... .. 371/211 5 Claims, 7 Drawing Sheets COMPARE / 40° AUDRESS g f [05 > 420 g Q l/] m / 301] 2211 1 1111111 . - - - 111111”?4O 320~+11111 - - . lune-340 eseszmg egg... 9,‘ % w'\\‘~ co (-3 co 1; ,7; > 350 200 j 3 L100 2 HO l/ r120 1J 1 1 1 1 1 1 1 . 11x1 1 f1 / 510 US. Patent Apr. 14, 1998 Sheet 1 0f 7 5,740,098 ilJlfl\ 2l:\\ 2|/r\ 8I\\ 8528 Ni):\a E5388572£5582825;, 52:33w2238m$5.5m2:38Q55.60_2:38o2:33 2l:r\ 58882888858882888858882888858882 2: > 588cc2880085888288coco-8oc262808255825023: 50885@680885880862688500258500826608852W; _88585888858882888858882888858; 68288 58882888858882888858882888858882I)_ “2UG 3: E; .oI US. Patent Apr. 14, 1998 Sheet 2 of 7 5,740,098 DATA AND 4 REAO/HRITE / 2 CONTROL SELECT A I l l ‘ I /48 CD CAM ' FUNCTIONAL PATH “4, 0w — 24 HUX' 28] SELECT B \_ 26 37 TEST “0 PATH ——> f44 46-\ BISTIN Mux LATCH CAM E \ COMPRESSION LATCH 32 K30 34 35 J LRl 5h 1, _ DCO LR2—P DATA COMPRESSION ( PR I OR ART 1 8 CD CAM ‘ f48 ‘ ' ‘ VA-P DCD "J 1°’ 16) R"PI A /IIAHA “ _ 4s LATCH ! . 37 CONTROL \LATCH T CAM '\ COMPRESSION “— LR‘ DCU F 3 LR2——-> DATA _ COMPRESSION US. Patent Apr. 14, 1998 Sheet 3 0f 7 5,740,098 omm ROW ADDRESS US. Patent Apr. 14, 1998 Sheet 4 of 7 5,740,098 FIG. 5' ‘ US. Patent Apr. 14, 1998 Sheet 6 0f 7 EEF.5iiiiall}..iiiiaiiilimmib?bw....................... : 670C 7006 / US. Patent Apr. 14, 1998 Sheet 7 0f 7 5,740,098 ‘920 (925 ll-lnll-l-lll-l-l-nlll-ll-Il 7 2 0 C 900 J 720d ......................................1. F1088 5,740,098 1 2 USING ONE MEMORY TO SUPPLY detected by this type of testing since each memory is tested ADDRESSES TO AN ASSOCIATED MEMORY separately and independently from data generated from the DURING TESTING BIST machine which does not use one memory to supply data to another memory, i.e., with the signal timings and This is a divisional of application Ser. No. 08/398,465, along the path which the data ?ows during functional ?led on Mar. 3, 1995 US Pat. No 5,563,833. operation. While the problem of testing associated memory is extant in BIST tests, it also exists in other types of tests RELATED APPLICATION of memories, e. g., signals from oif-chip testers applied to U.S. patent application Ser. No. 08/398,468, ?led Mar. 3, test memory circuits and other dependent circuits. 10 1995, entitled “BIST Tester for Multiple Memories”(Atty. SUMMARY OF THE INVENTION Docket No. BU9-94-146). According to the present invention, an associated memory FIELD OF THE INVENTION structure comprised of a plurality of memories amenable for This invention relates generally to testing of memory testing and a method of testing the memories is provided First and second memories are formed (on a semiconductor devices, and in one aspect to a built-in self-test for VLSI circuits which are contained on semiconductor chips. In a substrate in the preferred embodiment) wherein the data in the ?rst memory provides a basis for at least a portion of the more particular aspect, this invention relates to a built-in test input to the second memory during functional operation of for memories on semiconductor chips wherein there are a the two memories. Means for inputting test signals into the plurality of memories on the chip and wherein one memory ?rst memory is provided, and preferably an output latch for is associated with another; i.e., one memory provides at least receiving the output test data from the ?rst memory is part of the information required by one or more additional provided. Means are provided for loading the ?rst memory memories known as associated memories during conven tional operation. Such a memory relationship can be, for with data which is utilized as a basis for providing at least a portion of the input to the second memory. An access path example. on microprocessors wherein there are conventional 25 from the output port of the ?rst memory to the input port of memories which store data such as data cache unit (DCU) the second memory is provided to thereby allow use of the memories and which have associated therewith CAM memories. i.e., content addressable memories, which supply data in the ?rst memory to generate at least a portion of the input of the second memory. The ?rst memory is ?rst tested part of the address to the DCU memories during conven» tional operation. although other types of associated memo~ independently of the second memory. Thereafter, the ?rst ries can be tested according to this invention. memory is loaded with preconditioned algorithmic data that is used as a basis for inputs to the second memory during BACKGROUND ART testing of the second memory. The second memory is then tested by generating inputs to the ?rst memory during the Testing of associated memories of the type described test of the second memory, which will cause outputs of the above, formed on semiconductor substrates. has often been 35 ?rst memory to be supplied to the second memory which done by the provision of a built-in self-test (BIST). BISTs constitutes at least a portion of test data inputted to the include a state machine formed on the silicon substrate second memory. A latch is provided to capture the output of which contains the associative memories and the other VLSI the test data from the second memory. circuit components such as the logic components of a microprocessor chip. Such a BIST is shown in copending 40 BRIEF DESCRIPTION OF THE DRAWINGS application Ser. No. 08/398,468. ?led Mar. 3, 1995 and FIG. 1 is a diagrammatic View of the functioning of a entitled “BIST Tester for Multiple Memories” (Atty. Docket content addressable memory (CAM) and its function to No. BU9-94-146); and a state machine for testing a DCU provide input to a data cache unit (DCU) memory in one type memory is shown in U.S. Pat. No. 5,173,906. ' embodiment of this invention; In testing multiple memories, conventional prior art prac 45 FIG. 2 is a block diagram showing a typical prior art tice has been to surround each of the memories with latches construction of a typical con?guration for testing the func and multiplexors and to test each memory independently, tioning of a CAM memory associated with a DCU memory; from data supplied by the state machine of the BIST or FIG. 3 is a block diagram showing the construction through a scan-chain from an oif-chip tester. Also, conven according to this invention of the interconnection for testing tional prior art has employed a separate BIST for each the functioning of a CAM memory and a DCU memory memory.
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