Platform Independent Real-Time X3D Shaders and Their Applications in Bioinformatics Visualization
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Release Notes for X11R6.8.2 the X.Orgfoundation the Xfree86 Project, Inc
Release Notes for X11R6.8.2 The X.OrgFoundation The XFree86 Project, Inc. 9February 2005 Abstract These release notes contains information about features and their status in the X.Org Foundation X11R6.8.2 release. It is based on the XFree86 4.4RC2 RELNOTES docu- ment published by The XFree86™ Project, Inc. Thereare significant updates and dif- ferences in the X.Orgrelease as noted below. 1. Introduction to the X11R6.8.2 Release The release numbering is based on the original MIT X numbering system. X11refers to the ver- sion of the network protocol that the X Window system is based on: Version 11was first released in 1988 and has been stable for 15 years, with only upwardcompatible additions to the coreX protocol, a recordofstability envied in computing. Formal releases of X started with X version 9 from MIT;the first commercial X products werebased on X version 10. The MIT X Consortium and its successors, the X Consortium, the Open Group X Project Team, and the X.OrgGroup released versions X11R3 through X11R6.6, beforethe founding of the X.OrgFoundation. Therewill be futuremaintenance releases in the X11R6.8.x series. However,efforts arewell underway to split the X distribution into its modular components to allow for easier maintenance and independent updates. We expect a transitional period while both X11R6.8 releases arebeing fielded and the modular release completed and deployed while both will be available as different consumers of X technology have different constraints on deployment. Wehave not yet decided how the modular X releases will be numbered. We encourage you to submit bug fixes and enhancements to bugzilla.freedesktop.orgusing the xorgproduct, and discussions on this server take place on <[email protected]>. -
Stephen Clarke-Willson
Contact Stephen Clarke-Willson www.linkedin.com/in/drstephencw Programmer, Producer, Executive (LinkedIn) Sammamish www.arena.net (Company) www.above-the-garage.com (Personal) Summary above-the-garage.com/blog (Blog) Software technology development leadership and management. Top Skills Specialties: Technical / Product team building and management; Systems Programming System Architecture experience as first, second and third level manager in fast growing Game Development companies; systems programming, systems architecture, technology development. Publications Guild Wars Microservices and 24/7 Uptime Guild Wars 2 - Scaling from one to Experience millions Applying Game Design To Virtual NCSOFT Environments VP of Technology Nano-Plasm March 2019 - Present (1 year 7 months) Bellevue, WA ArenaNet LLC 13 years 6 months Programmer in the role of Studio Technical Director May 2013 - March 2019 (5 years 11 months) Bellevue, WA Lead engineering staff (about 100 members) for "gaming as a service" with continuous high volume content creation and delivery at MMO scale. Translate business objectives into innovative yet achievable technical challenges. Created technical unit with flat reporting structure and peer input reviews. Programmer in the roles of Server Programmer / Server Team Lead October 2005 - April 2013 (7 years 7 months) Developing multi-threaded, restartable, dynamically updatable, high performance, internet-resilient, bug free server code for the MMO Guild Wars (1 and 2). Above the Garage Productions Programmer / Owner Page 1 of 4 May 2004 - October 2005 (1 year 6 months) Game Technology Developer, Above the Garage Productions Developed downloadable music system "DirectSong.com" (from payment system [PayPal] to delivery system to embedded music player using Microsoft WMA technology). -
Reviving the Development of Openchrome
Reviving the Development of OpenChrome Kevin Brace OpenChrome Project Maintainer / Developer XDC2017 September 21st, 2017 Outline ● About Me ● My Personal Story Behind OpenChrome ● Background on VIA Chrome Hardware ● The History of OpenChrome Project ● Past Releases ● Observations about Standby Resume ● Developmental Philosophy ● Developmental Challenges ● Strategies for Further Development ● Future Plans 09/21/2017 XDC2017 2 About Me ● EE (Electrical Engineering) background (B.S.E.E.) who specialized in digital design / computer architecture in college (pretty much the only undergraduate student “still” doing this stuff where I attended college) ● Graduated recently ● First time conference presenter ● Very experienced with Xilinx FPGA (Spartan-II through 7 Series FPGA) ● Fluent in Verilog / VHDL design and verification ● Interest / design experience with external communication interfaces (PCI / PCIe) and external memory interfaces (SDRAM / DDR3 SDRAM) ● Developed a simple DMA engine for PCI I/F validation w/Windows WDM (Windows Driver Model) kernel device driver ● Almost all the knowledge I have is self taught (university engineering classes were not very useful) 09/21/2017 XDC2017 3 Motivations Behind My Work ● General difficulty in obtaining meaningful employment in the digital hardware design field (too many students in the field, difficulty obtaining internship, etc.) ● Collects and repairs abandoned computer hardware (It’s like rescuing puppies!) ● Owns 100+ desktop computers and 20+ laptop computers (mostly abandoned old stuff I -
Programmable Shading in Opengl
Computer Graphics - Programmable Shading in OpenGL - Arsène Pérard-Gayot History • Pre-GPU graphics acceleration – SGI, Evans & Sutherland – Introduced concepts like vertex transformation and texture mapping • First-generation GPUs (-1998) – NVIDIA TNT2, ATI Rage, Voodoo3 – Vertex transformation on CPU, limited set of math operations • Second-generation GPUs (1999-2000) – GeForce 256, GeForce2, Radeon 7500, Savage3D – Transformation & lighting, more configurable, still not programmable • Third-generation GPUs (2001) – GeForce3, GeForce4 Ti, Xbox, Radeon 8500 – Vertex programmability, pixel-level configurability • Fourth-generation GPUs (2002) – GeForce FX series, Radeon 9700 and on – Vertex-level and pixel-level programmability (limited) • Eighth-generation GPUs (2007) – Geometry shaders, feedback, unified shaders, … • Ninth-generation GPUs (2009/10) – OpenCL/DirectCompute, hull & tesselation shaders Graphics Hardware Gener Year Product Process Transistors Antialiasing Polygon ation fill rate rate 1st 1998 RIVA TNT 0.25μ 7 M 50 M 6 M 1st 1999 RIVA TNT2 0.22μ 9 M 75 M 9 M 2nd 1999 GeForce 256 0.22μ 23 M 120 M 15 M 2nd 2000 GeForce2 0.18μ 25 M 200 M 25 M 3rd 2001 GeForce3 0.15μ 57 M 800 M 30 M 3rd 2002 GeForce4 Ti 0.15μ 63 M 1,200 M 60 M 4th 2003 GeForce FX 0.13μ 125 M 2,000 M 200 M 8th 2007 GeForce 8800 0.09μ 681 M 36,800 M 13,800 M (GT100) 8th 2008 GeForce 280 0.065μ 1,400 M 48,200 M ?? (GT200) 9th 2009 GeForce 480 0.04μ 3,000 M 42,000 M ?? (GF100) Shading Languages • Small program fragments (plug-ins) – Compute certain aspects of the -
4010, 237 8514, 226 80486, 280 82786, 227, 280 a AA. See Anti-Aliasing (AA) Abacus, 16 Accelerated Graphics Port (AGP), 219 Acce
Index 4010, 237 AIB. See Add-in board (AIB) 8514, 226 Air traffic control system, 303 80486, 280 Akeley, Kurt, 242 82786, 227, 280 Akkadian, 16 Algebra, 26 Alias Research, 169 Alienware, 186 A Alioscopy, 389 AA. See Anti-aliasing (AA) All-In-One computer, 352 Abacus, 16 All-points addressable (APA), 221 Accelerated Graphics Port (AGP), 219 Alpha channel, 328 AccelGraphics, 166, 273 Alpha Processor, 164 Accel-KKR, 170 ALT-256, 223 ACM. See Association for Computing Altair 680b, 181 Machinery (ACM) Alto, 158 Acorn, 156 AMD, 232, 257, 277, 410, 411 ACRTC. See Advanced CRT Controller AMD 2901 bit-slice, 318 (ACRTC) American national Standards Institute (ANSI), ACS, 158 239 Action Graphics, 164, 273 Anaglyph, 376 Acumos, 253 Anaglyph glasses, 385 A.D., 15 Analog computer, 140 Adage, 315 Anamorphic distortion, 377 Adage AGT-30, 317 Anatomic and Symbolic Mapper Engine Adams Associates, 102 (ASME), 110 Adams, Charles W., 81, 148 Anderson, Bob, 321 Add-in board (AIB), 217, 363 AN/FSQ-7, 302 Additive color, 328 Anisotropic filtering (AF), 65 Adobe, 280 ANSI. See American national Standards Adobe RGB, 328 Institute (ANSI) Advanced CRT Controller (ACRTC), 226 Anti-aliasing (AA), 63 Advanced Remote Display Station (ARDS), ANTIC graphics co-processor, 279 322 Antikythera device, 127 Advanced Visual Systems (AVS), 164 APA. See All-points addressable (APA) AED 512, 333 Apalatequi, 42 AF. See Anisotropic filtering (AF) Aperture grille, 326 AGP. See Accelerated Graphics Port (AGP) API. See Application program interface Ahiska, Yavuz, 260 standard (API) AI. -
Troubleshooting Guide Table of Contents -1- General Information
Troubleshooting Guide This troubleshooting guide will provide you with information about Star Wars®: Episode I Battle for Naboo™. You will find solutions to problems that were encountered while running this program in the Windows 95, 98, 2000 and Millennium Edition (ME) Operating Systems. Table of Contents 1. General Information 2. General Troubleshooting 3. Installation 4. Performance 5. Video Issues 6. Sound Issues 7. CD-ROM Drive Issues 8. Controller Device Issues 9. DirectX Setup 10. How to Contact LucasArts 11. Web Sites -1- General Information DISCLAIMER This troubleshooting guide reflects LucasArts’ best efforts to account for and attempt to solve 6 problems that you may encounter while playing the Battle for Naboo computer video game. LucasArts makes no representation or warranty about the accuracy of the information provided in this troubleshooting guide, what may result or not result from following the suggestions contained in this troubleshooting guide or your success in solving the problems that are causing you to consult this troubleshooting guide. Your decision to follow the suggestions contained in this troubleshooting guide is entirely at your own risk and subject to the specific terms and legal disclaimers stated below and set forth in the Software License and Limited Warranty to which you previously agreed to be bound. This troubleshooting guide also contains reference to third parties and/or third party web sites. The third party web sites are not under the control of LucasArts and LucasArts is not responsible for the contents of any third party web site referenced in this troubleshooting guide or in any other materials provided by LucasArts with the Battle for Naboo computer video game, including without limitation any link contained in a third party web site, or any changes or updates to a third party web site. -
Manycore GPU Architectures and Programming, Part 1
Lecture 19: Manycore GPU Architectures and Programming, Part 1 Concurrent and Mul=core Programming CSE 436/536, [email protected] www.secs.oakland.edu/~yan 1 Topics (Part 2) • Parallel architectures and hardware – Parallel computer architectures – Memory hierarchy and cache coherency • Manycore GPU architectures and programming – GPUs architectures – CUDA programming – Introduc?on to offloading model in OpenMP and OpenACC • Programming on large scale systems (Chapter 6) – MPI (point to point and collec=ves) – Introduc?on to PGAS languages, UPC and Chapel • Parallel algorithms (Chapter 8,9 &10) – Dense matrix, and sorng 2 Manycore GPU Architectures and Programming: Outline • Introduc?on – GPU architectures, GPGPUs, and CUDA • GPU Execuon model • CUDA Programming model • Working with Memory in CUDA – Global memory, shared and constant memory • Streams and concurrency • CUDA instruc?on intrinsic and library • Performance, profiling, debugging, and error handling • Direc?ve-based high-level programming model – OpenACC and OpenMP 3 Computer Graphics GPU: Graphics Processing Unit 4 Graphics Processing Unit (GPU) Image: h[p://www.ntu.edu.sg/home/ehchua/programming/opengl/CG_BasicsTheory.html 5 Graphics Processing Unit (GPU) • Enriching user visual experience • Delivering energy-efficient compung • Unlocking poten?als of complex apps • Enabling Deeper scien?fic discovery 6 What is GPU Today? • It is a processor op?mized for 2D/3D graphics, video, visual compu?ng, and display. • It is highly parallel, highly multhreaded mulprocessor op?mized for visual -
From a Programmable Pipeline to an Efficient Stream Processor
Computation on GPUs: From a Programmable Pipeline to an Efficient Stream Processor João Luiz Dihl Comba 1 Carlos A. Dietrich1 Christian A. Pagot1 Carlos E. Scheidegger1 Resumo: O recente desenvolvimento de hardware gráfico apresenta uma mu- dança na implementação do pipeline gráfico, de um conjunto fixo de funções, para programas especiais desenvolvidos pelo usuário que são executados para cada vértice ou fragmento. Esta programabilidade permite implementações de diversos algoritmos diretamente no hardware gráfico. Neste tutorial serão apresentados as principais técnicas relacionadas a implementação de algoritmos desta forma. Serão usados exemplos baseados em artigos recentemente publicados. Através da revisão e análise da contribuição dos mesmos, iremos explicar as estratégias por trás do desenvolvimento de algoritmos desta forma, formando uma base que permita ao leitor criar seus próprios algoritmos. Palavras-chave: Hardware Gráfico Programável, GPU, Pipeline Gráfico Abstract: The recent development of graphics hardware is presenting a change in the implementation of the graphics pipeline, from a fixed set of functions, to user- developed special programs to be executed on a per-vertex or per-fragment basis. This programmability allows the efficient implementation of different algorithms directly on the graphics hardware. In this tutorial we will present the main techniques that are involved in implementing algorithms in this fashion. We use several test cases based on recently published pa- pers. By reviewing and analyzing their contribution, we explain the reasoning behind the development of the algorithms, establishing a common ground that allow readers to create their own novel algorithms. Keywords: Programmable Graphics Hardware, GPU, Graphics Pipeline 1UFRGS, Instituto de Informática, Caixa Postal 15064, 91501-970 Porto Alegre/RS, Brasil e-mail: {comba, cadietrich, capagot, carlossch}@inf.ufrgs.br Este trabalho foi parcialmente financiado pela CAPES, CNPq e FAPERGS. -
Programming Guide: Revision 1.4 June 14, 1999 Ccopyright 1998 3Dfxo Interactive,N Inc
Voodoo3 High-Performance Graphics Engine for 3D Game Acceleration June 14, 1999 al Voodoo3ti HIGH-PERFORMANCEopy en GdRAPHICS E NGINEC FOR fi ot 3D GAME ACCELERATION on Programming Guide: Revision 1.4 June 14, 1999 CCopyright 1998 3Dfxo Interactive,N Inc. All Rights Reserved D 3Dfx Interactive, Inc. 4435 Fortran Drive San Jose CA 95134 Phone: (408) 935-4400 Fax: (408) 935-4424 Copyright 1998 3Dfx Interactive, Inc. Revision 1.4 Proprietary and Preliminary 1 June 14, 1999 Confidential Voodoo3 High-Performance Graphics Engine for 3D Game Acceleration Notice: 3Dfx Interactive, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. The information is subject to change without notice. No responsibility is assumed by 3Dfx Interactive, Inc. for the use of this information, nor for infringements of patents or the rights of third parties. This document is the property of 3Dfx Interactive, Inc. and implies no license under patents, copyrights, or trade secrets. Trademarks: All trademarks are the property of their respective owners. Copyright Notice: No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photographic, or otherwise, or used as the basis for manufacture or sale of any items without the prior written consent of 3Dfx Interactive, Inc. If this document is downloaded from the 3Dfx Interactive, Inc. world wide web site, the user may view or print it, but may not transmit copies to any other party and may not post it on any other site or location. -
University of Klagenfurt Digital Signal Processor (DSP) MD SARWAR
University of Klagenfurt Digital Signal Processor (DSP) GROUP MEMBERS : MD SARWAR ZAHAN (MATRIX:1461419) BASHIRU OTOKITI (MATRIX:1361474) Topic: “GPU Processing” Proc. IEEE 96(5), 2008 AGENDA Introduction GPU Algorithm About GPU CPU VS GPU Short History Application of GPU GPU Pipeline, Architecture Conclusion WHAT IS GPU ? A graphics processing unit (GPU) is a dedicated processor that performs rapid mathematical calculations for rendering high quality video and images . The Abstract goal of a GPU is to enable a representation of a 3D world as realistically as possible. SHORT HISTORY OF GPU 2010 to 1970s 1980s 1990s 2000 to 2010 present ARCADE SYSTEM BOARDS S3 GRAPHICS NVIDIA & AUDI NEC 7220 NVIDIA 3D GRAPHICS RENDERING PIPELINE Image: 3D GRAPHICS RENDERING PIPELINE Vertex Processing: Process and transform individual vertices. Rasterization: Convert each primitive into a set of fragments. Fragment Processing: Process individual fragments. Output Merging: Combine the fragments of all primitives into color-pixel for the display. GPU ARCHITECTURE Image: NVidia GeForce 6800 Series GPU Board Host (CPU). 6 parallel vertex processors (receive data from the host). Image: NVidia GeForce 6800 GPU Architecture triangle setup stage (takes care of primitive assembly). rasterizer stage which produces the fragments. 16 processors (computes the output colors of each fragment). GPU COMPUTING Parallelism is the future of computing. GPU has moved from a fixed-function into full-fledged parallel programmable processor. GPU follow a single program multiple-data (SPMD) programming model. Image: SPMD Model SPMD Tasks are split up and run simultaneously on multiple processors with different input for faster results. GPU SOFTWARE ENVIRONMENTS Famous languages for GPU programming: NVIDIA’s (CUDA) OpenCL HLSL Cg GPU PERFORMANCE EVALUATION Image: GPU Performance Scan performance on CPU, graphics-based GPU (using OpenGL), and direct-compute GPU (using CUDA). -
Lecture: Manycore GPU Architectures and Programming, Part 1
Lecture: Manycore GPU Architectures and Programming, Part 1 CSCE 569 Parallel Computing Department of Computer Science and Engineering Yonghong Yan [email protected] https://passlab.github.io/CSCE569/ 1 Manycore GPU Architectures and Programming: Outline • Introduction – GPU architectures, GPGPUs, and CUDA • GPU Execution model • CUDA Programming model • Working with Memory in CUDA – Global memory, shared and constant memory • Streams and concurrency • CUDA instruction intrinsic and library • Performance, profiling, debugging, and error handling • Directive-based high-level programming model – OpenACC and OpenMP 2 Computer Graphics GPU: Graphics Processing Unit 3 Graphics Processing Unit (GPU) Image: http://www.ntu.edu.sg/home/ehchua/programming/opengl/CG_BasicsTheory.html 4 Graphics Processing Unit (GPU) • Enriching user visual experience • Delivering energy-efficient computing • Unlocking potentials of complex apps • Enabling Deeper scientific discovery 5 What is GPU Today? • It is a processor optimized for 2D/3D graphics, video, visual computing, and display. • It is highly parallel, highly multithreaded multiprocessor optimized for visual computing. • It provide real-time visual interaction with computed objects via graphics images, and video. • It serves as both a programmable graphics processor and a scalable parallel computing platform. – Heterogeneous systems: combine a GPU with a CPU • It is called as Many-core 6 Graphics Processing Units (GPUs): Brief History GPU Computing General-purpose computing on graphics processing units (GPGPUs) GPUs with programmable shading Nvidia GeForce GE 3 (2001) with programmable shading DirectX graphics API OpenGL graphics API Hardware-accelerated 3D graphics S3 graphics cards- single chip 2D accelerator Atari 8-bit computer IBM PC Professional Playstation text/graphics chip Graphics Controller card 1970 1980 1990 2000 2010 Source of information http://en.wikipedia.org/wiki/Graphics_Processing_Unit 7 NVIDIA Products • NVIDIA Corp. -
Computação Paralela Com Arquitetura De Processamento Gráfico Cuda Aplicada a Um Codificador De Vídeo H.264
CENTRO UNIVERSITÁRIO UNIVATES CENTRO DE CIÊNCIAS EXATAS E TECNOLÓGICAS CURSO DE ENGENHARIA DE CONTROLE E AUTOMAÇÃO AUGUSTO LIMBERGER LENZ COMPUTAÇÃO PARALELA COM ARQUITETURA DE PROCESSAMENTO GRÁFICO CUDA APLICADA A UM CODIFICADOR DE VÍDEO H.264 Lajeado 2012 ) u d b / r b . s e t a v i n u . w w w / / : p PROCESSAMENTO GRÁFICOAPLICADA A CUDA UM t COMPUTAÇÃO DE COMARQUITETURA PARALELA t h ( S E T A CODIFICADOR DEH.264 VÍDEO CODIFICADOR V I N U AUGUSTO LIMBERGERAUGUSTO LENZ a d l a t i g i Lajeado Área de concentração: Computação paralela concentração: Computação de Área e Controle Automação. para a obtenção do título de bacharel em Engenharia de Universitário UNIVATES, como parte dos requisitos Centro de Ciências Exatas e Tecnológicas do TrabalhoCentro de Conclusão de Curso apresentado ao ORIENTADOR: ORIENTADOR: 2012 D a c e t o i l b i Ronaldo Hüsemann B – U D B ) u d b / r b . s e t a v i n u . w w w / / : p PROCESSAMENTO GRÁFICOAPLICADA A CUDA UM t COMPUTAÇÃO DE COMARQUITETURA PARALELA t Banca Examinadora: h ( S Mestre pelo PPGCA/UNISINOS –SãoLeopoldo, Brasil peloMestre PPGCA/UNISINOS Prof. pela–Campinas,Mestre FEEC/UNICAMP Brasil Prof. E T Coordenador docursoEngenhariade de Controle Automação e A Maglan CristianoMaglan Diemer Marcelo Gomensoro de Malheiros CODIFICADOR DEH.264 VÍDEO CODIFICADOR V I N U AUGUSTO LIMBERGERAUGUSTO LENZ _______________________________ a d l Prof. Orientador: ____________________________________ Doutor pelo PPGEE/UFRGS – Porto Alegre, –Porto PPGEE/UFRGS Brasil Doutor pelo Prof. a t i g Ronaldo Hüsemann Ronaldo i Rodrigo Porto Wolff pelo Orientador e pela Examinadora.