2016

A Quarterly Publication of The Microelectronics Packaging & Test Engineering Council Volume 20, Number 4 WINTER

GEL DISPENSE FOR ENCAPSULATION OF MEMS PRESSURE SENSORS Gel Encapsulation Poses Unique Challenges in Packaging page 24

Everything-Proof: The Future+ of Mobile and Wearable Devices page 28

MEPTEC MEMBER COMPANY PROFILE Established in 1997, UTAC’s customers span across all vertical markets including: mobile phone and communication, consumer, computing, automotive, security banking, and security identity, industrial and medical applications. page 12

-Corp. INSIDE THIS ISSUE

The success of Epoxy paste adhe- In an industry that is accus- IC Designers, EDA Fan-Out packaging sives have histori- tomed to many package and IP Vendors, platforms is so cally been the sole options, consolidation could Foundries and undeniable today. epoxy material avail- produce “The Big Five” ad- Assembly Houses able for die attach. vanced packaging platforms. Can Work Together. 11 16 20 SPRING30 2011 MEPTEC Report 3 Wear Sense Move it. it. it.

Innovative IC, System-in-Package, and MEMS packaging portfolio for today’s miniaturization, mobility, and IoT needs.

Wire Flip 2.5D WLP Fanout SiP Bond Chip & 3D

Package it. Visit: aseglobal.com 2016 The MEPTEC Report is a Publication of the Microelectronics Packaging & Test Engineering Council 315 Savannah River Dr., Summerville, SC 29485 Tel: (650) 714-1570 Email: [email protected]

A Quarterly Publication of The Microelectronics Packaging & Test Engineering Council Volume 20, Number 4 WINTER Publisher MEPCOM LLC Editor Bette Cooper Art Director/Designer Gary Brown Sales Manager Gina Edwards 2016 ON THE COVER A Quarterly Publication of The Microelectronics Packaging & Test Engineering Council Volume 20, Number 4 WINTER

GEL DISPENSE FOR ENCAPSULATION As the MEMS-based sensing industry grows, the environmental conditions OF MEMS PRESSURE SENSORS MEPTEC Advisory Board Gel Encapsulation Poses Unique Challenges in Packaging in which these sensors must perform grow with it. Pressure sensing is one page 24 application where particularly harsh environments can be present. Unlike

Board Members Everything-Proof: The Future+ of Mobile and Wearable Devices previous technology, the MEMS-based technology offers the ability to place page 28

Ivor Barber AMD MEPTEC MEMBER COMPANY PROFILE Established in 1997, UTAC’s customers span across the microscopic sense element and wire bond interconnects directly in the all vertical markets including: mobile phone and communication, consumer, computing, automotive, security banking, and security identity, industrial and medical applications. fluid path. It is often necessary to protect the sense element and intercon- Joel Camarda SemiOps page 12 -Corp. INSIDE THIS ISSUE The success of Epoxy paste adhe- In an industry that is accus- IC Designers, EDA nects with products such as encapsulation gels. Fan-Out packaging sives have histori- tomed to many package and IP Vendors, platforms is so cally been the sole options, consolidation could Foundries and undeniable today. epoxy material avail- produce “The Big Five” ad- Assembly Houses Booz Allen Hamilton able for die attach. vanced packaging platforms. Can Work Together. Jeff Demmin 11 16 20 SPRING30 2011 MEPTEC Report 3 Cover Photo Courtesy of SMART Microsystems Ltd. Douglass Dixon Henkel Corporation

Nikhil Kelkar Exar Corporation COLUMN ANALYSIS INDUSTRY Acquirer Acquiree Amount ANALYSIS – 2016 was a turning point for the Fan-Out ON Anadigics $32 M INSIGHTS By Ron Jones Microsemi PMC-Sierra $2,500 M Will Fan-Out Packaging be Sustainable Micron Tech Inotera Memories $3,200 M They’re Still Microchip Tech Atmel $3,600 M Long-Term? Dancing Sony Altair Semiconductor $220 M Jean-Christophe Eloy Cisco Systems Leaba Semiconductor $320 M Yole Développement SMART Microsystems  packaging market since both leaders, Apple and TSMC A YEAR AGO, I WROTE AN ARTICLE Nick Leonardi GigOptics Magnum $54 M titled “Who’s Next on the Dance Floor.” It’s focus was on the rapid rise in the Cypress Broadcom wireless IoT $550 M Fan-Out History: 11 level of M&A activity in the semicon- ductor industry. Cavium QLogic $1,360 M 2016 IS A TURNING POINT FOR THE A Long Development and a Recent Hype For several years, semiconductor Softbank ARM, Inc. $32,000 M Fan-Out packaging market since both M&A had been averaging about $12 bil- leaders, Apple and TSMC changed lion per year. (See Table 1.) Analog Devices Linear Tech Corp (LTC) $14,800 M the game and may create a trend of acceptance of Fan-Out packages. Yole changed the game and may create a trend of acceptance of Renesas Intersil $3,200 M Développement (Yole) is analyzing the Year Semi M&A Beijing Mgmt Analolgix $500 M current market and technologies trends 2010 $ 7.7 B and offers you to discover these results PPM Associates Inphi Clarify $275 M within a new report entitled Fan-Out: Phil Marcoux 2011 $ 17.0 B Technologies & Market Trends 2016. Qualcomm NXP $38,500 M 2012 $ 8.5 B TSMC investment in Fan-Out TOTAL $101,111 M Wafer Level Packaging (FOWLP) and 2013 $ 11.5 B development of its Integrated Fan-Out Table 2. Source: GSA Market Watch and Press Releases (InFO) changed the wafer level packag- Fan-Out packages. Yole is analyzing the current market and 2014 $ 16.9 B ing (WLP) landscape. Following high 2015 (approx.) $120.0 B masks. Many designs continue to go up want to get a piece of the pie. I believe volume adoption of InFO and further in complexity, taking them beyond the the major factor in Qualcomm’s deci- development of embedded Wafer Level Table 1. Source: IC Insights technical reach of smaller fabless compa- sion to acquire NXP is its penetration in Ball grid array (eWLB) technology, a Source: Fan-Out Technologies & Market Trends 2016 report, Yole Développement. nies. the automotive market to bolster Qual- wave of new players and FO WLP tech- I added up the deals in November, The Internet of Things (IoT) and comm’s small presence. nologies may enter the market. TSMC’s Xilinx 2015 and the total was just north of $100 other smart technologies are continuing Having been in the industry for sev- FO WLP solution called InFO will be it is also a major turn: processors sors, memories, etc. This market is Gamal Refai-Ahmed billion. You can’t get an exact count to grow and are becoming a focus for a eral decades and watching the fabless used to package the Apple A10 applica- require thousands of connections more uncertain and will require new technologies trends and offers you to discover these results because not all deal sizes are disclosed lot of companies. To that end, companies model create hundreds and hundreds of tion processor, implemented in the new while the FO market was essentially integration solutions and high perform- and there is a time lapse between when are acquiring other companies that have new companies over the past 25 years, it iPhone 7 series… The success of FO focused on limited IO count applica- ing FO packages but has a very high deals are announced and when they close enabling products, technology or IP to is interesting to watch as consolidation packaging platforms is so undeniable tions so far. potential. . . . or don’t close. It’s a bit like counting position them for a market that is expect- reverses the trend to some degree with today. What will be the status of the a room full of white cats. The general ed to experience rapid growth. It is not a growing number of mega fabless/IDM market tomorrow? What are the next • Eventually, the potential for market Apart from TSMC, STATS ChipPAC consensus is 2015 came in around $120 a matter of whether IoT will happen, but companies. Nothing is forever . . . except steps of the leading FO players? Which spread is very high: the Apple brand is willing to make further investments billion. rather in what myriad configurations it change. ◆ technology will be the winning solu- brings more interest to the FO platform. powered by JCET, ASE extends its I don’t think there was any expecta- will reveal itself and how quickly it will tions? partnership with Deca Technologies tion that deals would stop just because grow over the next several years. According to Yole’s advanced pack- while Amkor, SPIL, and Powertech are RON JONES is CEO of N-Able within a new report. we rolled from 2015 to 2016 . . . and that A new driver this year is the rapid “Production starts in 2016 and rep- aging & semiconductor manufacturing in development phase eyeing future pro- Group International; a semiconduc- was indeed the case. rise in smart, autonomous vehicles of resents a big change in the Fan-Out team, the market will actually be split duction. Samsung is seemingly lagging ASE (US) Inc. tor focused consulting and recruiting Rich Rice It is the end of the year again and the all sizes. Great strides have been made industry for several reasons”, confirms into two types: behind and is considering its options to company. N-Able Group utilizes deep M&A tally is shown in the Table 2. in the last year and lots of companies Jérôme Azémar, Market & Technol- raise competitiveness. At this point in time, it looks like semi supply chain knowledge and a ogy Analyst, Advanced Packaging • The “core” market of FO, including “With such a high potential for the 2016 will be similar to 2015 in number powerful cloud based software appli- & Manufacturing at Yole. And he single die applications such as Base- high-density FO and solid growth of the cation to provide Conflict Mineral of deals in each size category and in total Deal Size 2015 2016 explains: band, Power management, RF trans- core FO, the supply chain is also expect- dollars. I excluded smaller deals that had Compliance support services to com- ceivers, etc. This is the main pool for ed to evolve with a considerable amount no given deal size. (See Table 3. 10 billion plus 4 3 panies throughout the semiconduc- • First of all, in terms of volume, cap- FO WLP solutions and will keep of investment in Fan-Out packaging As last year, the growth to some tor supply chain including fabless, turing the Apple processor market growing. capabilities”, asserts Jérôme Azemar 1 – 10 billion 5 5 degree is driven by trends that have been foundry, OSAT and materials suppli- is a big asset for Fan-Out technology. from Yole. Several players are already going on for years, such as the increas- 0 – 1 billion 4 7 ers. Visit www.n-ablegroup.com or iPhone 7 phones are expected to be • The “high-density” FO market, start- offering FO WLP while many others are ing cost of mask sets. It is not unusual email [email protected] sold in more than 200 million units. ed by Apple application processor developing their competitive Fan-Out (Top 3 accounted for almost 85%) for leading edge designs to run in excess for more information. engine (APE) that will include larger platforms to enter the Fan-Out landscape Altera ◆ Minghao Shen JEAN-CHRISTOPHE ELOY of $100 million, and that is just for the Table 3. Number of Deals by Deal Size • In terms of technology capability, I/O count applications such as proces- and enlarge their portfolio. WINTER 2016 meptec.org meptec.org WINTER 2016 YOLE DÉVELOPPEMENT 10 MEPTEC REPORT MEPTEC REPORT 11 Scott Sikorski STATS ChipPAC

Gartner Jim Walker PROFILE

ASSEMBLY SERVICES PROFILE – UTAC is a leading independent provider of UTAC offers a wide range of semi- conductor assembly services to meet customers’ needs and the increasing mar- CMOS Image Sensor ket demand for next generation devices. UTAC has a diverse capability spanning across ten factories, in six countries in the Asia Pacific region. Their packaging 5-Die Stacked (0.8mm) Smart Card Module Cu Clip QFN capability includes Leadless Packages, Module 2 FET + Clip + Controller Wafer Level Packages, System in Package semiconductor assembly and test services for a broad (SiP), Laminate Packages, Leaded Pack- ages and Security Smart Card Module and 8-Die Stacked (0.9mm) Smart Card Inlay. Special Advisors 12 UTAC - SINGAPORE - TEST CENTER OF EXCELLENCE To complement their packaging solu- fcBGA SiP (Solder) UTAC HOLDINGS LTD AND ITS tions they have state-of-the-art design and • Experienced Team (average years on the job) Final Test, Wafer Probe & Post-Test Processes: GQFN-SiP package characterization capabilities to LGA-SiP (Multichip RF) subsidiaries (UTAC), is a leading inde- • Engineering Managers 15 Years & Test Engineers 10 Years help customers achieve both performance pendent provider of semiconductor • World Class Systems for OEE & Factory Systems with Online & Offline Engineering Analysis assembly and test services for a broad and cost objectives. UTAC engineering • Operations with intrinsic ownership for Quality & Pervasive Continuous Improvement Culture. D2-fcFBGA (Hybrid) range of integrated circuits including teams collaborate closely with customers range of integrated circuits including analog, mixed-signal, logic, • Proven Project Management methodology used for NPI Qualification, Safe Launch, analog, mixed-signal, logic, memory Pre/Mass Production Release to understand the performance require- ments and utilize proprietary calculators and radio frequency. UTAC is the 6th • Driving on-going Innovations, Benchmarking & Value Creations with solide alignment with ATE & largest OSAT in the world and among Systems Solutions Suppliers and design tools to accelerate the pack- full-service assembly and test providers, • Wide range of configurations for Components, Integrated & Complex RF/Mixed Signal testing age design phase. Once the design is UTAC’s test percent of revenue is the solutions approved, UTAC uses a proven project N-Able Group International highest in the industry. • Sophisticated and Competitive Technical Roadmap for higher pin count and higher parallelism management methodology to facilitate the Ron Jones Superior WLCSP engineering experience including BSP, Side-Wall Protection & AVI/EOL new product introduction, taking the prod- The Group offers a full range of • package and test development, engineer- uct through a rigorous phase gate process memory and radio frequency. UTAC is the 6th largest OSAT in ing and manufacturing services and Medical / Automotive / Consumer / Industrial / Mobile Phone / Security to ensure first time qualification. solutions to customers who are primarily integrated device manufacturers (IDMs), TEST SERVICES fabless semiconductor companies, and UTAC is a world leader in integrated wafer foundries. circuits testing with more than 1,600 First established in 1997, the Group’s installed testers and a team of more than customers span across all vertical 300 experienced test engineers. Among markets including: mobile phone and full-service assembly and test providers, communication, consumer, comput- UTAC’s test percent of revenue is the the world and among full-service assembly and test providers, Gary Smith EDA ing, automotive, security banking, and highest in the industry. UTAC has wafer Mary Olsson security identity, industrial and medical sort and final test capability in every fac- UTAC’s Thin QFN .3mm VS. Standard QFN applications. Striving to maintain diver- tory location to provide a full-turnkey sity across end markets not only helps product flow. to provide balance in the ebb & flow of UTAC has extensive experience and product demand, it also positions them KEY FACTS & FIGURES KEY SERVICES capability to test all semiconductor device for growth in the overall industry with • Revenue $878 M (2015) • Assembly Research & Development types in the industry: analog, mixed sig- significant benefits from the proliferation • Established in 1997 • Package Assembly nal, logic, memory, CMOS image sensors, of the Internet of Things (IoT). accelerometer MEMS sensors, radio fre- UTAC’s test percent of revenue is the highest in the industry. • HQ in Singapore • Test Engineering & Development As more devices become connected • Operations in 6 countries, 10 factories • Test Services quency (RF) for radar, near field commu- to the IoT, the need to safeguard infor- • Approximately 12,000 employees • Quality Assurance nications (NFC) and other RFID devices. mation from cyber assaults is driving • Worldwide Sales Team • Reliability & Failure Analysis Their test solutions include wafer probe an increased demand for secure creation • Services: Assembly 65% / Test 35% • End of Line & Drop Ship (ambient, hot and cold), security black and management of devices and data. As box wafer level encryption, final test, O/S a leading supplier of assembly and test test, reliability and failure analysis. With a services, UTAC plays a vital role in their centralized test development engineering customer’s manufacturing flow. Similar team, UTAC provides test development to quality initiatives, security compliance (TD) services to customers worldwide. Honorary Advisors is regulated using industry standards and QFN Single Row Expose Die fcQFN Flip Chip QFN TD engineers work closely with custom- is administered at the UTAC corporate ers to reduce costs and streamline process level. Today, 50% of UTAC’s factories flows by ensuring test programs are opti- UTAC are certified with EAL 6 / ISO standard mized with the most effective test cover- UTAC is a world leader in IC testing with more than 1,600 installed testers and a team of more ISO1540. QFN Dual Row Top Expose Pad QFN age and enable the shortest test times. than 300 experienced test engineers. Photo: UTAC Test Operation in Thailand.

12 MEPTEC REPORT WINTER 2016 meptec.org meptec.org WINTER 2016 MEPTEC REPORT 13 Seth Alavi Sunsil MEMBER COMPANY PROFILE

Gary Catlin APPLICATIONS – Plasma dicing is a chemical-etching APPLICATIONS Rob Cole Die Attach Film Applications Annette Teng Chief Technology Officer Promex Industries Accept (left) process that does not chip or crack the silicon. The Reject (right)

DIE ATTACH FILM (DAF) AND DICING they use a subcontractor who has a well- die attach film (DDAF) have been com- stocked inventory. The cost per wafer of 16 Figure 4. Singulated die on Silver filled Figure 5. Adhesive presence on backside Figure 6. DAF stringer. mercially available since 2000. Epoxy silver filled DAF may be higher, but with DDAF being picked by the Datacon. of die. paste adhesives have historically been the savings in process steps and yield Skip Fehr the sole epoxy material available for die improvement, the cost is very compa- cure. The effect on die tilt and die shift- Figure 5. Poor adhesion may be traced affecting wirebond integrity. Saw dic- attach, an integral part of component rable to paste. ing caused by void formation has been to contaminants such as polydimethylsi- ing parameters must be optimized to gentle dicing process can be controlled to deliver extremely assembly, in particular for wire-bonded Currently both conductive and non- a challenge for paste users, particularly loxane (PDMS)[1] which can be removed eliminate such stringers. Another reject is devices, but not quite applicable for conductive DDAF films are commer- for large dies. The bondlines of stacked by Argon gas plasma cleaning. A pass/ conjoined die found during pick which is flip chip assembly. DAF and DDAF are cially available at various thicknesses. die of various DAF brands after cure are fail criteria set at greater than 95% DAF caused by inadequate adhesive singula- epoxy adhesives which are film based Most suppliers provide 20 to 25µm as a found to be consistently uniform. visible on die backside is acceptable for tion due to improper blade depth or worn instead of paste based and are attached standard thickness option. Lower 10µm High yield can be attained by good good die shear strength. out blades. Lasers can be used for the to the back of the wafer prior to dicing. thickness DAF is available but maybe quality control of DDAF material and Wafers with DAF that are diced with singulation of DAF wafers however, this DAF is sold by the supplier without a a challenge to procure for low volume Figure 1. Photo provided by Lintec. wafer backside cleanliness. Contami- improper dicing parameters may exhibit is only cost effective for high volume support dicing tape, whereas DDAF is users. Electrically and thermally conduc- nants either from mishandled DAF or a adhesive stringers in the saw streets as manufacturing. sold by the supplier on a stretchable sup- tive silver filled films are also available mishandled wafer can result in problems shown Fig 6. This is rejectable as the Die attach films can also be applied Elle Technology smooth sidewalls and has been proven to yield the highest port dicing tape which is partially sawn at 20-25µm thickness and have been with missing adhesive film as shown in stringers may cover bond pad openings to non-die attach processes such as lid Anna Gualtieri and subsequently poked by ejector nee- deployed at Promex for many QFN dles during automated die pick. DDAF device assemblies. QFNs with silver has gained popularity due to the many DDAF have passed JEDEC MSL3 for advantages of film over paste, driven 8x8mm QFN from Promex. However, ADVANTAGE COMPARISON DIE ATTACH FILM DIE ATTACH PASTE especially by the growth of stacked many high-end applications require high- die architecture. Because there is no er thermal conductivity and have resorted Paste Dispense machine set-up Engineering intensive & more None (less set-up dies) re-shaping of adhesive material from a to DAF with diamond fillers instead. Requirement of dies/wafers set-up dies/wafers drop-shape to a thin 2 dimensional layer, Promex has been assembling multi- die strength from all dicing methods. the process window for film is much die stacks with diamond filled DAF suc- Batch oven curing 1hr at 150C-165C Partial cure OK with full cure Must Cure 100% prior to wider than for paste material. Engineer- cessfully. Figure 2 shows a cross-section UPH improvement during wirebond wirebond ing intensive processes to control fillet of a 7-die stack die device using a dia- shape, overflow, under-coverage and mond filled film. The silicon wafers have Die to pad size ratio 1.0 Less than 0.9 ICINTEK Figure 2. 7-die stack with high thermal voiding are eliminated by the use of been thinned to 200µm before laminating Marc Papageorge conductive DAF. films. For very thin dies as well as for onto the diamond filled DAF. The die on Die strength during pick Reinforced by DAF No reinforcement stacked dies, it is imperative to use film. the device wafers with DAF were sin- There are a handful of suppliers of gulated using a dual spindle dicing saw Wafer warpage during handling Reinforced by DAF No reinforcement wafer level DAF. Major suppliers pro- as shown in Figure 3. Saws with single vide the circular DAF sheets in rolls spindle are not recommended as adhe- Bondline Consistent Must monitor for automatic machine lamination such sive stringers and conjoining of die may as shown in Figure 1. DAF can also be result. After singulation, die attach using Con-joined dies Must control during saw None sourced as sheets for non-automated a Datacon 2200 with a heated stage was Die pick Issues Missing adhesive Must control during prep None lamination. DDAF and DAF material performed. Each die is pressed down Stringers Must control during saw None ANNETTE TENG have a shelf life of 6 to 12 months when on a heated substrate at a force recom- stored at 0-10˚C. They can also be stored mended by the supplier which keeps the Die tilt and fillet issues None Must monitor at room temperature, but the expiration die firmly anchored in place. An example date is shortened by about half. Hence, of a wafer with silver epoxy DAF during Pot life before cure Hours/day Minutes<4hrs the material is only made to order and Figure 3. DDAF dicing on dual spindle saw. Datacon pick is shown in Figure 4. All major suppliers impose a minimum order DAF’ed die must be subsequently cured Voiding None Must control of up to 300 sheets or 3 rolls. A noncon- manufacturer that has a silver filled DAF at higher temperatures around 150-165˚C DA Cure Issues Bleed out None Must control ductive 8” DDAF is around $8/wafer product will only sell to high volume for 1 hour. One of the biggest advantage Shrinkage at corners None Must dispense proper amount In Memoriam PROMEX INDUSTRIES but the conductive version is an order users offshore. This limit on suppliers of film over paste is the absence of out- of magnitude higher in cost. One major can make DAF less cost effective unless gassing or void formation during oven Table 1.

16 MEPTEC REPORT WINTER 2016 meptec.org meptec.org WINTER 2016 MEPTEC REPORT 17 Bance Hom

TECHNOLOGY TECHNOLOGY – Over the past few years, there has Five Industry-Leading Packaging Technologies IC packages for implementing next-generation devices to support the connected world of the future

Contributors Ron Huemoeller, Adrian Arcedera and Rama Alapati Amkor Technology 20 been a significant shift from PCs and notebooks to OVER THE PAST FEW YEARS, THERE perimeter, as is the case with wire bonds. next package platform to pick up where has been a significant shift from PCs and Flip-chip technology enables several ball WLCSP leaves off. notebooks to smartphones and tablets as grid array package families. Although Associating “low cost” with “flip chip” Amkor Technology drivers of advanced packaging innovation. WLCSP also uses interconnect bumps, may seem like an oxymoron because the Rama Alapati In an industry segment that has grown the main distinction between a WLCSP early adopters of flip-chip packages were smartphones and tablets as drivers of advanced packaging inno- accustomed to a multitude of package and a flip-chip package is that the after the high-performance devices like CPUs, options, consolidation could produce bump process, the WLCSP die is mounted graphical processing units (GPUs) and “The Big Five” advanced packaging plat- directly on the printed circuit board and chipsets. However, as flip-chip processes forms. These include low-cost flip chip, does not have a package substrate. have matured, the associated costs have wafer-level chip-scale package (WLCSP), While WLCSP has been the go-to been reduced, while still maintaining the Figure 1. As package to die ratio increases, there is more disparity between the FOWLP and fcCSP. microelectromechanical systems (MEMS), package of choice to meet mobile product performance benefits, making it the ideal laminate-based advanced system-in-pack- requirements, WLCSP reaches a point platform for other IC technologies such rently only suited to a small percentage WLCSP: The Workhorse of Advanced performing, most reliable semiconductor age (SiP) and wafer-based advanced SiP where it is limited by its die size and the as RF, FPGAs, ASICs, memory, CMOS of mobile, wireless, medical and military Packaging Technology package platforms on the market today. vation. In an industry segment that has grown accustomed to a designs. (See Determining the Big Five number of I/O it can support. According to image sensors, LEDs, and more. In fact, applications. A WLCSP is a single-die package, From a market perspective, WLCSP Amkor Technology below.) Yole Développement, that magic number the newest low-cost flip-chip solutions are While many industry analysts prosely- limited by the die size, which includes is ideally suited for, but not limited to, Adrian Arcedera is roughly 500, typically in an 8 x 8 mm² not only very cost competitive to FOWLP, tize FOWLPs as a lower-cost alternative wafer bumping (with or without pad layer mobile phones, tablets, netbook PCs, disk Low-Cost Flip Chip package. Many industry analysts view fan- but they are also competitive in thinness as to WLCSP than flip-chip CSPs (FCCSPs), redistribution), wafer-level final test, drives, digital still and video cameras, Unlike the other four platforms, flip out wafer-level packaging (FOWLP) as newer methods are implemented. FOWLP is lower cost only when the ratio device singulation and packing in tape navigation devices, game controllers, chip is not a package platform, but an the solution to the increased I/O problem, Additionally, despite the recent hype of the package body size to the die size and reel to support a full turnkey solution. other portable/remote products and some interconnect method that uses bumps since it enables higher density by expand- regarding FOWLP, it is important to is nearly the same or only slightly larger. Now in volume production, WLCSP automotive end applications. instead of wire bonds to connect the vari- ing the footprint to slightly larger than the remember that low-cost flip-chip packages Figure 1 illustrates this relationship. The is the workhorse of the Big Five advanced Perpetual innovation is intrinsic to ous circuits as well as attach the die to a die size - and has lower cost than the flip- are currently dominating the advanced cost of the redistribution layer (RDL) is packaging technologies due to its cost/ packaging success and focuses on driv- multitude of package options, consolidation could produce “The package substrate. In the case of flip chip, chip alternative today. However, emerging packaging market. Why? Because it’s integral to the overall cost of the pack- performance ratio resulting from the elim- ing existing technologies to lower cost connections are formed over the surface low-cost flip-chip solutions will provide still a better choice than FOWLP for age. Standard WLCSP has the lowest-cost ination of the package substrate. Packag- points. With the anticipated growth in the of the die area rather than at the package more viable alternatives and create the most applications. In fact, FOWLP is cur- RDL impact, although as previously men- ing considerations start with WLCSP, and WLCSP market, there are many reasons Yole Développement tioned, its package size is limited to die only move to other formats when routing for improving and optimizing the WLCSP Jean-Christophe Eloy size only. As the ratio of body size to die requirements exhaust the available real manufacturing process. A good example DETERMINING THE BIG FIVE size increases, low-cost FCCSP structures estate. Ultimately, customers will choose of optimization is the implementation of become more favorable from a price point WLCSP over the other package options die sidewall protection. Although most To zero in on the “the Big Five” semicon- Mobility IOT Automotive Memory HPC perspective. When the package body size where technologically possible because it WLCSPs are not molded, a method has ductor packaging technologies, a team is greater than 1 mm more than the die is the lowest-cost package. developed to provide mold-like die sur- Big Five” advanced packaging platforms. of packaging experts identified five key size, the cost for wafer-level redistribution Also known as fan-in wafer-level face protection. Using this approach, a platforms that they believe will be lever- 1. Low-Cost Flip-Chip Platform becomes sufficiently high making FCCSP packaging (FIWLP) industry-wide, WLC- molding compound is injected into the aged across a multitude of applications the best path for cost. SPs are applicable to a wide range of saw streets and then the wafer is diced and markets - both now and in the future. 2. WLCSP Platform As flip chip continues to evolve, it markets and are generally related to ana- again, creating five- and six-sided molded The selected platforms are currently in remains more economical and more reli- log and mixed-signal, wireless connec- WLCSPs (see Figures 2a and 2b). This Feldman Engineering Corp. different stages of adoption and produc- able than most fan-out packages. Invest- tivity and automotive device categories. process is currently available, and cus- Ira Feldman tion, and will hold up through generations 3. MEMS and Sensor Packaging Platform ments in low-cost FCCSP technologies Typical applications include integrated tomers are now designing it into their of development to continue serving the have created economies of scale and are passive devices, codec, power amplifiers, WLCSP requirements. industry needs. The figure shown at right 4. Substrate-Based SiP Platform driving down the unit cost. FCCSP’s use is IC drivers, RF transceivers, wireless local Die sidewall protection becomes lists the market segments (mobility, Inter- expanding beyond the computing, mobile area network chips, GPS and automotive even more critical as silicon nodes scale net of Things (IoT), automotive, high-per- and wireless markets, extending into auto- radar. WLCSP offers the lowest total cost beyond 14 nm to 10 nm and 5 nm, where 5. Wafer-Based SiP Platform formance computing (HPC) and memory) motive and medical, as well as the next of ownership, enabling higher semicon- the risk of potential sidewall damage RON HUEMOELLER, ADRIAN ARCEDERA AND RAMA ALAPATI and identifies which markets are served by big wave for low-cost applications: the ductor content while leveraging the small- intensifies due to brittle dielectrics, small- one or more of these platforms. The Big Five packages target different market segments. wearable device market for the IoT. est form factor. It is one of the highest- er bump pitches and more. Ron Huemoeller Amkor Technology 20 MEPTEC REPORT WINTER 2016 meptec.org meptec.org WINTER 2016 MEPTEC REPORT 21 AMKOR TECHNOLOGY Ron Jones N-Able Group International

Raj Peddi Henkel Adhesive Electronics 4 Member News 10 Industry Insights 28 Henkel News eda2asic Consulting, Inc. DEPARTMENTS Herb Reiter 8 Coupling & Crosstalk 24 SMART Microsystems News 30 Opinion Annette Teng Promex Industries

MEPTEC Report Vol. 20, No. 4. Published quarterly by MEPCOM LLC, 315 Savannah River Dr., Summerville, SC 29485. Copyright 2017 by MEPCOM LLC. All rights reserved. Materials may not be reproduced in whole or in part without written permission. MEPTEC Report is sent without charge to members of MEPTEC. For non-members, yearly subscriptions are available for $75 in the United States, $80US in Canada and Mexico, and $95US elsewhere. For advertising rates and information contact Gina Edwards at 408-858-5493, Fax Toll Free 1-866-424-0130.  MEMBER NEWS

 AMKOR COMPLETES Namics Technologies Announces Plans QUALIFICATION OF SWIFT™ PACKAGING for New Manufacturing Facility FOR ADVANCED Namics will maintain MOBILE, NETWORKING product quality and consis- & SIP APPLICATIONS tency throughout this relo- Amkor Technology Inc. cation as all raw materials, has recently announced type of equipment, operators, completion of product manufacturing process flow qualification for its inno- and parameters, manufactur- vative new Silicon Wafer ing environment and outgo- Integrated Fan-Out Tech- ing inspection procedures nology (SWIFT™). SWIFT will remain the same for is designed to handle the NAMICS TECHNOLOGIES natural disasters. The new both facilities. In addition, demanding requirements of has developed a plan to con- building will enhance their Namics will strictly maintain today’s advanced mobile, struct a new upgraded manu- stability of supply and create product traceability of all networking and system-in- facturing facility on the same an improved manufactur- manufactured lots before, package (SiP) applications. property as their current ing environment. When during and after the transi- SWIFT was named the head office factory in Niigata the construction of the new tion. “Device of the Year” at the City, Japan. Construction building is complete and Namics is committed to 3D InCites Awards cer- began in March 2016 with manufacturing equipment providing the highest quality emony in 2016. It was rec- completion targeted for April installed, Namics will begin products with superior sup- ognized for being “uniquely 2017. sampling products for quali- port in order to meet their developed to deliver a high The current manufactur- fication of the new facility. primary goal of total cus- yielding, high-performance ing building has been in use Once all products from the tomer satisfaction. package with the thinnest for many years and needs to new facility have been quali- Contact Regional Man- profile in the industry.” be replaced with an upgraded fied by their customers, they ager Brian Schmaltz at SWIFT is targeted for building that incorporates will decommission the cur- [email protected] production in the second the latest construction rent facility and remove the or call 408-516-4611 for half of 2017 at K5, Amkor’s standards for withstanding building. more information. ◆ state-of-the-art manufac- turing, research and devel- opment center in Incheon, Master Bond’s Thermally Conductive, High Temperature South Korea. www.amkor.com Resistant Epoxy Passes NASA Low Outgassing Tests CERTIFIED TO MEET ASTM E595 NASA ASE RECEIVES ISO  low outgassing standards, Master Bond 26262 CERTIFICATION EP46HT-2AO Black is well suited for the aero- FOR ITS KAOHSIUNG space, electronic, opto-electronic industries and FACILITY can be used vacuum environments. This two ASE has announced that component system blends thermal stability with its Kaohsiung, Taiwan facil- a high strength profile for a variety of bonding, ity has received the ISO sealing and encapsulation applications. 26262 certification from EP46HT-2AO Black combines superior TÜV NORD, a technical thermal conductivity of 9-10 BTU•in/ft2•hr•°F service provider that helps [1.2981-1.4423 W/(m·K)] and reliable electrical companies to validate the insulation with a volume resistivity exceed- safety of products and ing 1014 ohm-cm at room temperature. It has heat, which allows it to have a working life of services. ISO 26262 is a a glass transition temperature of 200-210°C over 24 hours. It has a forgiving 100 to 30-35 standard related to the and is serviceable over the wide temperature mix ratio by weight and upon mixing, this safety of electrical and range of -100°F to +500°F [-73°C to +260°C]. thixotropic system has a viscosity of 140,000- electronic systems within This dimensionally stable system delivers a 280,000 cps. It bonds well to metals, compos- a car and addresses pos- tensile strength of 6,000-7,000 psi, compres- ites, glass, ceramics, rubbers and many plastics. sible hazards caused by sive strength of 26,000-28,000 psi and tensile Master Bond EP46HT-2AO Black is ther- malfunctioning behavior lap shear strength of 1,400-1,600 psi at 75°F. mally conductive and electrically insulative of safety-related systems, EP46HT-2AO Black also withstands a variety adhesive, sealant and potting compound that including interaction of of chemicals including oils, water, acids, bases meets NASA low outgassing requirements. these systems. and fuels. Read more about Master Bond’s heat resistant www.aseglobal.com  Unlike most traditional two part epoxies, adhesives at www.masterbond.com or contact EP46HT-2AO Black cures with the addition of Tech Support at [email protected]. ◆

4 MEPTEC REPORT WINTER 2016 meptec.org Industry Veteran Nick Leonardi Joins SMART Microsystems Team to Expand Next Generation MEMS

Sensors Packaging and Assembly ACCREDITED opment engineering with CERT # 3558* companies such as LSI Logic and Advanced Micro Devices. Current industry activities include his participation on the MEPTEC Advisory Board, Arizona State Univer- sity Bio-Medical Engineering School Advisory Board and memberships with other Elec- tronics Industry Organiza- tions. Mr. Leonardi received a B.S. Degree in Materials NICHOLAS LEONARDI Engineering from Alfred Uni- has been retained by SMART versity, in New York State. Microsystems in the role of SMART Microsystems has Business Development, bring- gained momentum and is well ing over 25 years of industry positioned in MEMS Packag- Surface mounted device with delamination (red) along the entire experience with positions ing and Assembly, supporting length of several leads. This part ranging from product devel- demand for next generation would fail per J-STD-020 criteria. opment and manufacturing sensor related technologies, to sales and marketing, in with focus on Medical, Auto start-ups to the Fortune 100. and the Mil/Aero industries. Mr. Leonardi gained valuable For more about SMART ® technical sales, marketing Microsystems capabilities SonoLab is Your Lab and applications management and services contact Nick experience with companies Leonardi, Director of Business such as General Electric and Development, at nleonardi@ An ISO/IEC 17025:2005 Certifi ed Testing Lab* National Semiconductor. smartmicrosystems.com, call SonoLab, a division of Sonoscan®, is the world’s largest The transition to business 440-366-4203, or visit the inspection service specializing in Acoustic Micro Imaging development followed years company website at smartmi- (AMI). Through SonoLab, you’ll have access to the superior in manufacturing and devel- crosystems.com. ◆ image quality and reliable data accuracy of Sonoscan C-SAM® acoustic microscopes, plus the capabilities and careful analysis of the world’s leading AMI experts. KYOCERA Optical Blood-Flow Sensor is With worldwide locations, SonoLab® Services Among World’s Smallest for Wearable unmatched capabilities, • Component Qualifi cation Devices, Smartphones extensive experience to Industry Standards and the best equipment • Materials Characterization available, SonoLab gives and Evaluation KYOCERA CORPORATION HAS you the ability, fl exibility • High-Capacity Screening announced that it has developed and capacity you need and Lot Reclamation one of the smallest known optical to meet all your AMI • Failure Analysis and blood-flow sensors, which mea- requirements. Constructional Analysis sures the volume of blood flow • Inspection and Audit Services in subcutaneous tissue. With the • Custom Training sensor, Kyocera is researching a variety of mobile health (mHealth) applications such as monitor- To learn more visit sonoscan.com/sonolab ing stress levels or preventing dehydration, heatstroke and altitude *For U.S. Locations Only sickness by studying trends or changes in blood-flow volume as alerts for these conditions and developing algorithms for detection. Leveraging Kyocera’s expertise in miniaturization, the sensor – only 1mm high, 1.6mm long and 3.2mm wide – is designed for use in small devices such as mobile phones and wearable devices. 847-437-6400 • sonoscan.com The company will offer sensor module samples starting April 2017, and aims to commercialize the technology as a device by Elk Grove Village, IL • Silicon Valley, CA • Phoenix, AZ • England Philippines • Singapore • Shanghai • Taiwan March 2018. Visit www.kyocera.com for more information. ◆ meptec.org WINTER 2016 MEPTEC REPORT 5  MEMBER NEWS Intel Unveils Compute Card, a Credit  EXAR APPOINTS DIVISION VP OF Card-Sized Compute Platform CORPORATE QUALITY AND RELIABILITY INTEL HAS ANNOUNCED ware manufactur- Exar Corporation has a new modular compute plat- ers can opti- named David Matteucci form called the Intel® Com- mize for Division Vice President of pute Card along with a range their Corporate Quality and Reli- of partners who will be work- Intel is ability. Mr. Matteucci will be ing with Intel to help acceler- working with central to managing Exar’s ate the ecosystem of solutions a wide range of Quality and Reliability func- based on the Intel Compute particular partners who share tion as well as supporting Card. Intel has been a leader solutions – from their vision that the tier 1 engagements. in delivering technology to interactive refrigerators Intel Compute Card could Mr. Matteucci has over help realize the benefits of the and smart kiosks to security significantly change the way 30 years of experience in Internet of Things and enable cameras and IoT gateways. they and the rest of the indus- the semiconductor indus- more smart and connected Device makers simply design try design and productize a try, having held executive devices. The Intel Compute a standard Intel Compute wide range of solutions in the positions at Power Integra- Card is being developed with Card slot into their device near future. tions, Nano Nexus Inc., that in mind, to transform the and then utilize the best Intel The Intel Compute Card will Zoran Corporation, Galileo way compute and connectiv- Compute Card for their per- be available in mid-2017 and Technology, National Semi- ity can be integrated and used formance and price needs. will come with a range of conductor, as well as previ- in future devices. This reduces the time and processors options, includ- ously at Exar Corporation, The Intel Compute Card resources needed to design ing the latest 7th Gen Intel® where he served as Vice has all the elements of a full and validate the compute Core™ processors. For more President of Operations computer, including Intel block and helps speed up information and to stay up Engineering and Quality SoC, memory, storage and innovation to bring the power to date on the Intel Compute and Reliability. wireless connectivity with of intelligence into an ever Card, visit www.intel.com/ www.exar.com flexible I/O options so hard- wider range of devices. ComputeCard. ◆  TESSERA HOLDING CORP. COMPLETES Mendoza Elected ACQUISITION OF DTS Chairman of Promex accelerates time to market Tessera Holding Corpora- tion announced that it has JEDEC Microelec- from concept to prototype to production completed the acquisition tronics Committee of DTS, Inc. The Com- BEN MENDOZA, VICE pany’s combined portfolio President and General Manag- of products and technolo- er of Golden Altos Corpora- gies uniquely positions it tion, and newly elected Chair- to deliver smart sight and man of the JEDEC JC-13.2 sound solutions and next- Microelectronic Devices generation 3D semicon- Committee, begins his term at Mixed Assembly with SMT & Chip-wire ductor interconnect solu- this month’s JEDEC meeting • Medical devices (implantable, wearable, medtech equipment) tions for mobile devices, in San Antonio, Texas. • Redundant continuous flow SMT assembly consumer electronics, and Joining JEDEC in the lines >/= 01005 component placement automotive markets - while 1990s, Mr. Mendoza began • RoHS compliant and leaded solder systems also addressing the grow- • IPC-A-610 Class 3 assembly representing the semiconduc- ing potential of emerging tor industry and now leads the technologies such as IoT IC Packaging microelectronic devices sec- and AR/VR. The Com- • Hermetic, plastic, air-cavity, COB tion of this Government Liai- pany’s team of world-class • Multiple interconnect types son committee. In addition to engineers will focus on • Custom engineered flows (commercial, medical, military) being a member of JEDEC, the vision of creating core • Fast-track prototypes to production volumes Mr. Mendoza participates in • Class 100 and Class 1000 clean rooms technologies that power other industry task groups. intelligent, immersive and These include Copper Wire personalized digital experi- (Bonding), Plastic Encapsu- ences. The difference is in the engineering lated Microcircuits Flow for tesseraholdingcorporation.com ISO 13485:2003 ● ISO 9001:2008 ● ITAR Registered ◆ Space Applications, and the Mission Assurance Improve- www.promex-ind.com | 408-496-0222 ment Working Group. ◆

6 MEPTEC REPORT WINTER 2016 meptec.org MST Expands Its Sales SMART Microsystems Purchases Organization for US Mitutoyo Programmable Measurement East Coast System for MEMS Sensors Packaging THE MICRO SYSTEMS TECHNOLOGIES (MST) Group, a global provider of ing material in a fraction of the time it innovative components and manufactur- would take by conventional means. Lot ing services for high-reliability / high- basis geometric measurements can be performance industries, such as medical performed in minutes. With machine technology and aerospace & defense accuracy greater than 2+3L/1000, they has experienced strong market growth will also be using this system to perform in recent years. The group’s customer contract precision measurement services focused strategy and growing demand to customers at a highly competitive rate have resulted in a decision to expand their with very rapid turnaround times. US organization. MST is pleased to wel- SMART Microsystems creates turn- come Robert F. Baker to the company. key solutions for microelectronic pack- Effective October 10, 2016, Robert F. age assembly challenges to move your Baker was appointed Eastern Regional MEMS sensor technology from develop- Account Manager for Micro Systems SMART MICROSYSTEMS HAS ment to production. With an engineering Technologies, Inc. Prior to joining MST, announced the recent purchase of a new team experienced in manufacturing and Robert was Business Development Man- Mitutoyo Quick Vision ELF Coordinate state-of-the-art facilities, SMART Micro- ager for Janco Electronics, Inc. Bringing a Measurement Machine (CMM). As an systems accelerates the transition of your wealth of relevant industry technical expe- ISO9001 certified supplier to their valued new MEMS sensor product to the market. rience to the company, Robert will focus customers, SMART has an obligation to For more about SMART Microsystems his sales and technical support activities in insure, monitor, and maintain the qual- capabilities and services contact Nick the Eastern United States. ity of all incoming materials. This highly Leonardi, Director of Business Develop- Visit www.mst.com for more informa- accurate programmable non-contact and ment, at nleonardi@smartmicrosystems. tion about Micro Systems Technologies contact measurement system will allow com, call 440-366-4203, or visit the com- products and services. ◆ SMART to measure and certify incom- pany website at smartmicrosystems.com. ◆

Two Part Addition Cured Silicone 1-800-776-9888 MasterSil 972TC-LO

For bonding,

potting,

sealing Thermally conductive & coating 7–9 Service BTU in/ft² hr °F temperature range Electically -120°F to insulative +400°F Volume NASA low resistivity outgassing >10¹⁴ ohm-cm Passes ASTM E595

Hackensack, NJ 07601 USA +1.201.343.8983 • [email protected] www.masterbond.com

meptec.org 1066LK_2.25x4.6_MasterSil972TC-LO_40yr.indd WINTER 2016 MEPTEC REPORT 1 10/26/16 7 11:50 PM COLUMN

COUPLING & system, nor the company that installed it. but it was a master on/off “request” switch This may have been both a quality versus one that actually removed power CROSSTALK control failure or “escape” at the supplier from the entire system. Requiring a screw- By Ira Feldman and at the time of installation. Quality is driver to remove the back panel of the essential for any product or service. It closet to access the logic control system to Electronic coupling is the transfer of ener- is critical to determine how to assess and unscrew wires is neither user friendly nor gy from one circuit or medium to another. control the quality of any manufactur- the best design. This approach may have Sometimes it is intentional and sometimes ing or delivery process. Without proper enabled the product or the system instal- not (crosstalk). I hope that this column, by quality systems, one does not know if the lation to hit the desired aesthetic and cost mixing technology and general observa- process is out of control which may result targets, but clearly it wasn’t designed for tions, is thought-provoking and “couples” in big surprises later on. In the case of failure. with your thinking. Most of the time I will the hotel lights, it is clear that there was Many organizations “design” or stick to technology but occasional cross- a quality failure – either in the physical plan for success but they don’t consider talk diversions may deliver a message hardware or during installation – since designing for failures in quality, safety, closer to home. the system was clearly not operating as or security. We have come a long way in designed. Or, at least, how most “reason- product design over the last twenty years. able” users would expect. Perhaps there However, it is not clear that progress has Quality, Meet was a local tradition of punishing those been made in a user’s ability to remove who go to bed after 11 PM? the power source from many electronic Safety & Security! Luckily, enlightened product manag- devices. In the “real old days” of vacuum ers and designers do place quality on tubes almost all devices had a true  WHAT CAN BE SIMPLER TO their list of product requirements. But do “Mains” switch that cut the input power specify or install than a light bulb they always add safety and security? to the power transformer – i.e. the same controlled by a wall switch? Over- It depends on the perceived risk and as unplugging it. Because we are impa- engineered versions, especially when complexity of the product in addition to tient and desire “instant television”, sets developed without engineers, can really regulatory requirements (if any). Where moved from truly turning off to going into cause you to lose sleep. However, the most will agree that quality control is an standby mode. The television was really real nightmare is the danger of simple essential cost – especially when in the on (consuming power keeping the tubes products being hijacked by the Inter- long run it may save money – some trade- powered up) but simply not displaying a net. off or fail to consider safety and security picture on the cathode ray tube (CRT) to What keeps me up at night? Many in order to reduce cost. eliminate the need to “warm up”. Today, things… When I’m focused on a client’s In the case of the hotel lighting system LCD screens use very little energy so product requirements, it is making sure failure, there was clearly a lack of qual- there is little concern about them being they match true market needs. Plus, doz- ity in the design process at either the powered up all the time. Since most new ens of other non-work related things like control system or hotel design level since TV’s are connected to the Internet, per- my children, the recent presidential elec- the designers failed to consider the system haps we should instead worry about their tion, the economy, … Thankfully I easily failure modes. (Who knows if there were capability of watching the viewers! (Read fall asleep shortly after my mind starts to actual engineers on the design team?) again: George Orwell’s 1984.) rundown this very long list. [And yes, this is a recursive thought since History has repeated itself with smart- What actually kept me awake on my there is both quality of the manufacturing phones. In the quest for making them thin- recent business trip? Poor product qual- and delivery process in addition to the ner and smaller, most leading brands have ity, improper system design, and a lack quality of the design process itself.] Done removed the ability to remove the battery. of planning for failure. At a brand-new properly the system design would have Smartphones are never really off and a hotel the fancy multi-button bedside included a Failure Mode Effect Analysis “hard reset” is a request to reset versus a controls for the room lights and curtains (FMEA) to identify most, if not all, possi- true power on/off cycle. As Samsung just failed in two different rooms. In the first ble failure modes along with countermea- discovered with the Note 7 battery issues, room, the lights would intermittently not sures to eliminate or reduce the impact of changing to a non-removable battery led switch off. And in the second room, the the failures. Clearly the system was not to their being banned from airplanes as multiple ceiling mounted spotlights over designed to fail in a “safe mode”. these phones could not be safely carried in the bed would not switch off – at all - Failure of a switch? Use another a true “power off” state. when I attempted to go to sleep. There switch for the same function. Failure of a As products and devices become more was a considerable delay at midnight to curtain motor? Manually close the curtain. complicated, the digital circuitry and get a maintenance person to disconnect Failure of the logic control system? If the software become significantly difficult to the wiring in the hidden electrical control system could detect this, it should have thoroughly test. As such, the probability panel. Unlike a desktop or floor lamp, turned itself off. But not every device can of security holes, test escapes, or latent these lights were too difficult to reach be “self aware” to detect proper operation. defects (possibly introduced after test) to unplug or unscrew without a ladder. I This is where the designers failed to pro- increase with complexity. Even presum- admit I was not thinking kind thoughts vide a way for the user – not the mainte- ing robust quality and security processes, at that moment about the engineer who nance technician – to override the system. defects will occur. Therefore, it is essen- designed the system, the supplier of the Yes, there was a “Master” switch bedside tial for products to “fail safe” with unam-

8 MEPTEC REPORT WINTER 2016 meptec.org biguous methods so that a user can shut configured on the same network. In this “Murphy was an optimist”… down or reset a compromised or malfunc- case, the researchers were able to bypass In industries and product categories tioning device. Without these capabilities, the manufacturer’s security using sophis- that do not have governmental nor volun- beyond mere inconveniences, we are put- ticated techniques. They speculated on the tary safety and security standards, another ting ourselves at grave risk as the number ability to use a similar security breach to role(s) should be added to the cross- of autonomous devices increase by the cause mayhem from power grid failures functional design team to focus on safety day – everything from self-driving cars to to epileptic seizure. In theory, these bulbs and security. Either an internal resource drones. This risk is compounded by the are simpler “things” than web and security or, better yet, an external resource who sheer number of devices that comprise the cameras with no user controlled security can provide the required perspective and Internet of Things (IoT). The recent dis- features. breadth of experience to take an indepen- tributed denial of service (DDoS) attacks Combine these issues and add para- dent view is required. Yes, quality has using approximately 100,000 compro- noia to keep us all up at night? How fought hard for a seat at the product mised web and security cameras demon- about a worm/virus that takes control of development table and now it is time strated the power of a small number (rela- your smartphone and changes the battery for safety and security to join too! tive to the projected billions of the IoT) of charging parameters causing your battery For more of my thoughts, please see simple devices. It is estimated that there to exploding or ignite? my blog http://hightechbizdev.com. are over half a million of these infected In the development and design pro- As always, I look forward to hearing devices due to the manufacturer(s) ship- cess, product designers, engineers, and your comments directly. Please contact ping them with the same default password product managers need to think about me to discuss your thoughts or if I can be and the users choosing not to change failure modes and ways to make their of any assistance. ◆ them. products safe and secure. We need to Researchers at the Weizmann Institute add security and safety to design for IRA FELDMAN is the Principal Consultant of Feldman Engineering Corp. which guides high of Science recently demonstrated the abil- manufacturing, quality, support, etc. technology products and services from concept ity to spread a worm among Internet con- that is known as “DFx”. Beyond making to high volume manufacturing. He engages nected light bulbs via their ZigBee mesh a product elegant and intuitive to use, the on a wide range of projects including techni- radio network. The worm allowed them design team needs to worry about how cal marketing, product-generation processes, to take control of the light bulbs and to their product could be misused and what supply-chain management, and business devel- spread to neighboring bulbs that were not to do in case things go wrong. As it is said opment. ([email protected])

SMT, COB, COF, IC ASSEMBLY

SAME DAY, 1 - 5 DAYS TURN

AmTECH is a leading Silicon Valley provider for SMT, COB, COF and IC Assembly.

Gold ball, aluminum and gold wedge wire bonding, Automated Optical Inspection (AOI) and XRAY.

— SMT ASSEMBLY, Lead-Free, 0201, uBGA, CSP — COB, COF, IC ASSEMBLY, Cleanroom ISO 7 (Class 10,000), Aluminum and Gold wire — NPI - PROTOTYPE, 8, 24 to 72 hours turn — Low to Medium Volume PRODUCTION, MRP, IPC-A-610 Class 2 and 3, MIL-STD-883

Your NPI Manufacturing Solution! Phone (408) 227-8885 Email: [email protected]

www.amtechmicro.com meptec.org WINTER 2016 MEPTEC REPORT 9 COLUMN

INDUSTRY Acquirer Acquiree Amount INSIGHTS ON Anadigics $32 M By Ron Jones Microsemi PMC-Sierra $2,500 M Micron Tech Inotera Memories $3,200 M They’re Still Microchip Tech Atmel $3,600 M Dancing Sony Altair Semiconductor $220 M Cisco Systems Leaba Semiconductor $320 M  A YEAR AGO, I WROTE AN ARTICLE titled “Who’s Next on the Dance Floor.” GigOptics Magnum $54 M It’s focus was on the rapid rise in the Cypress Broadcom wireless IoT $550 M level of M&A activity in the semicon- ductor industry. Cavium QLogic $1,360 M For several years, semiconductor Softbank ARM, Inc. $32,000 M M&A had been averaging about $12 bil- lion per year. (See Table 1.) Analog Devices Linear Tech Corp (LTC) $14,800 M Renesas Intersil $3,200 M Year Semi M&A Beijing Mgmt Analolgix $500 M 2010 $ 7.7 B Inphi Clarify $275 M 2011 $ 17.0 B Qualcomm NXP $38,500 M 2012 $ 8.5 B TOTAL $101,111 M 2013 $ 11.5 B Table 2. Source: GSA Market Watch and Press Releases 2014 $ 16.9 B 2015 (approx.) $120.0 B masks. Many designs continue to go up want to get a piece of the pie. I believe in complexity, taking them beyond the the major factor in Qualcomm’s deci- Table 1. Source: IC Insights technical reach of smaller fabless compa- sion to acquire NXP is its penetration in nies. the automotive market to bolster Qual- I added up the deals in November, The Internet of Things (IoT) and comm’s small presence. 2015 and the total was just north of $100 other smart technologies are continuing Having been in the industry for sev- billion. You can’t get an exact count to grow and are becoming a focus for a eral decades and watching the fabless because not all deal sizes are disclosed lot of companies. To that end, companies model create hundreds and hundreds of and there is a time lapse between when are acquiring other companies that have new companies over the past 25 years, it deals are announced and when they close enabling products, technology or IP to is interesting to watch as consolidation . . . or don’t close. It’s a bit like counting position them for a market that is expect- reverses the trend to some degree with a room full of white cats. The general ed to experience rapid growth. It is not a growing number of mega fabless/IDM consensus is 2015 came in around $120 a matter of whether IoT will happen, but companies. Nothing is forever . . . except billion. rather in what myriad configurations it change. ◆ I don’t think there was any expecta- will reveal itself and how quickly it will tion that deals would stop just because grow over the next several years. RON JONES is CEO of N-Able we rolled from 2015 to 2016 . . . and that A new driver this year is the rapid Group International; a semiconduc- was indeed the case. rise in smart, autonomous vehicles of tor focused consulting and recruiting It is the end of the year again and the all sizes. Great strides have been made company. N-Able Group utilizes deep M&A tally is shown in the Table 2. in the last year and lots of companies At this point in time, it looks like semi supply chain knowledge and a 2016 will be similar to 2015 in number powerful cloud based software appli- cation to provide Conflict Mineral of deals in each size category and in total Deal Size 2015 2016 dollars. I excluded smaller deals that had Compliance support services to com- no given deal size. (See Table 3. 10 billion plus 4 3 panies throughout the semiconduc- As last year, the growth to some tor supply chain including fabless, 1 – 10 billion 5 5 degree is driven by trends that have been foundry, OSAT and materials suppli- going on for years, such as the increas- 0 – 1 billion 4 7 ers. Visit www.n-ablegroup.com or ing cost of mask sets. It is not unusual email [email protected] (Top 3 accounted for almost 85%) for leading edge designs to run in excess for more information. of $100 million, and that is just for the Table 3. Number of Deals by Deal Size

10 MEPTEC REPORT WINTER 2016 meptec.org ANALYSIS

Will Fan-Out Packaging be Sustainable Long-Term?

Jean-Christophe Eloy Yole Développement

Fan-Out History:

2016 WAS A TURNING POINT FOR A Long Development and a Recent Hype the Fan-Out packaging market since both leaders, Apple and TSMC changed the game and may create a trend of acceptance of Fan-Out packages. Yole Développement (Yole) is analyzing the current market and technologies trends and offers you to discover these results within a new report entitled Fan-Out: Technologies & Market Trends 2016. TSMC investment in Fan-Out Wafer Level Packaging (FOWLP) and development of its Integrated Fan-Out (InFO) changed the wafer level packag- ing (WLP) landscape. Following high volume adoption of InFO and further development of embedded Wafer Level Ball grid array (eWLB) technology, a Source: Fan-Out Technologies & Market Trends 2016 report, Yole Développement. wave of new players and FO WLP tech- nologies may enter the market. TSMC’s FO WLP solution called InFO will be it is also a major turn: processors sors, memories, etc. This market is used to package the Apple A10 applica- require thousands of connections more uncertain and will require new tion processor, implemented in the new while the FO market was essentially integration solutions and high perform- iPhone 7 series… The success of FO focused on limited IO count applica- ing FO packages but has a very high packaging platforms is so undeniable tions so far. potential. today. What will be the status of the market tomorrow? What are the next • Eventually, the potential for market Apart from TSMC, STATS ChipPAC steps of the leading FO players? Which spread is very high: the Apple brand is willing to make further investments technology will be the winning solu- brings more interest to the FO platform. powered by JCET, ASE extends its tions? partnership with Deca Technologies According to Yole’s advanced pack- while Amkor, SPIL, and Powertech are “Production starts in 2016 and rep- aging & semiconductor manufacturing in development phase eyeing future pro- resents a big change in the Fan-Out team, the market will actually be split duction. Samsung is seemingly lagging industry for several reasons”, confirms into two types: behind and is considering its options to Jérôme Azémar, Market & Technol- raise competitiveness. ogy Analyst, Advanced Packaging • The “core” market of FO, including “With such a high potential for the & Manufacturing at Yole. And he single die applications such as Base- high-density FO and solid growth of the explains: band, Power management, RF trans- core FO, the supply chain is also expect- ceivers, etc. This is the main pool for ed to evolve with a considerable amount • First of all, in terms of volume, cap- FO WLP solutions and will keep of investment in Fan-Out packaging turing the Apple processor market growing. capabilities”, asserts Jérôme Azemar is a big asset for Fan-Out technology. from Yole. Several players are already iPhone 7 phones are expected to be • The “high-density” FO market, start- offering FO WLP while many others are sold in more than 200 million units. ed by Apple application processor developing their competitive Fan-Out engine (APE) that will include larger platforms to enter the Fan-Out landscape • In terms of technology capability, I/O count applications such as proces- and enlarge their portfolio. ◆ meptec.org WINTER 2016 MEPTEC REPORT 11 PROFILE

UTAC - SINGAPORE - TEST CENTER OF EXCELLENCE UTAC HOLDINGS LTD AND ITS • Experienced Team (average years on the job) Final Test, Wafer Probe & Post-Test Processes: subsidiaries (UTAC), is a leading inde- • Engineering Managers 15 Years & Test Engineers 10 Years pendent provider of semiconductor • World Class Systems for OEE & Factory Systems with Online & Offline Engineering Analysis assembly and test services for a broad • Operations with intrinsic ownership for Quality & Pervasive Continuous Improvement Culture. range of integrated circuits including • Proven Project Management methodology used for NPI Qualification, Safe Launch, analog, mixed-signal, logic, memory Pre/Mass Production Release and radio frequency. UTAC is the 6th • Driving on-going Innovations, Benchmarking & Value Creations with solide alignment with ATE & largest OSAT in the world and among Systems Solutions Suppliers full-service assembly and test providers, • Wide range of configurations for Components, Integrated & Complex RF/Mixed Signal testing UTAC’s test percent of revenue is the solutions highest in the industry. • Sophisticated and Competitive Technical Roadmap for higher pin count and higher parallelism The Group offers a full range of • Superior WLCSP engineering experience including BSP, Side-Wall Protection & AVI/EOL package and test development, engineer- ing and manufacturing services and Medical / Automotive / Consumer / Industrial / Mobile Phone / Security solutions to customers who are primarily integrated device manufacturers (IDMs), fabless semiconductor companies, and wafer foundries. First established in 1997, the Group’s customers span across all vertical markets including: mobile phone and communication, consumer, comput- ing, automotive, security banking, and security identity, industrial and medical UTAC’s Thin QFN .3mm VS. Standard QFN applications. Striving to maintain diver- sity across end markets not only helps to provide balance in the ebb & flow of product demand, it also positions them KEY FACTS & FIGURES KEY SERVICES for growth in the overall industry with • Revenue $878 M (2015) • Assembly Research & Development significant benefits from the proliferation • Established in 1997 • Package Assembly of the Internet of Things (IoT). • HQ in Singapore • Test Engineering & Development As more devices become connected • Operations in 6 countries, 10 factories • Test Services to the IoT, the need to safeguard infor- • Approximately 12,000 employees • Quality Assurance mation from cyber assaults is driving • Worldwide Sales Team • Reliability & Failure Analysis an increased demand for secure creation • Services: Assembly 65% / Test 35% • End of Line & Drop Ship and management of devices and data. As a leading supplier of assembly and test services, UTAC plays a vital role in their customer’s manufacturing flow. Similar to quality initiatives, security compliance is regulated using industry standards and QFN Single Row Expose Die fcQFN Flip Chip QFN is administered at the UTAC corporate level. Today, 50% of UTAC’s factories are certified with EAL 6 / ISO standard ISO1540. QFN Dual Row Top Expose Pad QFN

12 MEPTEC REPORT WINTER 2016 meptec.org ASSEMBLY SERVICES UTAC offers a wide range of semi- conductor assembly services to meet customers’ needs and the increasing mar- CMOS Image Sensor ket demand for next generation devices. UTAC has a diverse capability spanning across ten factories, in six countries in the Asia Pacific region. Their packaging 5-Die Stacked (0.8mm) Smart Card Module Cu Clip QFN capability includes Leadless Packages, Module 2 FET + Clip + Controller Wafer Level Packages, System in Package (SiP), Laminate Packages, Leaded Pack- ages and Security Smart Card Module and 8-Die Stacked (0.9mm) Smart Card Inlay. To complement their packaging solu- fcBGA SiP (Solder) tions they have state-of-the-art design and GQFN-SiP package characterization capabilities to LGA-SiP (Multichip RF) help customers achieve both performance and cost objectives. UTAC engineering D2-fcFBGA (Hybrid) teams collaborate closely with customers to understand the performance require- ments and utilize proprietary calculators and design tools to accelerate the pack- age design phase. Once the design is approved, UTAC uses a proven project management methodology to facilitate the new product introduction, taking the prod- uct through a rigorous phase gate process to ensure first time qualification.

TEST SERVICES UTAC is a world leader in integrated circuits testing with more than 1,600 installed testers and a team of more than 300 experienced test engineers. Among full-service assembly and test providers, UTAC’s test percent of revenue is the highest in the industry. UTAC has wafer sort and final test capability in every fac- tory location to provide a full-turnkey product flow. UTAC has extensive experience and capability to test all semiconductor device types in the industry: analog, mixed sig- nal, logic, memory, CMOS image sensors, accelerometer MEMS sensors, radio fre- quency (RF) for radar, near field commu- nications (NFC) and other RFID devices. Their test solutions include wafer probe (ambient, hot and cold), security black box wafer level encryption, final test, O/S test, reliability and failure analysis. With a centralized test development engineering team, UTAC provides test development (TD) services to customers worldwide. TD engineers work closely with custom- ers to reduce costs and streamline process flows by ensuring test programs are opti- mized with the most effective test cover- UTAC is a world leader in IC testing with more than 1,600 installed testers and a team of more age and enable the shortest test times. than 300 experienced test engineers. Photo: UTAC Test Operation in Thailand. meptec.org WINTER 2016 MEPTEC REPORT 13 PROFILE

UTAC’S OFFERINGS SOLUTIONS & PARTNERS

Assembly Capability • 3-D Embedded Partners • Leadless Packages: QFN, multi-row • WLCSP Fan-In, Fan–Out and Solder Pillar Bump QFN, thin QFN, side-lead plating QFN, Cav- ity QFN, MEMS, Image Sensor and Cu Clip/ Design Rules & Roadmaps Alignment: Power & - Substrate Design • Wafer Level Packages: wafer thinning, pro- AT&S - Assembly Design tective coating, saw & laser dicing - Design Integration • System in Package (SiP): Laminate, Lead- less, FC-SiP, QFN-SiP, Multi-Die SiP Known Good Die (KGD) • Laminate Packages: PBGA, FCBGA, CSP, RDL Thin / Dice FBGA, WCSP, Inspect / Tape & Reel • Leaded Packages: PDIP, SOT, SOIC, TO, QFP Laser Diode • Smart Card Module Assembly & Inlay w/ EAL 6 Common Criteria Site Certification Substrate Manufacturing Embedded Chip AT&S Strip Test

SMT Top FC / Under Fill Cap or Mold Solder Ball Attach Package Saw

Package Level Test Test Services Reliability Test • High Volume Wafer Probe (Tri-Temp) • High Volume Final Test (Tri-Temp) • Security Black Box Testing/Encryption w/ EAL 6 Site Level Certification • Burn-In Services UTAC has established agreements with several IC Bump companies to provide seamless, com- • Reliability & Failure Analysis Testing plete turnkey backend solutions for Fan-In and Fan-Out WLCSP as well as Solder Pillar Bump • Production & Package Qualification for Flip Chip. This seamless solution begins with state-of-the-art Bump technology through UTAC Wafer Sort, End-of-Line Processing and Ship. Research & Development (Assembly / Test) • Package Design Consultation • Thermal, Mechanical & Electrical Modelling • Package Prototyping • Material Selection & Benchmarking • Test Program Development • Test Program Conversion BUMP CAPABILITY BY PRODUCT TYPE • Test Hardware Design & Layout

UTAC Design Centers provide one-stop design service for full range of packages.

14 MEPTEC REPORT WINTER 2016 meptec.org UTAC GROWTH MILESTONES

1997 United Test & Assembly Center Incorporated in Singapore (UTAC)

1998 Developed memory & DRAM turnkey test & assembly services

1999 Acquired test operations Fujitsu Microelectronics Asia

2003 Established China footprint in Shanghai 2005 Acquired Ultra Corp. to establish presence in Taiwan and add memory test and assembly services 2006 Acquired NS Electronics Bangkok to penetrate the Analog assembly market 2010 Acquired ASAT and its subsidiary in Dongguan, to enhance China footprint 2014 Acquired 3 Panasonic Plants; Singapore, Malaysia, & Indonesia; Launched Japan Sales Region and Offices 2015 Organic growth through product development and site certifications in key areas: MEMS, Cu Clip, Automotive & Security 2016 Qualification & high volume production ramp: MEMS, GQFN, Cu Clip, Automotive (SLP), & Security products: Smart Card Inlay, Smart Card Module, Secure IC Encryption Wafer Sort

UTAC FACILITY SNAPSHOT Dongguan, China Karawang, Indonesia Serangoon, Singapore Bangkok, Thailand Package Type Package Type: Package Type: Package Type: • QFN • QFP • WLCSP • QFN • QFP • SOP • FCCSP • FCQFN • FPBGA • TO • FCCSP - 95mm • GQFN • FCQFN • F-LD Singulation Saw • SMD • MODULE •TAPE/TAG • Cap • FCSMD • LGA Operational Certs: • FCBGA Operational Certs: Operational Certs: ISO9001 (1999), • BGA OHSAS18001, ROHS, OHSAS18001, ISO14001 (2000), • COB/CVM Certified Sony Green Partner, ISO14001, ISO27001 (2009), Operational Certs: TS16949, ISO14001, ISO9001:4003, OHSAS18000 (2011), ISO 9001, TS16949, EAL 6 Site TS16949, EAL 6 Site ISO14001,18001, QC08000 AEC-Q100, ISO/IEC27001, Hsinchu City, Taiwan Malacca, Malaysia ISO/IEC17025, EAL 6 Site Package Type: Shanghai, China Package Type: • WLCSP Ang Mo Kio, Singapore Package Type: • SOT(SMD) • BGA • LGA •TO(Power) Package Type: • LGA • BGA Operational Certs: • CLCC/LGA Operational Certs: • QFN ISO9001:2008 (2012), • BGA ISO9001/QS9000, Operational Certs: TS16949:2009 (2012), • QFN OHSAS18001, TQM, ISO 9001:2005, ISO14001:2004 (2013), • SOP ISO14000, QC080000, ISO 14001:2008, ISO18001:2007 • LDHU ISO9001, ISO/TS16949, OHSAS18001:2012 • TO ANSI ESD S20.20 Operational Certs: ISO9001:2008, S16949:2009, ISO14001:2004, O18001:2007 meptec.org WINTER 2016 MEPTEC REPORT 15 APPLICATIONS

Die Attach Film Applications Annette Teng Chief Technology Officer Promex Industries

DIE ATTACH FILM (DAF) AND DICING they use a subcontractor who has a well- die attach film (DDAF) have been com- stocked inventory. The cost per wafer of mercially available since 2000. Epoxy silver filled DAF may be higher, but with paste adhesives have historically been the savings in process steps and yield the sole epoxy material available for die improvement, the cost is very compa- attach, an integral part of component rable to paste. assembly, in particular for wire-bonded Currently both conductive and non- devices, but not quite applicable for conductive DDAF films are commer- flip chip assembly. DAF and DDAF are cially available at various thicknesses. epoxy adhesives which are film based Most suppliers provide 20 to 25µm as a instead of paste based and are attached standard thickness option. Lower 10µm to the back of the wafer prior to dicing. thickness DAF is available but maybe DAF is sold by the supplier without a Figure 1. Photo provided by Lintec. a challenge to procure for low volume support dicing tape, whereas DDAF is users. Electrically and thermally conduc- sold by the supplier on a stretchable sup- tive silver filled films are also available port dicing tape which is partially sawn at 20-25µm thickness and have been and subsequently poked by ejector nee- deployed at Promex for many QFN dles during automated die pick. DDAF device assemblies. QFNs with silver has gained popularity due to the many DDAF have passed JEDEC MSL3 for advantages of film over paste, driven 8x8mm QFN from Promex. However, especially by the growth of stacked many high-end applications require high- die architecture. Because there is no er thermal conductivity and have resorted re-shaping of adhesive material from a to DAF with diamond fillers instead. drop-shape to a thin 2 dimensional layer, Promex has been assembling multi- the process window for film is much die stacks with diamond filled DAF suc- wider than for paste material. Engineer- cessfully. Figure 2 shows a cross-section ing intensive processes to control fillet of a 7-die stack die device using a dia- shape, overflow, under-coverage and mond filled film. The silicon wafers have voiding are eliminated by the use of Figure 2. 7-die stack with high thermal been thinned to 200µm before laminating conductive DAF. films. For very thin dies as well as for onto the diamond filled DAF. The die on stacked dies, it is imperative to use film. the device wafers with DAF were sin- There are a handful of suppliers of gulated using a dual spindle dicing saw wafer level DAF. Major suppliers pro- as shown in Figure 3. Saws with single vide the circular DAF sheets in rolls spindle are not recommended as adhe- for automatic machine lamination such sive stringers and conjoining of die may as shown in Figure 1. DAF can also be result. After singulation, die attach using sourced as sheets for non-automated a Datacon 2200 with a heated stage was lamination. DDAF and DAF material performed. Each die is pressed down have a shelf life of 6 to 12 months when on a heated substrate at a force recom- stored at 0-10˚C. They can also be stored mended by the supplier which keeps the at room temperature, but the expiration die firmly anchored in place. An example date is shortened by about half. Hence, of a wafer with silver epoxy DAF during the material is only made to order and Figure 3. DDAF dicing on dual spindle saw. Datacon pick is shown in Figure 4. All major suppliers impose a minimum order DAF’ed die must be subsequently cured of up to 300 sheets or 3 rolls. A noncon- manufacturer that has a silver filled DAF at higher temperatures around 150-165˚C ductive 8” DDAF is around $8/wafer product will only sell to high volume for 1 hour. One of the biggest advantage but the conductive version is an order users offshore. This limit on suppliers of film over paste is the absence of out- of magnitude higher in cost. One major can make DAF less cost effective unless gassing or void formation during oven

16 MEPTEC REPORT WINTER 2016 meptec.org Accept (left) Reject (right)

Figure 4. Singulated die on Silver filled Figure 5. Adhesive presence on backside Figure 6. DAF stringer. DDAF being picked by the Datacon. of die. cure. The effect on die tilt and die shift- Figure 5. Poor adhesion may be traced affecting wirebond integrity. Saw dic- ing caused by void formation has been to contaminants such as polydimethylsi- ing parameters must be optimized to a challenge for paste users, particularly loxane (PDMS)[1] which can be removed eliminate such stringers. Another reject is for large dies. The bondlines of stacked by Argon gas plasma cleaning. A pass/ conjoined die found during pick which is die of various DAF brands after cure are fail criteria set at greater than 95% DAF caused by inadequate adhesive singula- found to be consistently uniform. visible on die backside is acceptable for tion due to improper blade depth or worn High yield can be attained by good good die shear strength. out blades. Lasers can be used for the quality control of DDAF material and Wafers with DAF that are diced with singulation of DAF wafers however, this wafer backside cleanliness. Contami- improper dicing parameters may exhibit is only cost effective for high volume nants either from mishandled DAF or a adhesive stringers in the saw streets as manufacturing. mishandled wafer can result in problems shown Fig 6. This is rejectable as the Die attach films can also be applied with missing adhesive film as shown in stringers may cover bond pad openings to non-die attach processes such as lid

ADVANTAGE COMPARISON DIE ATTACH FILM DIE ATTACH PASTE

Paste Dispense machine set-up Engineering intensive & more None (less set-up dies) Requirement of dies/wafers set-up dies/wafers

Batch oven curing 1hr at 150C-165C Partial cure OK with full cure Must Cure 100% prior to UPH improvement during wirebond wirebond

Die to pad size ratio 1.0 Less than 0.9

Die strength during pick Reinforced by DAF No reinforcement

Wafer warpage during handling Reinforced by DAF No reinforcement

Bondline Consistent Must monitor

Con-joined dies Must control during saw None Die pick Issues Missing adhesive Must control during prep None Stringers Must control during saw None

Die tilt and fillet issues None Must monitor

Pot life before cure Hours/day Minutes<4hrs

Voiding None Must control DA Cure Issues Bleed out None Must control Shrinkage at corners None Must dispense proper amount

Table 1. meptec.org WINTER 2016 MEPTEC REPORT 17 APPLICATIONS

sealing and wafer bonding. At Quik-pak, where Open molded cavity plastic pack- ages (OmPP) are made in array form as shown in Figure 7, various DAF materi- als were evaluated for sealing a large panel lid. OmPP are made by molding walls on QFN lead frames with standard thermoset mold compounds. OmPP packages can be temporarily sealed to Figure 9. provide engineers with the flexibility to test and debug rapidly. They can also be Sample Force (Kgf) effectively overmolded by dispensing epoxy to fill the cavity and curing. And, Figure 7. 1 14.831 these cavity packages can be lid-sealed for MEMS and sensor products. Lid seal- 2 11.588 ing can be done either individually or in 3 13.370 panel form utilizing DAF, with a prefer- ence for the latter for cost savings. Table 2. Lid shear results in excess of 10Kg A comparison of 5 DAF types from for a 28 leaded OmPP QFN package. several suppliers showed one DAF type that produced 100% yield on lid seal Summary and Conclusion integrity. For each DAF type, a panel In this article, DAF is shown to be of OmPP packages, namely, QFNs, was well established as a standard die attach Figure 8a. panel lid sealed under thermal compres- material and can also work as a lid seal sion and then saw singulated. One DAF material for open cavity panels. Many product yielded 108/108 pass on visual in types of DAF, including silver filled 10X magnification with no voids on all 4 electrically conductive, diamond filled sides of the singulated QFNs. Figures 8a thermally conductive as well as non- and 8b shows the sidewall of the ceramic conductive DAF for various complex lid over the QFN with a very uniform microelectronic assemblies have been ◆ bondline of 20-25 µm in thickness of successfully implemented. DAF. 15/15 units passed after been sub- References jected to a Fluorinert™ leak test (Mil. [1] “Delamination from Process Induced Sources” Std. 883 Method 1014 Condition C1) A. Teng C., IEEE Electronic Component & Technol- Figure 8b. ogy Conference, San Diego, June 1-4, 1999 with no preconditioning to catch leakers by the presence of escaping bubbles. on both lid and package surfaces (Figure Acknowledgements Furthermore, lid shear of the lidded 9). Table 2 shows the lid shear results in The author would like to acknowledge Dr. Suzette Pangrle and Anthony Lazala of Promex and Ilene QFN showed high strength with adhesive excess of 10Kg for a 28 leaded OmPP Arciaga, previously of Quik-pak for their work on fracture as revealed by adhesive residues QFN package. DAF.

15TH ANNUAL MEMS AND SENSORS TECHNOLOGY SYMPOSIUM

SAN JOSE, CA 6.06.2017 TURN INSPIRATION INTO ELECTRONICS INDUSTRY INNOVATION

www.IPCAPEXEXPO.org

CONFERENCE & EXHIBITION FEBRUARY 14-16 MEETINGS & COURSE S FEBRUARY 1 1-16

Tuesday, February 14, 2017 | 8:30am-9:30am Mayim Bialik, Actress & Neuroscientist “The Big Bang Theory - Making Science Cool (and Funny)”

Wednesday, February 15, 2017 | 8:00am-9:00am Mary (Missy) Cummings, Naval Officer, Military Pilot & Professor, Duke University “The Future of Drones”

SAN DIEGO CONVENTION CENTER CALIFORNIA | USA TECHNOLOGY

Five Industry-Leading Packaging Technologies IC packages for implementing next-generation devices to support the connected world of the future

Ron Huemoeller, Adrian Arcedera and Rama Alapati Amkor Technology

OVER THE PAST FEW YEARS, THERE perimeter, as is the case with wire bonds. next package platform to pick up where has been a significant shift from PCs and Flip-chip technology enables several ball WLCSP leaves off. notebooks to smartphones and tablets as grid array package families. Although Associating “low cost” with “flip chip” drivers of advanced packaging innovation. WLCSP also uses interconnect bumps, may seem like an oxymoron because the In an industry segment that has grown the main distinction between a WLCSP early adopters of flip-chip packages were accustomed to a multitude of package and a flip-chip package is that the after the high-performance devices like CPUs, options, consolidation could produce bump process, the WLCSP die is mounted graphical processing units (GPUs) and “The Big Five” advanced packaging plat- directly on the printed circuit board and chipsets. However, as flip-chip processes forms. These include low-cost flip chip, does not have a package substrate. have matured, the associated costs have wafer-level chip-scale package (WLCSP), While WLCSP has been the go-to been reduced, while still maintaining the microelectromechanical systems (MEMS), package of choice to meet mobile product performance benefits, making it the ideal laminate-based advanced system-in-pack- requirements, WLCSP reaches a point platform for other IC technologies such age (SiP) and wafer-based advanced SiP where it is limited by its die size and the as RF, FPGAs, ASICs, memory, CMOS designs. (See Determining the Big Five number of I/O it can support. According to image sensors, LEDs, and more. In fact, below.) Yole Développement, that magic number the newest low-cost flip-chip solutions are is roughly 500, typically in an 8 x 8 mm² not only very cost competitive to FOWLP, Low-Cost Flip Chip package. Many industry analysts view fan- but they are also competitive in thinness as Unlike the other four platforms, flip out wafer-level packaging (FOWLP) as newer methods are implemented. chip is not a package platform, but an the solution to the increased I/O problem, Additionally, despite the recent hype interconnect method that uses bumps since it enables higher density by expand- regarding FOWLP, it is important to instead of wire bonds to connect the vari- ing the footprint to slightly larger than the remember that low-cost flip-chip packages ous circuits as well as attach the die to a die size - and has lower cost than the flip- are currently dominating the advanced package substrate. In the case of flip chip, chip alternative today. However, emerging packaging market. Why? Because it’s connections are formed over the surface low-cost flip-chip solutions will provide still a better choice than FOWLP for of the die area rather than at the package more viable alternatives and create the most applications. In fact, FOWLP is cur-

DETERMINING THE BIG FIVE

To zero in on “the Big Five” semiconductor Mobility IOT Automotive Memory HPC packaging technologies, a team of pack- aging experts identified five key platforms that they believe will be leveraged across 1. Low-Cost Flip-Chip Platform a multitude of applications and markets - both now and in the future. The selected 2. WLCSP Platform platforms are currently in different stages of adoption and production, and will hold up through generations of development to 3. MEMS and Sensor Packaging Platform continue serving the industry needs. The figure shown at right lists the market seg- 4. Substrate-Based SiP Platform ments (mobility, Internet of Things (IoT), automotive, high-performance computing (HPC) and memory) and identifies which 5. Wafer-Based SiP Platform markets are served by one or more of these platforms. The Big Five packages target different market segments.

20 MEPTEC REPORT WINTER 2016 meptec.org Figure 1. As package to die ratio increases, there is more disparity between the FOWLP and fcCSP. rently only suited to a small percentage WLCSP: The Workhorse of Advanced performing, most reliable semiconductor of mobile, wireless, medical and military Packaging Technology package platforms on the market today. applications. A WLCSP is a single-die package, From a market perspective, WLCSP While many industry analysts prosely- limited by the die size, which includes is ideally suited for, but not limited to, tize FOWLPs as a lower-cost alternative wafer bumping (with or without pad layer mobile phones, tablets, netbook PCs, disk to WLCSP than flip-chip CSPs (FCCSPs), redistribution), wafer-level final test, drives, digital still and video cameras, FOWLP is lower cost only when the ratio device singulation and packing in tape navigation devices, game controllers, of the package body size to the die size and reel to support a full turnkey solution. other portable/remote products and some is nearly the same or only slightly larger. Now in volume production, WLCSP automotive end applications. Figure 1 illustrates this relationship. The is the workhorse of the Big Five advanced Perpetual innovation is intrinsic to cost of the redistribution layer (RDL) is packaging technologies due to its cost/ packaging success and focuses on driv- integral to the overall cost of the pack- performance ratio resulting from the elim- ing existing technologies to lower cost age. Standard WLCSP has the lowest-cost ination of the package substrate. Packag- points. With the anticipated growth in the RDL impact, although as previously men- ing considerations start with WLCSP, and WLCSP market, there are many reasons tioned, its package size is limited to die only move to other formats when routing for improving and optimizing the WLCSP size only. As the ratio of body size to die requirements exhaust the available real manufacturing process. A good example size increases, low-cost FCCSP structures estate. Ultimately, customers will choose of optimization is the implementation of become more favorable from a price point WLCSP over the other package options die sidewall protection. Although most perspective. When the package body size where technologically possible because it WLCSPs are not molded, a method has is greater than 1 mm more than the die is the lowest-cost package. developed to provide mold-like die sur- size, the cost for wafer-level redistribution Also known as fan-in wafer-level face protection. Using this approach, a becomes sufficiently high making FCCSP packaging (FIWLP) industry-wide, WLC- molding compound is injected into the the best path for cost. SPs are applicable to a wide range of saw streets and then the wafer is diced As flip chip continues to evolve, it markets and are generally related to ana- again, creating five- and six-sided molded remains more economical and more reli- log and mixed-signal, wireless connec- WLCSPs (see Figures 2a and 2b). This able than most fan-out packages. Invest- tivity and automotive device categories. process is currently available, and cus- ments in low-cost FCCSP technologies Typical applications include integrated tomers are now designing it into their have created economies of scale and are passive devices, codec, power amplifiers, WLCSP requirements. driving down the unit cost. FCCSP’s use is IC drivers, RF transceivers, wireless local Die sidewall protection becomes expanding beyond the computing, mobile area network chips, GPS and automotive even more critical as silicon nodes scale and wireless markets, extending into auto- radar. WLCSP offers the lowest total cost beyond 14 nm to 10 nm and 5 nm, where motive and medical, as well as the next of ownership, enabling higher semicon- the risk of potential sidewall damage big wave for low-cost applications: the ductor content while leveraging the small- intensifies due to brittle dielectrics, small- wearable device market for the IoT. est form factor. It is one of the highest- er bump pitches and more. meptec.org WINTER 2016 MEPTEC REPORT 21 TECHNOLOGY

MEMS Packaging all types advanced packaging expertise Many leading companies and industry to integrate different MEMS and sensor experts predict that the growing trend for functionalities with data processing ICs smart devices (smart cars, smart cities, in multi-die packages. FlipStack CSP smart factories and more) will result in the technology is an example of sensor fusion, deployment of a trillion sensors, many of where the bottom ASIC die is a flip chip, which will use MEMS technology. How- and the MEMS die is stacked on top and ™ ever, MEMS devices are not standard inte- Figure 2a. 5-sided molded WLP (CSPnl wire-bonded to reduce the overall package technology). grated circuits. Creative wafer fabrication footprint. techniques produce Si-based transducers Advanced MEMS packaging platforms and actuators that respond to or interact will be essential to achieving the deploy- with, external or environmental stimulus. ment of anything close to a trillion sensors. At the onset of MEMS packaging, priority was given to solving the end- Laminate-based Advanced SiP market application over cost and package Traditional laminate-based SiP solu- form factor. This created a broad diversity tions have existed for some time and have of package form factors, with a different been manufactured by electronic manufac- approach for almost every application turing services (EMS) providers with print- and end market. As the MEMS market ed circuit board (PCB) assembly design grows and transitions into high-volume rules and relaxed form factors. Advanced production, package and test standardiza- laminate-based SiP solutions, on the other tion is needed to offer cost-competitive Figure 2b. Top-down view of 5S molded hand, are more complex systems that are solutions without sacrificing performance. WLP (CSPnl technology). miniaturized using tighter and smaller out- The requirement to control stress to the sourced assembly and test (OSAT)-based MEMS structure while allowing stimulus outside to maintain maximum compatibil- assembly capabilities. Advanced laminate- to go through remains the same. The com- ity during assembly, final test and surface based SIP solutions serve a higher end of bination of a standard cavity packaging board mount. The standard MEMS plat- the market. This is the case for 4G/LTE RF platform and optimized material sets will forms will also allow the use of other pack- front end modules (FEMs) which require ensure a near-stress-free environment that aging techniques like FlipStack® technol- the complex integration of filters, mixers, allows the MEMS device to function as it ogy, through silicon via (TSV), Cu pillar demodulators, amplifiers and discretes in was designed to in the real world. and die stacking for MEMS sensor fusion a highly dense form factor with ultra-low Amkor’s focus is creating a standard and IoT applications. Figure 3 shows interconnect parasitics. cavity package platform that will provide examples of these packaging approaches. Advanced SiPs integrate disparate the flexibility to support multiple MEMS Sensor fusion, where software com- technologies, such as a small microproces- applications. It will be customizable on bines the data from different sensors to sor with embedded memory, a sensing the inside while remaining standard on the reduce application uncertainty, leverages element such as a MEMS device or image

Figure 3. MEMS and sensor standard package platforms.

22 MEPTEC REPORT WINTER 2016 meptec.org sensor, RF die and power management ICs in a very small form factor. In these designs, it is not unusual to find various different interconnects such as wire bond, 3D TSV SWIFT flip-chip and WLCSP BGA along with sur- Memory Logic face mounted components. Interposer The laminate-based advanced SiP qualifies as one of the Big Five packaging technologies because it fits the bill for new market growth areas, providing a great 2.5D TSV SLIM deal of value in terms of form factor and increased functionality at a cost point that Figure 4. Wafer-based SiP offerings. accelerates product penetration in new and existing markets. For example, laminate- HPC, memory and high-end mobility. Over based advanced SiP family include high- based SiP solutions can enable miniaturized time, however, more devices will take density fan-out wafer-level packages such cost effective solutions in the consumer and advantage of wafer-based SiP technology as the SWIFT™ and SLIM™ product lines. industrial IoT space, since they integrate to enable extreme form factor reductions These configurations use a “die last” increased functionality and component and increased product performance at approach that minimizes the yield loss risk counts in very small form factors. lower power. prevalent in the complex die first WLFO Laminate-based SiP solutions that are While laminate-based SiP leverages packages. SWIFT is expected to ramp to currently in production achieve the lowest the existing die scale infrastructure, wafer- production in the next few quarters and form factor at cost and performance points based processes differ significantly from become a predominant driver of wafer- that address market needs in RF, storage, laminate-based processes and require based advanced SiP products. The SLIM automotive, IoT and power segments. In investment in wafer processing tooling. and SWIFT small body sizes have passed addition, a core design kit enables custom- Wafer-based SiP replaces and/or comple- chip-package interaction (CPI) qualifica- ers to do module and substrate design and ments the laminate substrate, providing tions, with large body sizes in develop- also supports system modeling, character- RDL line/space (l/s) features down to 1 µm ment. Also on the wafer-based advanced ization and full turnkey services to achieve x 1 µm. A wafer-based SiP RDL can scale SiP roadmap are 2.5D interposer and 3D the smallest form factors and fastest time to fab back end of line (BEoL)-like dimen- IC stacks. The 2.5D TSV is available to market. sions, whereas traditional laminate-based today, having been qualified since 2013. advanced SiPs are currently limited to 10 Working with ecosystem partners provides Wafer-based Advanced SiP µm x 10 µm l/s. Therefore, wafer-based a seamless supply chain and qualified Si Similar to a laminate-based advanced SiP systems provide the best-in-class (BiC) portfolio and also enables co-design by SiP, a wafer-based advanced SiP allows scaling capability and have the ability to providing design kits for each of the wafer- for the integration of complex and dis- scale to fab-like dimensions. based SiP platforms. Figure 4 shows these parate technologies, but meets the higher There are increased costs associated packaging approaches. performance requirements for bandwidth, with wafer-based SiP due to the complex- form factor and density requirements in ity of the products produced. One of the Advanced Packages for Today and high-performance computing (HPC), IoT, contributors to the increased costs com- the Future mobility and automotive segments. In addi- pared to laminate-based advanced SiP is The mobility market is driving form tion to integrating basic microprocessors, the capital expenditures (CapEx) required factor reduction and high-density inter- sensing elements (MEMS or image sen- to build a platform for wafer-based pro- connects for multi-die integration. In the sors), RF dice and power management ICs, cesses in Class 1 or Class 10 cleanrooms. HPC, networking, deep learning and GPU a wafer-based advanced SIP can integrate Fab-like infrastructure and additional applications, wafer-based advanced SiPs memory (high bandwidth memory (HBM), toolsets including those used for traditional address the power, memory bandwidth and Hybrid Memory Cube (HMC), and oth- front-end processes such as physical and latency issues of new devices coming to ers), ASIC devices and high-performance chemical vapor deposition (CVD) tools, the market in the next couple of years. The processors, such as GPUs and FPGAs. chemical mechanical planarization (CMP) 2.5D, 3D, SLIM and SWIFT technologies This final segment of the Big Five is the tools and temporary bond/debond systems, can potentially help OEMs and fabless technology that serves the widest scope of contribute to the increased upfront costs companies delay migration to the next applications. required to enable wafer-based SiP plat- node by enabling system-scaling approach- The wafer-based advanced SiP is cur- forms. As the tools and factories depreci- es through wafer-based SiP technology. rently targeted for high-end devices and is ate, the manufacturing costs of wafer-based Wafer-based advanced SiPs round out still in the early introduction phases to the advanced SiPs will be reduced, enabling a the Big Five portfolio, allowing continued industry. It effectively addresses system- wider set of applications to take advantage innovative choices that will help achieve scaling needs and can help offset or delay of the form factor reduction and significant the best performance, form factor and the need for next-generation Si node based product performance increases. value-to-cost ratio for any application. ◆ products. Its initial market entry points are Package configurations in the wafer- meptec.org WINTER 2016 MEPTEC REPORT 23 Your Microelectronic Package Assembly Solution for MEMS Sensors

Gel Dispense for Encapsulation of MEMS Pressure Sensors

AS THE MEMS-BASED SENSING industry grows, the environmental conditions in which these sensors must perform grow with it. Pressure sensing is one application of MEMS-based sensing where particularly harsh environments can be present. Examples of common challenging environmental conditions include automobile exhaust, fuels, refrig- erants and atmosphere with moisture and ice. Unlike previous technology, which used large mechanical assemblies and welded or soldered interconnects in the fluid path, the MEMS-based technology offers the ability to place the micro- scopic sense element and wire bond interconnects directly in the fluid path. Figure 1. X-ray of die and wire bonds after gel dispense. As a result of the harsh environment and exposed assemblies, it is often necessary 1) complete gel coverage of critical com- under pressure and apply unintended and to protect the sense element and intercon- ponents, 2) elimination of all air voids in potentially damaging stress on the sense nects with products such as encapsula- the gel, 3) proper and complete cure, and element and on the interconnects. This tion gels. 4) a controllable process with a measur- can cause premature output shift or prod- The first step in the process of pro- able output. uct failure. Most silicone gels are hygro- tecting exposed MEMS-based assemblies Attaining and maintaining complete scopic in nature—they readily absorb is to select the proper gel for the design gel coverage over all critical components moisture. In typical product designs the intent of the product and for the environ- seems like a straightforward process. hygroscopic gel is placed in the fluid ment in which it will serve. Protective Verification of the gel dispense process path. The hygroscopic nature of the gel gels have come a long way in recent ensures coverage of all critical compo- and exposure to the fluid path will cause years with a virtually endless selection nents, but with shrinking product packag- the gel to collect moisture in any air of silicone dielectric encapsulation gels. es and complex layouts, an unobstructed voids present. The moisture-filled voids Typically encapsulation gels are selected view of critical areas is not often obtain- immediately become a source of cor- based on desired final product properties, able. At SMART Microsystems, analysis rosion. For process engineers that have such as viscosity after cure and chemi- techniques, such as acoustic microscopy experience in gel dispense procedures, cal properties best suited for the end-use and 3D X-ray, are used to develop and preventing air voids is the primary condi- environmental conditions. The manufac- validate gel dispense procedures during tion that must be accommodated during turing procedures for using gel are often the initial design process (see Figure 1). product and process design. This requires overlooked in the initial design process, These tools allow inspection inside of the careful vacuum degas of the gel prior to and must be reconciled by the process part after dispense, confirmation that the dispense, with additional centrifuge use engineering team. product is properly protected, and veri- as needed due to the intrinsic properties Once the design is complete, a fication that the gel dispense parameters of the gel. A post-dispense degas may process is developed by the engineer- have achieved the desired result. also be required due to product design, ing team to properly apply the correct The root cause for the prevailing gel such as if the product geometry entraps amount of gel to best serve the end-use dispense failure mode which plagues air. application without creating unintended most MEMS-based sensor product Heat cure encapsulation gels are the consequences. These requirements designers is air voids trapped in the gel. preferred choice for many MEMS-based compel the satisfaction of four critical For pressure sensors with gel in the fluid sensor products because they offer a factors during the application process: path, entrapped air in the gel will move complete cure. Heat cure encapsulation

24 MEPTEC REPORT WINTER 2016 meptec.org AEROSPACE AUTOMOTIVE DEFENSE DEVICE MANUFACTURERS MEDICAL ENVIRONMENTAL INSTRUMENTS & CONTROLS FOOD & AGRICULTURE MANUFACTURING ENERGY NETWORKING & COMMUNICATIONS When You Need Reliable MEMS & Sensor Interconnects Make the SMART Choice.

PROTOTYPE DEVELOPMENT • ENVIRONMENTAL LIFE TEST • MANUFACTURING SERVICES

Creating robust and reliable interconnects for new technologies presents a series of new obstacles. Despite this, problems encountered as a result of custom packaging, unique geometry, and unusual material limitations can be overcome. Using a combination of well understood processes (such as wire bonding), emerging technologies (such as isotropic conductive adhesive) combined with creative engineering, SMART Microsystems can develop reliable interconnect processes for your new technology.

SMART Microsystems creates turn-key solutions for microelectronic package assembly challenges to move your MEMS sensor technology from development to production. With an engineering team experienced in manufacturing and state-of-the-art facilities, SMART Microsystems accelerates the transition of your new MEMS sensor product to the market.

Call us today at 440-366-4203 or visit our website for more information about SMART Microsystems capabilities and services.

Your Microelectronic Package Assembly Solution for MEMS Sensors 141 Innovation Drive, Elyria, Ohio 44035 • [email protected] www.smartmicrosystems.com Your Microelectronic Package Assembly Solution for MEMS Sensors

Figure 2. Thermocouple embedded into the gel of a specially modified part. gels are typically dispensed at a lower viscosity to promote flow and complete coverage. After the material has been SMART’s precision automatic dispense degassed and dispensed, it must be prop- equipment. erly cured to achieve the final viscosity to protect the product. In order to estab- Not all MEMS sensor designs require lish the proper cure profile for the gel, dielectric encapsulation gel protection, as recommended by the manufacturer, it but many on the front-line of harsh envi- Figure 3. Shot weight test coupon. is necessary to characterize the process. ronmental sensing do. It is important A calibrated thermocouple reader and to the end-use product viability that the a fine wire thermocouple are used in fications. Gel dispense processes pose process of protective gel encapsulation order to characterize the specific cure unique, but surmountable, challenges to is designed and validated properly. Engi- oven profile. The fine wire thermocouple quantification. At SMART Microsystems, neers at SMART Microsystems under- is embedded into the gel of a specially highly accurate and precise measurement stand from experience that encapsulation modified part (see Figure 2). The thermal and dispense tools are used in the design, gel is not simply a corrective action to a gradient of the gel will always lag the development, and production phases of preexisting failure mode. Gel encapsula- thermal gradient of the cure oven. Cure gel encapsulation. The dispense process tion is a process which is performed with characterization ensures a proper and is designed using precise mass scales and equal diligence in design and develop- complete cure of every part every time. with accurate programmable dispensing ment to wire bonding, die attach, assem- Product specifications and require- units to deliver a precise shot weight of bly, and many other process crucial to the ments that cannot be measured or quan- gel material in every part (see Figure end-use sensor and the same diligence is tified serve little purpose. Therefore, 3). This type of process design provides observed throughout production. a process must be designed which is exceptional results with measurable out- For more information about SMART controllable and which has a measurable puts that can be controlled through statis- Microsystems services visit their website output in order to meet product speci- tical process control (SPC). at www.smartmicrosystems.com. ◆

The SMART Advantage. Lowest Overall Development Time and Cost.

PROTOTYPE DEVELOPMENT ENVIRONMENTAL LIFE TEST MANUFACTURING SERVICES

• Proof of Concept and Feasibility • Identify Reliability Issues • Scale Up • Process Development • Avoid Issues in Field of Use • Low-volume Production • Engineering Expertise • Turnkey Testing and Overflow Support • Quality Assurance

26 MEPTEC REPORT WINTER 2016 meptec.org OPINION

 continued from page 30 their capabilities in form of Assembly Design Kits (ADKs).

How Can IC Designers, EDA and IP Vendors, Foundries and Assembly Houses Work Together The rest of this article will focus on the importance of ADKs and the roles of and data/product flow between these five EcoSystem partners. It also will outline how ADK and reference flow enable multi-die IC designers to walk the nar- row road between costly over-designs and risky/unreliable under-designs. Together with die-level IP building blocks, ADK and reference flow offer a solid platform for multi-die IC design. This “three legged stool” will encourage many more IC designers to evaluate and choose multi-die solutions. Only then the IC manufacturers will be able to recoup their already significant investments in Green: IC Designer & Wafer Foundry, Yellow: Package Designer and Assembly House, multi-die IC manufacturing equipment, Blue: EDA Vendors’ contributions, Red: 3rd party IP Vendors’ contributions flows and newly formed relationships with supply chain partners. Figure 2. Multi-die IC EcoSystem. Figure 2 outlines the Multi-die IC EcoSystem and shows in green how all in die form, are other examples for level IP building blocks can be manu- the proven fabless/foundry cooperation how 3rd party IP complements and add factured in their most suitable process dovetails into the emerging Assembly value to one or more proprietary SoC technologies, they offer lower cost per Design Flow and how 3rd party IP build- die(s). function and best performance per Watt. ing blocks contribute to multi-die design The yellow part shows that the role and manufacturing. of EDA is to automate development of How Close is Such an EcoSystem to This modular approach, combining ADKs and to provide tools for planning, Becoming Reality? one or more proprietary dies, manufac- design and verification of multi-die ICs. Parts of this design/manufacturing tured in their most suitable process tech- Like foundries, assembly houses benefit EcoSystem have been in use for many nology, with one or more 3rd party IP significantly from highly automated years, to design and assemble SiP and building blocks demonstrates how simi- flows for characterization of package PoP multi-die ICs. lar such a modular multi-die IC design materials and active as well as passive Amkor and Cadence announced in project is to a system design approach components. Streamlined model creation Spring 2016 the start of a joint Package and how much flexibility it offers, while is also important. Data encryption pro- Assembly Design Kit (PADK) develop- significantly improving performance and tects proprietary know-how. Designers ment, in support of advanced IC packag- reducing power, development cost and appreciate user-friendly tools, accurate ing technologies. time to profit. and up-to-date information about multi- Please contact them or your EDA and The green portion of Figure 2 also die assembly flow as well as materials, assembly partner(s) to learn about their shows that multi-die IC technologies DO components and equipment capabilities. current capabilities and plans. ◆ NOT REPLACE our proven SoC tech- These help designers significantly to nology. To the contrary, they integrate minimize iterations and reduce time to HERB REITER founded eda2asic Consulting, proprietary SoC dies as differentiators profit and enable them to walk the nar- Inc. in the spring of 2002 with the intention to into the multi-die EcoSystem and add row road between costly over-design and focus on increasing the cooperation between to these SoCs more market value by risky/unreliable under-design. EDA suppliers and semiconductor vendors. Herb earned an MBA at San Jose State Uni- combining such proprietary designs with The red arrows show how 3rd party versity and Master Degrees in Business and off-the-shelf 3rd party IP. The high band- IP can flow into the design steps as Electrical Engineering at the University and width memory cubes (HBMs) are such models and into the manufacturing steps the Technical College in Linz/Austria, respec- 3rd party die-level IP building blocks, as die-level IP building blocks, to be tively. Herb has also taken more than forty already in use. SERDES dies, data con- combined with the customers’ proprietary Continuing Education courses at Stanford verters, power management ICs (PMICs), die-level IP building blocks. Because die- University in recent years. meptec.org WINTER 2016 MEPTEC REPORT 27 Everything-Proof: The Future of Mobile and Wearable Devices

Raj Peddi at 30 days and 90 days. A long pot life Henkel Adhesive Electronics allows manufacturers to minimize waste, as the adhesive can cope with continuous use for up to 60 days with no material degradation. In addition to these benefits, CONSUMERS’ GROWING DEPENDENCE LOCTITE ECCOBOND LS 3106P has on mobile devices now extends well exceptionally low weight loss, indicating beyond the communications realm and minimal outgassing for robust performance. into health, fitness, entertainment, trans- The lens module’s operation is dependent portation and more. With this reliance on upon the optical lenses, so any outgassing smartphones, fitness bands and connected promotions of the sort. However, reaching during the cure process could fog the lens watches also comes huge expectations: true waterproof status for the entire phone, and affect the performance of the camera. expectations for reliability, expectations for watch or fitness band is a tall order but one Henkel’s waterproof sealant remains stable enormous functionality, expectations for where significant progress is being made. during UV curing without any outgassing, exceptional design and, yes, expectations The product design and material selection ensuring predictable lens operation. LOC- for extreme durability. considerations for ensuring water resistance TITE ECCOBOND LS 3106P also exhibits In the early days of smartphones, users are immense and extend from the PCB, very low shrinkage, which is critical for were generally happy if they could drop where conformal coatings play an impor- fragile, thin lenses and alignment accuracy their phone with little consequence. The tant role, to sealants for camera modules as shrinking of the material post-cure can ability to cope with an occasional spill of and, yes, even elimination of external jacks result in shifting alignment or impaired a common beverage or sweat during those and connector ports. lenses. With no change in linear shrinkage 6 a.m. workouts was also a nice-to-have. As a leading provider of adhesive solu- post-cure, LOCTITE ECCOBOND LS As reliability and environmental durabil- tions for camera module assembly, Henkel 3106P protects against lens misalignment ity incrementally improved, so, too, did has developed a full suite of materials that and/or damage. consumer demands. The quest for more enable advanced camera module technol- While all of these material properties features in shrinking dimensions continues ogy – from lens bonding to attachment of are critically important, LOCTITE ECCO- to place huge pressure on thermal manage- the lens holder to the substrate to voice BOND LS 3106P’s primary function is ment, protection of exceptionally small and coil motor bonding and everything in waterproofing and here, too, the adhesive delicate components, EMI capability and between. Now, in a new breakthrough, delivers. In waterproof simulation testing, reliable interconnects. Remarkably, many Henkel has developed a waterproof sealing LOCTITE ECCOBOND LS 3106P sur- of these challenges have already been adhesive for camera module lens bond- vived complete water submergence. The addressed. High-performance, re-workable ing – yet another milestone on the path to test vehicle was sealed with the adhesive underfills, capable thermal materials in pad, fully waterproofed smartphones. LOCTITE and submerged in water for 24 hours at film and liquid formats, unique package- ECCOBOND LS 3106P is an optically room temperature, following which it was level EMI alternatives and game-changing clear adhesive that effectively seals all of exposed to an 85°C/ 80% relative humidity solder pastes have, indeed, enabled the the lenses within a lens house bonding for (RH) environment. The material showed no smallness, performance and reliability of both auto focus and fixed focus lenses, water leakage or swelling following the 24 today’s mobile devices. protecting the optical components against hour submergence or the 85° C/85% RH Now what? Top on the wish list has to damage from water. exposure. be waterproof durability. Water resistance The new adhesive has a low thixotropic Henkel’s LOCTITE ECCOBOND LS is something consumers have longed for index, making it ideal for filling the small 3106P is one of many elements required and considered by some as a virtual smart- gaps present in a lens assembly. This mate- for the waterproofed smartphones and phone utopia. As most smartphone owners rial characteristic allows LOCTITE ECCO- wearables of the modern era. With suc- have probably experienced the unfortunate BOND LS 3106P to flow easily without cess already proven with newer-generation result of a wet mobile phone, the idea added pressure and provides excellent devices, LOCTITE ECCOBOND LS 3106P that this could someday be avoidable is coverage for complete self-sealing. What’s is helping to facilitate the future of mobile enticing. To be sure, leading smartphone more, the thixotropic index of LOCTITE durability. manufacturers have already made moves ECCOBOND LS 3106P shows very little To find out more, visit www.henkel- in this direction, as evidenced by recent change over time with similar performance adhesives.com/electronics. ◆

28 MEPTEC REPORT WINTER 2016 meptec.org TThehe smaller smaller the the device device - -the the more more solutions solutions

NoNo matter matter where where you you are are or orwhat what your your process process requires, requires, you you can can count count on on Henkel‘s Henkel‘s expertise. expertise. OurOur unmatched unmatched portfolio portfolio of ofadvanced advanced materials materials for for the the semiconductor semiconductor and and assembly assembly markets markets all all backedbacked by by the the innovation, innovation, knowledge knowledge and and support support of ofHenkel‘s Henkel‘s world-class world-class global global team team ensures ensures youryour success success and and guarantees guarantees a low-riska low-risk partnership partnership proposition. proposition. OPINION

Assembly Design Kit (ADK) for Multi-die ICs Moving from Moore’s Law to More-than-Moore is like the change from IDMs to the fabless model

Herb Reiter eda2asic Consulting, Inc.

IT TOOK SOME TIME TO TRANSITION our industry from the IDM model to the well-functioning cooperation between fabless IC vendors and foundry partners. In addition to establishing new business models, IC designers and wafer foundry experts as well as EDA vendors and IP providers needed to be trained in how to best work together. To make the technical cooperation between these four camps low risk, efficient and cost effective, they jointly built an EcoSystem with these major elements: a) Process Design Kits (PDKs), to con- vey the foundry capabilities and con- straints, b) Low-level libraries, memory compil- ers, soft and hard IP blocks and c) User friendly Reference Design Flows, to enable IC designers to fully utilize a) and b) Figure 1. Revenues for heterogeneous functions exceeded the worldwide revenues for digital functions in 2015. These are still the key elements for success of the rapidly expanding fabless / wearable as well as other applications How to Broaden Market Acceptance foundry cooperation. demand smaller packages. In addition, for More-than-Moore Technologies As further shrinking of transistor market needs for higher performance Apple and other early adopters feature sizes is getting much more costly and lower power have encouraged the (Hynix, Micron, Samsung, AMD, IBM, and difficult, both in regards to IC devel- IC manufacturing community to develop Marvell, Nvidia, Xilinx, …) have dem- opment time, NRE and transistor cost, a range of advanced IC packaging tech- onstrated, that more of the value creation following Moore’s Law is no longer eco- nologies, such as 2.5/3D-ICs and, more and product differentiation is shifting nomical for many medium to higher vol- recently, multi-die Fan-out Wafer-level from the die to the IC package. These ume applications. Also as semiconductor Packages (FO-WLP). technology pioneers have, in close coop- experts notice, demand for heterogeneous Recent iPhone 7 teardown reports eration with their supply chain partners, function is increasing rapidly. Figure 1 confirm that Apple chose TSMC’s new contributed significantly to maturing the shows that the revenues for heteroge- InFO packaging technology to verti- supply chain for multi-die IC design and neous functions already exceeded the cally stack logic and a DRAM, to save manufacturing. Just like the quality of worldwide revenues for digital functions footprint, increase bandwidth as well as wafer suppliers’ PDKs significantly influ- in 2015. reduce cost, latency and power of the ences customers’ selection of foundry Advanced packaging technologies A10 application processor. This high- partners, now it is becoming important (PoP and SiP) are offering proven ways volume design is accelerating the devel- that assembly houses offer customers to combine multiple known good dies opment of similar advanced packaging detailed and up-to-date information about (KGDs) in one package. However, foot- technologies at other foundries and at print and height limitations for mobile, assembly & test houses (OSATs). continued on page 27 

30 MEPTEC REPORT WINTER 2016 meptec.org Packaging Solutions for Smartphones and Tablets

Wafer Level Chip Scale Packages Laminate-Based Advanced SiP Wafer-Based Advanced SiP Low-Cost Flip Chip MEMS

Enabling a Smart World As one of the world’s largest suppliers of outsourced semiconductor packaging, design, assembly & test services; Amkor helps make “next generation” products a reality.

CONNECTING People and Technology www.amkor.com

C or . Magazines and Carriers for Process Handling Solutions

Film Frames Film Frame Film Frame Shippers Grip Rings Magazines

Grip Ring Magazines Grip Ring Shippers Lead Frame Stack Magazines - Magazines - F.O.L./E.O.L. E.O.L.

Process Carriers Boat Magazines I. C. Trays - I. C. Tubes and Rails (Boats) Multi-Channel

Miscellaneous Substrate Carrier TO Tapes & Wafer Carriers Magazines Magazines Magazines

Accept Nothing Less.

Perfection Products Inc. 1320 S. Indianapolis Ave. • Lebanon, IN 46052 Phone: (765) 482-7786 • Fax: (765) 482-7792 Check out our Website: www.perfection-products.com Email: [email protected]