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DUAL-OUTPUT LOW-DROPOUT LINEAR REGULATOR Datasheet

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DUAL-OUTPUT LOW-DROPOUT LINEAR REGULATOR Datasheet TPS767D301-EP www.ti.com SGLS327A –FEBRUARY 2006–REVISED APRIL 2010 DUAL-OUTPUT LOW-DROPOUT LINEAR REGULATOR Check for Samples: TPS767D301-EP 1FEATURES • Controlled Baseline • 1-mA Quiescent Current During Shutdown – One Assembly/Test Site, One Fabrication • Dual Open-Drain Power-On Reset With Site 200-ms Delay for Each Regulator • Extended Temperature Performance of –55°C • 28-Pin PowerPAD™ TSSOP Package to 125°C • Thermal Shutdown Protection for Each • Enhanced Diminishing Manufacturing Sources Regulator (DMS) Support • Enhanced Product-Change Notification PWP PACKAGE (TOP VIEW) • Qualification Pedigree 1 28 Component qualification in accordance with JEDEC and industry NC 1RESET standards to ensure reliable operation over an extended NC 2 27 NC temperature range. This includes, but is not limited to, Highly 1GND 3 26 NC Accelerated Stress Test (HAST) or biased 85/85, temperature 1EN 4 25 1FB/NC cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing 1IN 5 24 1OUT should not be viewed as justifying use of this component beyond 1IN 6 23 1OUT specified NC 7 22 2RESET performance and environmental limits. NC 8 21 NC • Dual Output Voltages for Split-Supply 2GND 9 20 NC Applications 2EN 10 19 NC • Output Current Range of 0 mA to 1.0 A Per 2IN 11 18 2OUT Regulator 2IN 12 17 2OUT • 3.3-V/Adjustable Output NC 13 16 NC NC 14 15 NC • Fast Transient Response • 3% Tolerance Over Load and Temperature NC − No internal connection • Dropout Voltage Typically 350 mV at 1 A • Ultra-Low 85-mA Typical Quiescent Current DESCRIPTION/ORDERING INFORMATION The TPS767D301-EP dual-voltage regulator offers fast transient response, low dropout (LDO) voltages, and dual outputs in a compact package and incorporates stability with 10-mF low-ESR output capacitors. The TPS767D301-EP dual-voltage regulator is designed primarily for DSP applications. This device can be used in any mixed-output voltage application, with each regulator supporting up to 1 A. Dual active-low reset (RESET) signals allow resetting of core logic and I/O separately. Table 1. ORDERING INFORMATION REGULATOR 1 REGULATOR 2 TJ TSSOP (PWP) VO VO –55°C to 125°C Adjustable (1.5 V to 5.5 V) 3.3 V TPS767D301MPWPREP 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 2006–2010, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. TPS767D301-EP SGLS327A –FEBRUARY 2006–REVISED APRIL 2010 www.ti.com DESCRIPTION/ORDERING INFORMATION (CONTINUED) DROPOUT VOLTAGE vs LOAD TRANSIENT RESPONSE FREE-AIR TEMPERATURE 100 103 VO = 3.3 V µ 50 CL =100 F IO = 1 A T = 25°C A 102 oltage − mV 0 − Change in O V ∆ −50 101 Output V oltage − mV −100 A IO = 10 mA 100 1 − Dropout V 0.5 DO V 10−1 0 V = 3.3 V O IO = 0 CO = 10 µF O I − Output Current 10−2 0 2040 60 80 100120 140 160 180 200 −60−40−20 0 20 40 60 80 100 120 140 t − Time − µs TA − Free-Air Temperature − °C Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (typically 85 mA over the full range of output current, 0 mA to 1 A). These two key specifications yield a significant improvement in operating life for battery-powered systems. This LDO device also features a sleep mode; applying a TTL high signal to enable (EN) shuts down the regulator, reducing the quiescent current to 1 mA at TJ = 25°C. The RESET output of the TPS767D301-EP initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS767D301-EP monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage. The TPS767D301-EP is offered in an adjustable version (programmable over the range of 1.5 V to 5.5 V). Output voltage tolerance is specified as a maximum of 3% over line, load, and temperature ranges. The TPS767D301-EP is available in a 28-pin PWP (TSSOP) package. The device operates over a junction temperature range of –55°C to 125°C. TPS767D3xx 5 28 RESET VI IN RESET 6 IN 250 kΩ 24 OUT V C1 O 4 23 0.1 µF EN OUT C 50 V + O 10 µF GND 3 Figure 1. Typical Application Circuit (Fixed Versions) for Single Channel 2 Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated Product Folder Link(s): TPS767D301-EP TPS767D301-EP www.ti.com SGLS327A –FEBRUARY 2006–REVISED APRIL 2010 FUNCTIONAL BLOCK DIAGRAM Adjustable Version (for Each LDO) IN EN RESET _ + OUT + 200-ms Delay _ R1 Vref = 1.1834 V R2 GND FUNCTIONAL BLOCK DIAGRAM Fixed-Voltage Version (for Each LDO) IN EN RESET _ + OUT + 200-ms Delay R1 _ Vref = 1.1834 V FB/NC R2 GND External to the device Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Link(s): TPS767D301-EP TPS767D301-EP SGLS327A –FEBRUARY 2006–REVISED APRIL 2010 www.ti.com TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NAME NO. 1GND 3 Regulator 1 ground 1EN 4 I Regulator 1 enable 1IN 5, 6 I Regulator 1 input supply voltage 2GND 9 Regulator 2 ground 2EN 10 I Regulator 2 enable 2IN 11, 12 I Regulator 2 input supply voltage 2OUT 17, 18 O Regulator 2 output voltage 2RESET 22 O Regulator 2 reset 1OUT 23, 24 O Regulator 1 output voltage Regulator 1 output voltage feedback for adjustable version and no connect for fixed-output 1FB/NC 25 I version 1RESET 28 O Regulator 1 reset 1, 2, 7, 8, 13–16, NC No connection 19–21, 26, 27 TIMING DIAGRAM VI Vres Vres See Note A. t V V V IT+ IT+ O See Note B. See Note B. Threshold Voltage Less than 5% of the output voltage VIT− VIT− t ÎÎ RESETÎÎ Output 200-ms 200-ms ÎÎ ÎÎ Delay Delay ÎÎ ÎÎ Output Output ÎÎ ÎÎ Undefined Undefined ÎÎ ÎÎ ÎÎ ÎÎ t ÎÎ ÎÎ A. Vres is the minimum input voltage for a valid RESET. The symbol Vres is not currently listed within EIA or JEDEC standards for semiconductor symbology. B. VIT – Trip voltage typically is 5% lower than the output voltage (95% VO). 4 Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated Product Folder Link(s): TPS767D301-EP TPS767D301-EP www.ti.com SGLS327A –FEBRUARY 2006–REVISED APRIL 2010 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT (2) VI Input voltage range –0.3 13.5 V VI Input voltage range 1IN, 2IN, EN –0.3 VI + 0.3 V 1OUT, 2OUT 7 VO Output voltage V RESET 16.5 Peak output current Internally limited HBM ESD rating 2 kV Continuous total power dissipation See Dissipation Rating Table TJ Operating virtual junction temperature range –55 150 °C Tstg Storage temperature range –65 150 °C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to network ground terminal. Table 2. DISSIPATION RATING TABLE AIR FLOW T ≤ 25°C DERATING FACTOR T = 70°C T = 85°C PACKAGE A A A (CFM) POWER RATING ABOVE TA = 25°C POWER RATING POWER RATING 0 3.58 W 35.8 mW/°C 1.97 W 1.43 W PWP(1) 250 5.07 W 50.7 mW/°C 2.79 W 2.03 W (1) This parameter is measured with the recommended copper heat-sink pattern on a four-layer PCB, 1-oz copper on 4-in × 4-in ground layer. For more information, refer to TI technical brief literature number SLMA002. Recommended Operating Conditions MIN MAX UNIT (1) VI Input voltage 1IN, 2IN 2.7 10 V (2) IO Output current for each LDO 0 1 A VO Output voltage range 1OUT, 2OUT 1.5 5.5 V TJ Operating virtual junction temperature –55 125 °C (1) To calculate the minimum input voltage for maximum output current, use the following equation: VI(min) = VO(max) + VDO(max load) (2) Continuous output current and operating junction temperature are limited by internal protection circuitry, but it is not recommended that the device operate under conditions beyond those specified in this table for extended periods of time. Copyright © 2006–2010, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): TPS767D301-EP TPS767D301-EP SGLS327A –FEBRUARY 2006–REVISED APRIL 2010 www.ti.com Electrical Characteristics Vi = VO(nom) + 1 V, IO = 1 mA, EN = 0, CO = 10 mF (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TJ = 25°C VO 1.5 V ≤ V ≤ 5.5 V, Adjustable O 10 mA < I < 1 A TJ = –55°C to O 0.97VO 1.02VO (1) 125°C VO Output voltage V TJ = 25°C 3.3 4.3 V < VI < 10 V, 3.3-V output T = –55°C to 10 mA < IO < 1 A J 3.201 3.366 125°C Quiescent current (GND current) 10 µA < IO < 1 A, TJ = 25°C 85 mA for each LDO(1) IO = 1 A, TJ = –55°C to 125°C 125 Output voltage line regulation 0.01 ΔV /V V + 1 V < V ≤ 10 V, T = 25°C %/V O O for each LDO(1) (2) O I J BW = 200 Hz to 100 kHz, VO = 1.8 V, Output noise voltage 55 µVRMS IC = 1 A, CO = 10 mF, TJ = 25°C Output current limit for each LDO VO = 0 V 1.7 2 A Thermal shutdown junction temperature 150 °C TJ = 25°C 1 2.7 V < VI
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