A Flexible Platform for Network Processing
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A FLEXIBLE PLATFORM FOR NETWORK PROCESSING Kurtis B. Kredo II, Dr. Albert A. Liddicoat, Dr. Hugh M. Smith, Dr. Phillip L. Nico California Polytechnic State University, San Luis Obispo 1 Grand Avenue, EE Department San Luis Obispo, CA 93407 United States [email protected], (aliddico, husmith, and pnico)@calpoly.edu ABSTRACT and new algorithms or techniques are developed for Much of the current research in computer networks security applications. Software-based network devices focuses on providing increasing levels of functionality at provide a programmable base to support these advanced very high bandwidths. Traditional implementations using and changing functions, but they are unable in most cases application specific integrated circuits (ASICs) can to support very high data rates [3, 4]. process data very quickly, but do not allow modification Current research generally uses one of two when protocols or algorithms change. Software-based technologies to perform network processing at high implementations provide the ability to change bandwidths. Software-based implementations often use a functionality very easily, but often can not support high network processor, such as the Intel IXP1200, to bandwidths. The third generation Cal Poly Intelligent implement the required functionality. Alternatively, some Network Interface Card (CiNIC), presented in this paper, researchers focus development of reprogrammable combines the speed of hardware implementation with the hardware-based systems that utilize Field Programmable flexibility of a software-based system by using field Gate Arrays (FPGAs). Researchers have investigated programmable gate arrays (FPGAs) and a hardcore other technologies, however network processors and processor to perform network protocol processing. FPGAs are the predominant implementation devices. Utilizing the CiNIC within a network device allows A review of current work and an overview of the developers and researchers to implement additional project described in this paper are provided in the next functionality in various ways. The CiNIC Platform has two subsections. Sections 2 and 3 describe the been developed for flexibility and may be used for a architecture of the CiNIC presented in this paper and broad range of research and development projects conclusions are provided in Section 4. including hardware/software co-design, embedded systems, and distributed systems. 1.1 Current Work KEY WORDS At least two research groups, one from Georgia Network Interfaces, Computer Networks, Protocol Institute of Technology and another from Princeton Offloading, Reprogrammable Devices, Intelligent NIC University, have used Intel IXP network processors for research projects. The authors in [5] describe a software programmable router that uses an Intel IXP1200 network 1. Introduction processor and a PentiumIII general-purpose processor. Computational resources are logically divided into three Current advances in fiber optic technology have made functional layers with the lowest level (the IXP1200 large amounts of bandwidth available in computer MicroEngines) performing common data plane processing networks as users have placed increasing demands upon and the PentiumIII at the highest level performing control network devices [1, 2, 3]. Providing hardware that can plane processing. The middle layer contains the utilize these speeds has often been the sole domain of StrongARM processor present in the IXP1200. application specific integrated circuits (ASICs). Additionally, the authors in [4] describe an IXP1200- However, ASICs are not flexible enough to be used based network co-processor card used for traffic within network devices that must be updated often or modification within a storage area network. Utilizing the within systems that change in functionality over time. In co-processor improved performance while using a addition to operating at very high bandwidths, network lightweight messaging system. devices are being called upon to do more processing than Other researchers have used reprogrammable hardware the standard protocols. Implementations of these to perform the network processing. Moving the functions often have to change; for example, as service implementation from software to reprogrammable parameters change for quality of service implementations hardware provides system designers with a greater degree of flexibility, which allows many operations, such as 438-081 55 encryption, to occur much more rapidly. Two projects of · Provide an architecture that is no more difficult to use note are the Field Programmable Port Extender [3], which than a standard NIC and the set of applications provides pluggable processing modules within an implemented on the co-processor. advanced switch, and a reprogrammable network · Focus development on high-end network devices. interface presented in [6]. However, there are several · Design to reduce complexity and promote flexibility. other research projects that focus on development Providing a general and flexible architecture enables utilizing reprogrammable hardware [7, 8, 9]. researchers to implement functionality in ways that are not possible using other—both commercial and 1.2 The CiNIC Project academic—platforms. Platforms utilizing an architecture that provides reprogrammable hardware and a processor The Cal Poly Intelligent Network Interface Card within a single system-on-chip package (e.g., the Xilinx (CiNIC) project is part of the ongoing research of the VirtexII Pro FPGAs) approaches the CiNIC’s flexibility, Network Performance Research Laboratory (NetPRL) at but does not provide the computational resources Cal Poly. The CiNIC project focuses on improving available from a separate hardcore processor. network performance by implementing additional Additionally, since the third generation CiNIC has a functionality, beyond a standard system, within the CiNIC general architecture, several research projects beyond and by offloading network protocol processing from the network processing, such as hardware/software co-design, Host system. Two generations of the CiNIC have already embedded systems, and distributed systems, would been developed and this paper discusses the third and benefit from the architecture. current generation. Additionally, since development using intelligent NICs Each of the past CiNIC generations has provided a differs from development using other devices, work has platform for development and provided information for been done to introduce new interfaces to the Host. Work future design by showing the strengths and weaknesses of such as VIA [10] and SPINE [11] have provided new the respective architectures. The first generation CiNIC software interfaces between the Host system or user performed network processing within an Intel application and the intelligent NIC. In a similar fashion, a StrongARM processor. A complete embedded computer new hardware- and operating system-independent system was dedicated to the first generation CiNIC, interface was developed along with the third generation including: an EBSA 285 processor board, a separate hard CiNIC which provides a minimal generic interface to any drive, and a standard NIC. The second generation CiNIC intelligent NIC. Thomas details the new interface in [12] deviated from the previous generation by performing all and provides examples of how to map the interface to the network processing within Altera’s Nios softcore standard socket API. processor. System size was also reduced to a single PCI card which is inserted into the host system. Based on past results a combination of these architectures was used for 2. CiNIC Architecture the third generation CiNIC. Taking the best of the previous architectures, the third The third generation of the CiNIC (afterwards referred generation CiNIC combines the flexibility and speed of to simply as the CiNIC) departs from the previous reprogrammable hardware with the raw computational generations in that it integrates both the reprogrammable power of a hardcore processor. Each type of hardware flexibility of FPGAs and the computational power of a plays a different role in performing the network protocol hardcore processor. Combining flexibility and processing in the third generation CiNIC. For common computational power allows the CiNIC to perform the processing two FPGAs provide a platform for standard network protocol processing while adding implementing functionality either directly in hardware by functionality implemented either in hardware within the use of hardware description language (HDL) modules or FPGAs or in software running on the processor. The in software that runs on Xilinx’s MicroBlaze softcore entire system is contained on a PCI form factor card for processor. More computationally intensive or out of band use within a host system; however, there are no processing occurs on an IBM PowerPC processor. restrictions that prevent using the CiNIC as a standalone Providing multiple implementation possibilities also system if PCI functionality is not required. makes the third generation CiNIC the most flexible Two Xilinx Virtex1000 FPGAs provide the basis for CiNIC architecture to date and allows easy comparison network processing with one FPGA containing the between different implementations of the same MicroBlaze softcore processor and its peripherals, and the functionality. other FPGA containing custom HDL modules. Software Several goals guided the design of the third generation running on MicroBlaze performs the transport layer CiNIC. Those