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IXP1200 Hardware Reference Manual

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IXP1200 Hardware Reference Manual Intel® IXP1200 Network Processor Family Hardware Reference Manual December 2001 Part Number: 278303-009 Intel® IXP1200 Network Processor Family Revision History Revision Date Revision Description 8/30/99 001 Beta 1 release. 10/29/99 002 Beta 3 release. 3/2/00 003 Beta 4 release. 6/5/00 004 Version 1.0 release. 9/27/00 005 Version 1.1 release. 12/20/00 006 Version 1.2 release. 6/1/01 007 Version 1.3 SDK release. 8/10/01 008 Version 2.0 SDK release. Miscellaneous changes. 12/07/01 009 Version 2.01 SDK release. Miscellaneous changes. Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The IXP1200 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © Intel Corporation, 2001 Intel is a registered trademark of Intel Corporation or its subsidiaries in the United States and other countries *Other names and brands may be claimed as the property of others. ii Hardware Reference Manual Intel® IXP1200 Network Processor Family Contents 1 Introduction.......................................................................................................................15 1.1 About this Document ...........................................................................................15 1.2 Related Documentation.......................................................................................15 1.3 Conventions ........................................................................................................16 1.3.1 Data Terminology ...................................................................................16 1.3.2 Definitions...............................................................................................16 2 Technical Introduction ......................................................................................................17 2.1 Overview .............................................................................................................17 2.2 IXP1200 Functional Units....................................................................................18 2.3 Key Architectural Features ..................................................................................19 2.4 Some Architectural Concepts..............................................................................21 2.4.1 References .............................................................................................21 2.4.2 Signals and Synchronization ..................................................................22 2.4.3 Context Swapping and Threads .............................................................23 2.4.4 Some Examples .....................................................................................24 2.4.5 Local Data Storage and Block Transfers................................................25 2.4.6 Concurrency ...........................................................................................26 2.5 Typical Packet Data Flow....................................................................................26 2.6 External Interfaces ..............................................................................................29 2.7 Internal Architecture ............................................................................................30 2.7.1 StrongARM* Core...................................................................................31 2.7.2 Microengines ..........................................................................................33 2.7.2.1 Microengine Data Bandwidth to SRAM Unit and IX Bus Unit....37 2.7.3 SRAM Unit..............................................................................................37 2.7.4 SDRAM Unit ...........................................................................................41 2.7.4.1 Internal SDRAM Bandwidth and Internal Data Busses .............42 2.7.4.2 Chained References..................................................................42 2.7.5 PCI Unit ..................................................................................................43 2.7.6 IX Bus Unit .............................................................................................45 2.7.6.1 Ready Bus.................................................................................46 2.7.6.2 IX Data Bus Modes ...................................................................47 2.7.6.3 Scratchpad RAM .......................................................................47 2.7.6.4 Hashing Unit..............................................................................47 2.7.6.5 IXB3208 Bus Scaling Fabric......................................................48 2.8 Software Development Tools ..............................................................................49 3 StrongARM* Core.............................................................................................................51 3.1 Overview .............................................................................................................51 3.2 ARM* Architecture...............................................................................................51 3.2.1 Coprocessors .........................................................................................51 3.2.2 Memory Management Unit (MMU) .........................................................52 3.2.2.1 MMU Faults and CPU Aborts ....................................................52 3.2.2.2 Data Aborts ...............................................................................52 3.2.2.3 Interaction of the MMU, Icache, Dcache, and Write Buffer .......52 3.2.2.4 MMU Enable/Disable.................................................................53 3.2.3 Instruction Cache (Icache) .....................................................................54 Hardware Reference Manual iii Intel® IXP1200 Network Processor Family 3.2.3.1 Icache Operation....................................................................... 54 3.2.3.2 Icache Validity ........................................................................... 54 3.2.3.3 Icache Enable/Disable and Reset ............................................. 54 3.2.4 Data Caches (Dcaches) .........................................................................55 3.2.4.1 Main Data Cache....................................................................... 55 3.2.4.2 Mini Cache ................................................................................ 55 3.2.4.3 Dcaches Enable/Disable and Reset.......................................... 55 3.2.4.4 Dcache Operation ..................................................................... 55 3.2.4.5 Software Dcache Flush ............................................................. 57 3.2.5 Write Buffer ............................................................................................57 3.2.5.1 Write Buffer Operation............................................................... 58 3.2.5.2 Enabling and Disabling the Write Buffer.................................... 58 3.2.6 Read Buffer ............................................................................................58 3.2.6.1 Read Buffer Operation .............................................................. 59 3.2.7 ARM* Instruction Set and Timing ........................................................... 60 3.2.8 Exceptions.............................................................................................. 60 3.2.8.1 Exception Priorities.................................................................... 61 3.2.8.2 Exception Vector Table ............................................................. 61 3.2.8.3 Hard Reset ................................................................................ 61 3.2.8.4 Abort.......................................................................................... 62 3.2.8.5 Undefined Instruction ................................................................ 63 3.2.9 StrongARM* Core Debug Support ......................................................... 63 3.2.9.1 Instruction Breakpoint...............................................................
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