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Video and Image Processing Suite User Guide

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Video and Image Processing Suite User Guide Video and Image Processing Suite User Guide UG-VIPSUITE 2017.05.10 Last updated for Intel® Quartus® Prime Design Suite: 17.0 Subscribe Send Feedback Contents Contents 1 Video and Image Processing IP Cores..............................................................................7 1.1 Release Information................................................................................................8 1.2 Device Family Support.............................................................................................8 1.3 Latency................................................................................................................. 9 1.4 In-System Performance and Resource Guidance.......................................................10 1.5 Stall Behavior and Error Recovery........................................................................... 11 2 Avalon-ST Video.............................................................................................................16 2.1 Avalon-ST Video Configuration Types....................................................................... 18 2.2 Avalon-ST Video Packet Types.................................................................................19 2.2.1 Avalon-ST Video Control Packets................................................................. 20 2.2.2 Avalon-ST Video Video Packets................................................................... 21 2.2.3 Avalon-ST Video User Packets.....................................................................24 2.3 Avalon-ST Video Operation.....................................................................................25 2.4 Avalon-ST Video Error Cases.................................................................................. 25 3 Clocked Video................................................................................................................ 26 3.1 Video Formats...................................................................................................... 26 3.1.1 Embedded Synchronization Format: Clocked Video Output..............................26 3.1.2 Embedded Synchronization Format: Clocked Video Input ...............................27 3.1.3 Separate Synchronization Format................................................................28 3.1.4 Video Locked Signal.................................................................................. 29 3.1.5 Clocked Video and 4:2:0 Chroma Subsampling............................................. 29 4 VIP Run-Time Control.................................................................................................... 33 5 Getting Started.............................................................................................................. 36 5.1 IP Catalog and Parameter Editor............................................................................. 36 5.1.1 Specifying IP Core Parameters and Options.................................................. 37 5.2 Installing and Licensing IP Cores.............................................................................37 5.2.1 OpenCore Plus IP Evaluation.......................................................................38 6 VIP Connectivity Interfacing.......................................................................................... 39 6.1 Avalon-ST Color Space Mappings............................................................................ 39 6.1.1 Interfacing with High-Definition Multimedia Interface (HDMI)..........................40 6.1.2 Interfacing with DisplayPort........................................................................41 6.1.3 Interfacing with Serial Digital Interface (SDI)............................................... 42 6.1.4 Unsupported SDI Mappings........................................................................ 45 6.1.5 12G SDI.................................................................................................. 45 7 Clocked Video Interface IP Cores...................................................................................49 7.1 Supported Features for Clocked Video Output IP Cores...............................................49 7.2 Control Port......................................................................................................... 50 7.3 Clocked Video Input Format Detection..................................................................... 50 7.4 Interrupts............................................................................................................ 52 7.5 Clocked Video Output Video Modes..........................................................................53 7.5.1 Interrupts................................................................................................ 57 7.6 Clocked Video Output II Latency Mode.....................................................................57 7.7 Generator Lock.....................................................................................................58 Video and Image Processing Suite User Guide 2 Contents 7.8 Underflow and Overflow.........................................................................................59 7.9 Timing Constraints................................................................................................ 60 7.10 Handling Ancillary Packets....................................................................................61 7.11 Modules for Clocked Video Input II IP Core............................................................. 63 7.12 Clocked Video Input II Signals, Parameters, and Registers........................................65 7.12.1 Clocked Video Input II Interface Signals.....................................................65 7.12.2 Clocked Video Input II Parameter Settings..................................................68 7.12.3 Clocked Video Input II Control Registers.....................................................70 7.13 Clocked Video Output II Signals, Parameters, and Registers.....................................71 7.13.1 Clocked Video Output II Interface Signals...................................................71 7.13.2 Clocked Video Output II Parameter Settings................................................73 7.13.3 Clocked Video Output II Control Registers.................................................. 75 7.14 Clocked Video Input Signals, Parameters, and Registers.......................................... 77 7.14.1 Clocked Video Input Interface Signals........................................................ 77 7.14.2 Clocked Video Input Parameter Settings..................................................... 79 7.14.3 Clocked Video Input Control Registers........................................................80 7.15 Clocked Video Output Signals, Parameters, and Registers......................................... 81 7.15.1 Clocked Video Output Interface Signals...................................................... 81 7.15.2 Clocked Video Output Parameter Settings................................................... 83 7.15.3 Clocked Video Output Control Registers......................................................85 8 2D FIR II IP Core........................................................................................................... 88 8.1 2D FIR Filter Processing.........................................................................................88 8.2 2D FIR Filter Precision........................................................................................... 89 8.3 2D FIR Coefficient Specification.............................................................................. 89 8.4 2D FIR Filter Symmetry......................................................................................... 91 8.4.1 No Symmetry........................................................................................... 92 8.4.2 Horizontal Symmetry.................................................................................92 8.4.3 Vertical Symmetry.................................................................................... 92 8.4.4 Horizontal and Vertical Symmetry............................................................... 93 8.4.5 Diagonal Symmetry...................................................................................93 8.5 Result to Output Data Type Conversion.................................................................... 94 8.6 Edge-Adaptive Sharpen Mode................................................................................. 95 8.6.1 Edge Detection......................................................................................... 95 8.6.2 Filtering...................................................................................................95 8.6.3 Precision..................................................................................................96 8.7 2D FIR Filter Parameter Settings............................................................................. 96 8.8 2D FIR Filter Control Registers................................................................................98 9 Mixer II IP Core........................................................................................................... 100 9.1 Alpha Blending................................................................................................... 101 9.2 Video Mixing Parameter Settings........................................................................... 102 9.3 Video Mixing Control Registers.............................................................................
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