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JANUARY 2021 VOL. 28, NO. 1 ISSN: 1074 1879 EDITOR-IN-CHIEF: DANIEL TOMASZEWSKI

TABLE OF CONTENTS T ECHNICAL B RIEFS TECHNICAL BRIEFS ...... 1 • System and High-Volume-Manufacturing Driven More Moore Scaling Roadmap • Highlights of IEDM 2020 SYSTEM AND HIGH-VOLUME- • Highlights of the 2020 IEEE Photovoltaic Specialists Conference MANUFACTURING DRIVEN MORE • Review of the 2020 IRPS

UPCOMING TECHNICAL MEETINGS ...... 31 MOORE SCALING ROADMAP • 5th IEEE Electron Devices Technology and MUSTAFA BADAROGLU1 AND PAOLO A. GARGINI2 Manufacturing (EDTM) Conference 1 • 2021 IEEE Photovoltaics Specialist Conference (PVSC) IEEE IRDS MORE MOORE CHAIRMAN, QUALCOMM, • 2021 IEEE International Memory Workshop (IMW) 2IEEE LIFE FELLOW, I-JSAP FELLOW, CHAIRMAN IRDS • 2021 IEEE Latin American Electron Devices Conference (LAEDC) [email protected], [email protected]

SOCIETY NEWS ...... 35 • Board of Governors Meeting • Message from EDS President • Message from the Chair of the EDS Optoelectronic Devices Committee 1. Introduction • Message from Editor-in-Chief Scaling device features by approximately 30% in each new tech- • Congratulations to Dr. Robert W. Dutton-2020 nology generation supported Moore’s Law doubling the number of IEEE EDS Celebrated Member • EDS Members Named Recipients of 2021 IEEE transistors every 2-years for decades while also improving system Technical Field Awards performance by concurrently increasing transistor drive current • In Memory of James D. Meindl • Announcement of the 2020 EDS Undergraduate and reducing operating voltage. This combination allowed intro- Student Scholarship Winners duction of new functions in innovative System-On-Chip (SoC) • Announcement of the 2020 EDS Masters Student products with better performance and lower cost. The progress Fellowship Winners • Announcement of the 2020 EDS PhD Student of technology scaling has been measured by monitoring PPAC Fellowship Winners (Performance-Power-Area-Cost) improvements, typically hap- • 2020 EDS Chapter of the Year Award Winners • Call for Nominations—EDS Student Fellowships pening with any new technology introduction with a cadence of for 2021 2–3 years. However, pure geometric scaling does not provide any YOUNG PROFESSIONALS ...... 46 longer the necessary PPAC improvements at the system level due • India’s Rise in Nanoelectronics Research to several reasons: • IEEE Young Professionals Germany at Robert Bosch Semiconductor Headquarters 1) limits of practical power dissipation were reached around the middle of the previous decade and this constraint im- CHAPTER NEWS ...... 51 • DIPED-2020 Seminar/Workshop Dedicated to the posed a maximum useable frequency of 5–6 GHz, Memory of Prof. Nikolai Voitovich 2) ideal geometric scaling introduces increasing levels of para- • TEC Costa Rica Recipient of the 2020 IEEE EDS Student Branch Chapter of the Year Award sitics that adversely reduce performance, • EDS Cares: Face Mask Loop Extender and Face Shield 3) cost of scaling is increasing faster than in the past due to for SMK 18 Shah Alam Muslimah Student and lithographic limitations demanding multiple exposure per Teacher Volunteers layer and therefore making final products very costly, REGIONAL NEWS ...... 55

EDS MEETINGS CALENDAR ...... 69 (continued on page 3) CALL FOR PAPERS—SPECIAL ISSUE OF THE IEEE TRANSACTIONS ON ELECTRON DEVICES ...... 71

NEWSLETTER DISTRIBUTION CHANGES ...... 72 YOUR COMMENTS SOLICITED Your comments are most welcome. Please write directly to the Editor-in-Chief of the Newsletter at [email protected]

28neds01_Final_DigitalOnly.indd 1 1/20/21 11:13 AM ELECTRON DEVICES NEWSLETTER SOCIETY EDITORIAL STAFF

Editor-In-Chief President Vice President of Membership Daniel Tomaszewski Ravi Todi and Services Lukasiewicz Research Network—Institute of Western Digital Technologies Patrick Fay Microelectronics and Photonics Email: [email protected] University of Notre Dame Email: [email protected] E-mail: [email protected] Treasurer Bin Zhao Vice President of Publications REGIONS 1–6, 7 & 9 United Kingdom, Middle Freescale Semiconductor and Products Eastern, Northeastern & East & Africa E-mail: [email protected] Joachim Burghartz Southeastern USA Stewart Smith Institute for Microelectronics (Regions 1, 2 & 3) Scottish Microelectronics Centre Secretary Stuttgart Rinus Lee E-mail: [email protected] M.K. Radhakrishnan E-mail: [email protected] NanoRel GlobalFoundries E-mail: [email protected] Vice President of Regions/ E-mail: [email protected] Western Europe Chapters Mike Schwarz Jr. Past President Murty Polavarapu Central USA & Canada Technische Hochschule Fernando Guarin Space Electronics Solutions (Regions 4 & 7) Mittelhessen University of GlobalFoundries E-mail: [email protected] Michael Adachi Applied Sciences E-mail: [email protected] Simon Fraser University E-mail: mike.schwarz1980@ Vice President of Strategic E-mail: [email protected] googlemail.com Sr. Past President Directions Samar Saha Paul Berger Prospicient Devices The Ohio State University Southwestern & Western USA REGION 10 E-mail: [email protected] E-mail: [email protected] (Regions 5 & 6) Australia, New Zealand & Muhammad Mustafa Hussain South East Asia Vice President of Education Vice President of Technical University of California—Berkeley Sharma Rao Balakrishnan Navakanta Bhat Committees E-mail: MuhammadMustafa. Universiti Sains Islam Malaysia Indian Institute of Science John Dallessase [email protected] E-mail: [email protected] Email: [email protected] University of Illinois at Urbana- Champaign Vice President of Meetings Email: [email protected] Latin America (Region 9) North East and East Asia Kazunari Ishimaru Edmundo A. Guiterrez-D. Ming Liu Kioxia Corporation INAOE Institute of Microelectronics Email: [email protected] E-mail: [email protected] E-mail: [email protected]

REGION 8 South Asia Eastern Europe Soumya Pandit Kateryna Arkhypova University of Calcutta IRE NASU E-mail: [email protected] E-mail: [email protected] IEEE prohibits discrimination, harassment, and bullying. For more information, visit http://www.ieee.org/web/aboutus/whatis/policies/p9-26.html. Scandinavia & Central Europe Marcin Janicki Lodz University of Technology E-mail: [email protected]

EDS Board of Governors (BoG) CONTRIBUTIONS WELCOME Elected Members-at-Large Elected for a three-year term (maximum two terms) with ‘full’ voting privileges Readers are encouraged to submit news items concerning the Society and its members. Please send your ideas/articles directly to either Editor-in- 2021 TERM 2022 TERM 2023 TERM Chief or the Regional Editor for your region. The email addresses of all Paul Berger (1) Constantin Bulucea (1) Roger Booth (2) Regional Editors are listed on this page. Email is the preferred form of Navakanta Bhat (2) Daniel Camacho (1) Xiojun Guo (1) submission. Merlyne De Souza (1) John Dallesasse (1) Edmundo A. Gutierrez-D. (2) NEWSLETTER DEADLINES Kazumari Ishimaru (1) Mario Lanza (1) Francesca Iacopi (1) William (Bill) Nehrer (1) Geok Ing Ng (1) Benjamin Iniguez (2) ISSUE DUE DATE Murty Polavarapu (2) Claudio Paoloni (1) P. Susthitha Menon (1) Camilo Velez Cuervo (1) Hitoshi Wakabayashi (1) Manoj Saxena (2) Sumant Sood (2) October July 1st January October 1st April January 1st July April 1st

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IEEE Electron Devices Society Newsletter (ISSN 1074 1879) is published quarterly by the Electron Devices Society of the Institute of Electrical and Electronics Engineers, Inc. Headquarters: 3 Park Avenue, 17th Floor, New York, NY 10016–5997. Printed in the U.S.A. One dollar ($1.00) per member per year is included in the Society fee for each member of the Electron Devices Society. Periodicals postage paid at New York, NY and at additional mailing offices. Postmaster: Send address changes to IEEE Electron Devices Society Newsletter, IEEE, 445 Hoes Lane, Piscataway, NJ 08854.

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2 IEEE Electron Devices Society Newsletter ❍ January 2021

28neds01_Final_DigitalOnly.indd 2 1/20/21 11:13 AM SYSTEM AND HIGH-VOLUME-MANUFACTURING DRIVEN MORE MOORE SCALING ROADMAP

(continued from page 1)

4) there is an increasing imbal- ter is to provide physical, electrical, 10 years, for multiple cloud applica- ance and disconnect between and reliability requirements for a tions. The first step in the roadmap the performance of devices at unified logic and memory technol- process is to identify the ground rules the die level and the perfor- ogy platform to sustain power, per- and their inherent limits set by the mance requirements of the formance, area, cost (PPAC) “scaling unit process modules, devices, and overall system (e.g. memo- guidelines” for mobile and cloud ap- the impact of any parasitics on perfor- ry bandwidth bottleneck) that plications over a time horizon of 15 mance. The second step is to describe creates a significant burden years for Mainstream/High-Volume the standard cell scaling parameters to further enhance system in- Manufacturing (HVM) [1]. Such tech- and how to further tighten key design tegration and performance. nology platform identifies the main rules by means of Design Technology Therefore, for all the above technology drivers and provides the Co-Optimization (DTCO). The third reasons there is a need to con- enabling tools for the following ap- step is then the identification of de- currently consider overall sys- plication (Fig. 1): vice architecture and interconnects tem and economics trade-offs • Mobile—5G/6G, hetero integra- technology drivers to satisfy System- and introduce items that can tion, edge computing, graphics, On-Chip requirements. Finally, op- provide better system building extreme reality (VR/AR) timization of all the above elements blocks at the die level other • Machine learning at edge and brings performance and careful en- than ideal geometrical scaling. cloud ergy management together to col- The ITRS established in 1998 was • High-performance energy-effi- lectively enable cost effective system mainly aimed at transistor density cient graphics/sensing scaling. Since transistor technology and performance improvements by • Data/micro servers—cache/buffer alone is no longer sufficient to sat- means of scaling but in this decade memory and accelerator integra- isfy the requirements for enhanced the roadmap projections have been tion, IO, high-performance inter- memory bandwidth, IO, and outside re-focused on system constraints; this posers connectivity demanded by system consideration led to the restructured • Ultra-low power computing ex- driven requirements, it is necessary International Roadmap for Devices ploiting non-volatility. to introduce new 2.5D/3D integration andSystems (IRDS). This collection More Moore (MM) roadmap schemes. These integration technolo- of documents provides the roadmap guidelines identify technology en- gies enable the effective adoption of for logic devices, on-chip intercon- ablement items for improving the the needed memory with sufficient nect, and memory devices driven by system performance, power, and bandwidth, increased capacity, and feasible manufacturability routes and area in a timely manner; meeting a latency parameters required for the system integration requirements. mobile product cadence of one year, various applications listed above. maybe even six months, while pro- As the final step of this optimization 2. Market Drivers of More Moore viding a scalable product platform for process the various available enable- Scaling and Roadmap Process the servers, which must be surviving ment items are carefully analyzed and System considerations and cost optimization requirements have driven the need for a unified technology platform where high-performance digital logic needs to enable server applications are considered and also provide support for low power needs to enable mobile computing for the edge applications. Both requirements must be kept into account with equivalent relevance to allow the electronics industry to continue growing at historical (or better) rates. Therefore the mission of the IRDS More Moore (MM) IFT chap- Fig. 1. Two pillars of More Moore application drivers.

January 2021 ❍ IEEE Electron Devices Society Newsletter 3

28neds01_Final_DigitalOnly.indd 3 1/20/21 11:13 AM the essential items are down-selected the rising process complexity asso- 193i tool. Another careful consider- to meet product delivery timeline ciated with the multiple patterning it ation on how aggressively ground while limiting process complexity to is important to carefully allocate the rules are to be scaled is due to con- the most relevant innovative module lithography technology to be used siderations about the increased con- processes to be added to the device with each layer. The feature size that tributions of parasitics to the total technology platform in High-Volume- can be produced by any lithography performance. In summary, overlay Manufacturing (HVM). tool is largely determined by the and unnecessary scaling may bring exposure wavelength. This means diminishing returns on both transis- 3. Ground Rules that design ground rules are deter- tor performance and also unneces- Determination of ground rules is mined by keeping into consideration sarily increasing power dissipation. a critical step in defining both the the capability limits of the avail- This becomes the case even though unit process modules and a real- able lithography tool. For instance area scaling may indeed reduce in- istic economy of scaling [2]. It is of 76–80 nm metal pitch can be ob- terconnects parasitics due to a re- paramount importance to select a tained by using 193i immersion li- duction of wirelengths. All these set of design ground rules that are thography tools (193 nm exposure trade-offs must be kept into careful as aggressive as possible and yet wavelength) with double or even qua- consideration in the complex selec- consistent with high yields in the druple exposures. Similarly, 28–30 nm tion of ground rules (Fig. 2). 2D scal- High-Volume-Manufacturing (HVM) metal pitch can be presently ob- ing is expected to eventually reach process to assure economic prod- tained by using EUV tools (13.5 nm) practical limits around the year 2030 uct viability. Lithography technology with a single exposure, but 18 nm when full 3D stacking technology is remains the key process step en- pitch or lower may require double expected to become mainstream. abling reduction of device features. EUV exposure. These examples However, the limits of single expo- show the trade-off between expo- Correcting Nonsense sure lithography were reached more sure tool selection and design rules. Node Naming than a decade ago and additional Due to the much lower exposure The ITRS had defined technology process steps had to be introduced wavelength of EUV it is possible to nodes as the half-pitch of the small- to maintain scaling of device fea- achieve much smaller ground rules est metal layer in any IC in the 90s. tures by around 30% per technology for the EUV layers with much bet- However, in the past 10 years several generation. The most viable solu- ter tolerance margins as compared companies have redefined their own tion to achieve the required scaling to double or quadruple exposure technology nodes by using much goal through the years has resulted using tools exposing with 193nm smaller numbers than the official exposing multiple times any layers wavelength. However, the selection definition. This method of naming that exceeded the lithography capa- of the lithography tool to be used nodes has by now lost any credibility bilities. In few words for illustrative by layer is not so obvious because since there is no longer any relation purposes let’s consider exposing careful cost considerations must be between the node name and any twice a set of lines and spaces; the done since any exposure done by of the dimensions on the actual ICs first time the set of lines and spaces the EUV tool is as much as 3 times that are being produced nowadays. is exposed in the resist and then the more expensive than the one of a For instance, several companies are same pattern is re-exposed talking about 7 nm tech- a second time but offset by nology node while in real- half pitch. The outcome is ity it should be named as a set of interdigitized lines 18 nm technology node spaced at half the distance corresponding to half of of the original ones. Under the 36 nm minimal metal practical conditions more pitch in the actual ICs. complicated sequences It is important to note and mask combinations are that there is no correlation required. This represents between the naming con- a viable engineering ap- vention (e.g. 7 nm, 5 nm proach although it comes technology) from different with the penalty of dou- foundries and integrated bling or even quadrupling device manufacturers the lithography cost for any (IDMs) and the technology layer produced with this capabilities in line with the process method. Due to Fig. 2. Evolution of ground rules. PPAC requirements.

4 IEEE Electron Devices Society Newsletter ❍ January 2021

28neds01_Final_DigitalOnly.indd 4 1/20/21 11:13 AM To further clarify this point the IRDS chose to name the by explicitly putting the key parameters used in defining the ground rules in the technology naming convention, these are: GxxMxxTx where Gxx represents the contacted gate pitch, Mxx represents the tightest metal pitch in nm and Tx represents the number of stacked tiers making up a 3D integrated transistor circuits. This notation illustrates the technology pitch scaling capability as well as 3D stacking capability Fi g. 3. DTCO-enhanced standard cell scaling evolution. [3]. On top of pitch scaling there are other elements of relevance such as cell height, Fin depopulation, DTCO cell height with substantial area sav- tinuous electrostatics, drive current constructs, 3D integration, etc. that ings. Recently further cell height re- and cell architecture improvements define the target area scaling (gates/ duction has been demonstrated by such as increasing the Fin height and mm2), which will be explained in the placing contact-over-active devices reducing the width of Fin to keep next paragraph. [4]. It is expected that in 2028 PMOS electrostatics under control [5][6]. For sake of completeness the ar- and NMOS devices could be stacked In order to continue increasing per- tificially defined industry technology on top of each other allowing a fur- formance and density it is necessary nodes are indicated as a reference in ther cell area reduction. This trend to increase the transistor output cur- the roadmap. in standard cell height and width rent and this requires improving the scaling is illustrated in Fig. 3 with electrostatic control of the channel 4. Standard Cell Architecture the density scaling of standard cell region while also reducing transistor As mentioned earlier design rules shown in Fig. 4. footprint to increase layout density. cannot be aggressively scaled down To accomplish these tasks, it is neces- like in the past and therefore it is 5. Device Structures sary to make a transition from FinFET necessary to complement their role In the next 15 years it is forecasted to Gate All Around (GAA) structures in reducing the area of the basic cell that three phases of scaling will occur such as circular tubes or lateral with novel layout techniques that al- (Fig. 5): 1) Extending improvements nanosheets; the GAA transition is low to achieve the desired area re- of FinFET, 2) Transition to gate-all- expected to gradually occur during duction goal as well as producing around (GAA) devices, 3) Sequen- the 2022–2025 period. Such transition more manufacturable design rules. tial integration (3DVLSI) of stacked will require the introduction of new This methodology is called Design devices. FinFET has continued to process modules like channel release Technology Co-Optimization (DTCO). remain the key transistor architec- for the build-up of stacked channels, The basic approach of DTCO consists ture since 2011 and it will continue to substantial improvements in inner in reducing the standard cell height remain the transistor architecture of spacer to reduce the effect of para- and width by combining many de- choice until 2025 or so thanks to con- sitic capacitance, increased bottom sign elements enabled channel isolation to reduce by the technology. For parasitics, and enhanced instance, reducing the replacement-metal-gate number of active devices modules to provide mul- in the cell and combining tiple threshold voltages as a limited scaling of the the spacing between the width of active devices as nanosheets is reduced. well as carefully applying Lateral GAA structure a limited scaling of many would eventually evolve secondary rules such as into full 3D forms by in- tip-to-tip, tip extension, corporating much thinner PMOS-NMOS separa- channel structures when tion, and minimum metal finally stacking NMOS area rules produce a over PMOS architecture drastic reduction of the Fig. 4. Standard cell density scaling. will be adopted.

January 2021 ❍ IEEE Electron Devices Society Newsletter 5

28neds01_Final_DigitalOnly.indd 5 1/20/21 11:13 AM Use of Si channel material places a to avoid surface scattering. The adop- surface phenomena. The adoption of lower limit to reducing channel thick- tion of 2D channel materials will bring 2D materials will enable much thinner ness as required when scaling the gate an opportunity for further reduction channels because it will eliminate the length to 10–12 nm because of a con- of gate lengths since the conduction effect of dangling bonds at the inter- flicting need for thicker Si nanosheets mechanism is no longer affected by face between the conducting channel and the surrounding insulation [7]. Further reduction of capacitance is possible because of gate length reduction and lower dielectric constant of channel materials. However, 300mm manufacturability, 2D material synthe- sis, and contact engineering will still remain sources of critical challenges to be solved before adopting 2D transistor structures as the foundation of device platform beyond 2028. Key dimensions for the logic device scaling are shown in Fig. 6. Sys- Fig . 5. Evolution of device structures. tem-on-chip built with GAA devices

Fig. 6. Key dimensions for the logic technology scaling.

6 IEEE Electron Devices Society Newsletter ❍ January 2021

28neds01_Final_DigitalOnly.indd 6 1/20/21 11:13 AM are expected to utilize several GAA view it is more advantageous than is expected that this technology could device types. This implies that a typi- low-capacity embedded memories evolve onto the fine-grain and regular cal SoC designer will need to select and it also offers a better performing fabric suitable for logic-on-logic ap- upfront the type of devices needed bus/IO structure by taking advantage plications (potentially equalizing the based on their threshold voltage and of the better interconnect capability size of different-tier dies) if regular- nanosheet widths prior to fabrication. associated with the interposer. In the fabric data-flow micro-architectures Below are examples of some of the future it is expected that the interpos- will prove successful in the industry. anticipated device choices in 2025: er technology will allow to place vari- The technology of sequential in- 1) High-density SRAM will need ous types of chipsets, (i.e., not limited tegration of multiple tiers of devices transistors with ultra-low leak- to memory), in the same package and relies on the fabricating of subse- age of about 7 nm width, its fabric would also include voltage quent tier using a thermal budget 2) High-density designs will need regulators, decoupling capacitances, lower than the one used to fabricate transistors with moderate buffers, IO, ESD, etc. There are vari- any of the underlying tiers. Inter- leakage of about 15 nm width, ous implementation routes to enable tier via pitch can be of the order of 3) High-performance design will optimal 3D stacked components. As 50–300 nm in this technology, en- tolerate high-leakage transis- the combination of 3D stacked com- abling 100 M vias/mm2 [10]. It is tors of about 25 nm width. ponents will keep on increasing and important to point out that using as more interconnect routes can be this integration scheme it becomes 6. 2.5D/3D Integration placed on the interposer it will be possible to independently optimize Realization of 2D device technolo- possible to create larger and larger specific devices in each tier (e.g., gies will enable energy-efficient per- high performance systems in a single threshold voltage, channel mate- formance computing, but this will package [9]. rial, raised source/drain, strain, etc). require an architectural adjustment Die-to-wafer stacking technolo- Although this technology has many to achieve optimal results. Under gies will continue to employ μBump advantages several challenges still these conditions it will be necessary stacking and/or hybrid/dielectric lay ahead. Selection of layer-by-layer to move the data from the computing bonding. Either of those technologies thermal budgets, integration meth- logic to the high-capacity memories requires Thru-Silicon-Via (TSV) in one odology of high-aspect-ratio vias, se- with high-bandwidth connections. or more of the tiers to connect the lection of cell topology and allocation 2.5D systems have already demon- individual dice stacked onto top of by layer of interconnection partition- strated to be very efficient in the gen- the interposer. Integration drivers for ing between fine, median and looser erations of high-bandwidth memory this technology are high-bandwidth pitch in each tier (e.g. connections (HBM) chipsets where stacked DRAM and high-density memories stacked between PMOS-tier and NMOS-tier, memory cubes (e.g. 128 Gbit/cube) on logic die. Furthermore, hetero- between standard cells, between have been put side-by-side in a pack- geneous stacking will be allowing standard cell and bitcell) remains a age with the computing logic die integration of new functions and sub- formidable planning challenge. In assembled on the same interposer. stantial reduction of form factor. How- order to extract the maximum value This technology has demonstrated ever, design/architecture partitioning, from this multi-tier architecture it is 64 GB memory with a bandwidth of thermal management; and IO and advisable to select an approach fa- 2 TB at 512 GB/sec in a single pack- power distribution allocation across voring regularity organized layout; age [7]. In order to keep increasing the design/system network will still this arrangement is ideal to optimize HBM performance and increasing present very difficult challenges. Typi- any highly parallel computation and the total amount of memory in the cal pitch of μBumps on these tech- also to accommodate for the fastest same package, there will be a need nologies is presently around 40 μm, memory access while also supporting to implement more complex 3D ar- enabling 625 vias/mm2, while Cu pad a very large memory capacity. As time chitectures. It is expected that in the (in hybrid bonding) pitch is around goes by this integrated architecturally next 2–5 years, work-level memory 10 μm, enabling 10,000 vias/mm2. driven die layout will make data-cen- (e.g. 3D SRAM and/or DRAM on top Wafer-to-wafer stacking is used tric computing highly successful. It is of logic) will be stacked together on in applications where there are no also possible that this approach may logic to provide a low-latency and issues related to form factor mis- eventually evolve into more general- large bandwidth communication ca- match. This type of stacking was suc- purpose computing [11]. An example pability between memory and logic. cessfully used in image sensors and of 3D micro-architecture employing Most of 3D stacking technology HBM (stacked DRAM) applications. a highly regular layout is shown in development focuses on bringing In this case μBump pitch is around Fig. 7; here the sequencer controlling high-capacity memory closer to logic 40 μm while Cu pad (in hybrid bond- the flow of data across tiers con- because from a performance point of ing) is around 1–2 μm. Eventually it trols computation performance.

January 2021 ❍ IEEE Electron Devices Society Newsletter 7

28neds01_Final_DigitalOnly.indd 7 1/20/21 11:13 AM Fig. 7. 3D VLSI enablement with regular fabric.

Fig. 8. Critical defect dimension, process complexity, and number of defects/wafer analysis for a projected 3nm FinFET technology to get the initial ramp yield of 80%.

7. Yield Considerations of lines and spaces can be achieved control for an 80 mm2 mobile die In order to be continuing More Moore by a single exposure as opposed used as a benchmark for this analy- scaling on multiple layers will neces- to the present situation where 3 sis (Fig. 8) it is necessary that the re- sitate an increased number of met- or even 4 exposures per layer are quired D0 level be reduced by 2.2x in allization layers, therefore the mask required. However, it is expected 2034 (over 5 logic node transitions) count is bound to increase too, bar- that the mask count will resume to Besides the expected addition of ring any new breakthrough in metal- escalate after 2031 driven by an in- possible defects due to increased lization techniques and lithography. creased need for metallization layers process complexity there is also The expected transition of multiple required by full 3D integration. As the risk of increased defectivity due challenging mask layers from 193i the number of layers keeps on in- to brand new modules causing lithography to EUV, and from EUV creasing so will process complexity altogether severe challenges to (NA = 0.33) to high-NA EUV (NA and therefore the defectivity (D0) re- yields. These are some of the sourc- > 0.5) will potentially save several quirements will accordingly become es of possible defects: smaller masks since the desired resolution more severe. To keep the yield under defects that were no relevant in

8 IEEE Electron Devices Society Newsletter ❍ January 2021

28neds01_Final_DigitalOnly.indd 8 1/20/21 11:14 AM the past will become more impor- capable of concurrently resolving contributions to the IEEE IRDS More tant as device features keep getting performance, power, and thermal is- Moore roadmap. smaller, the number of high-aspect sues. For further scalability of power ratio structures such as taller fins and energy it is estimated that adop- References and GAA architecture will require tion of 2D materials for the channel [1] IEEE IRDS 2020 edition. Online: more and newer conformal depo- is a good approach for concurrently https://irds.ieee.org/editions/2020 sition processes, high-aspect ratio reducing both channel length and [2] M. van den Brink, “Continued scal- contacts will challenge contact and capacitance. However, GAA manu- ing in semiconductor manufacturing en- via technologies and control of lat- facturability and contact engineering abled by advances in lithography,” IEDM, eral etch technology and sophisti- remain critical challenges to adopt- December 2019. cated sidewall/bottom cleans will ing 2D material channel device as a [3] S.K. Moore, “A better way to mea- be required. In few words there is a device platform beyond 2028. sure progress in semiconductors,” “The concern that the process complex- Innovative embedded memories node is nonsense,” IEEE Spectrum, Au- ity and the number of materials will technologies are significantly gain- gust 2020. increase even though most of the ising momentum via concrete plans of [4] C. Auth et al., “A 10nm high per- sues are not known at present. Even- adopting MRAM and stacked SRAM/ formance and low-power CMOS tech- tually beyond 2030 lithography will DRAM solutions since higher band- nology featuring 3rd-generation finFET no longer be able to resolve some width and capacity requirements are transistors, self-aligned quad patterning, dimensions less than 8 nm or so and becoming a major bottleneck that contact over active gate and Cobalt local overlay requirements of fraction of a are actually becoming more relevant interconnects,” IEDM, December 2017. nanometer will reach a natural limi- than solving latency limitations. Nev- [5] G. Yeap et al., “5nm CMOS produc- tation. It is suggested that more re- ertheless bandwidth, endurance, and tion technology platform featuring full- liance on self-organizing structures, latency improvements are needed to fledged EUV, and high mobility channel self-alignment and self-conformal adopt NAND-FLASH as an AI memo- FinFETs with densest 0.021 um2 SRAM deposition will be viable by then, ry solution. Multi-level cell schemes cells for mobile SoC and high-perfor- but these new process steps will seem to be the preferred route to mance computing applications,” IEDM, also further increase process and scale up the number of bits per chip December 2019. material complexity. in these memories. [6] M. Badaroglu, “Interconnect-aware 2.5D/3D-stacking technologies are technology and design co-optimization 8. Summary of Predictions motivated by the benefits of stacking for the 5-nm technology and beyond,” from 2020 Edition of IRDS More memory-on-logic in large chips such Journal of Low Power Electronics (JOL- Moore Roadmap as data servers, AI, and network prod- PE), Vol. 14, No. 2, June 2018. Until approximately the year 2010 ucts as multiple vias of communica- [7] Q Smets, et al., “Ultra-scaled personal computers and laptops tions between chips are increased MOCVD MoS2 MOSFETs with 42nm con- drove technology requirements. In (e.g., arrays of bumps). by offering an tact pitch and 250uA/um drain current,” the past decade mobile devices, avenue for products bundling more IEDM, December 2019. cloud data centers, AI algorithms features and reducing time-to-market. [8] M. Badaroglu, “3D IC opportunities and high-performance comput- 2.5D integration is expected to con- for high-performance computing”, Semi ing applications have been driving tinue evolving towards transforming 3D & Systems summit, January 2020. More Moore scaling requirements. the present passive interposers into [9] A.A. Elsherbini et al., “Heteroge- The conditions imposed on transis- active interposers. This approach will neous integration using omni-director performance due to power were enable multi-sourcing and interoper- tional interconnect packaging,” IEDM, limitations and those were partially ability of various chiplets in the pack- December 2019. compensated by the industry with age system whereby the interposer [10] W. Rachmady et al., “300mm Design-Technology-Co-Optimizaion will be providing active and passive heterogeneous 3D integration of record (DTCO). In the future, Lateral-GAA functions such as voltage regulation, performance layer transfer germanium offers reduced leakage and im- decoupling capacitances, buffers, IO, PMOS with silicon NMOS for low power proved performance at lower op- ESD, etc. high performance logic applications”, erating voltages and it is therefore For more information—visit https:// IEDM, December 2019. expected to be a viable path for en- irds.ieee.org/editions/2020. [11] E. P. Benedictis, M. Badaroglu, A. hanced PPAC values starting as early Chen, T.M. Conte, and P. Gargini, “Sus- as 2022. For the successful deploy- 9. Acknowledgments taining Moore’s law for 3D chips,” IEEE ment of GAA any possible capaci- The authors acknowledge the IEEE Computer, Vol. 50, No. 8, pp. 69–73, tance reduction is a key parameter IRDS members for their valuable August 2017.

January 2021 ❍ IEEE Electron Devices Society Newsletter 9

28neds01_Final_DigitalOnly.indd 9 1/20/21 11:14 AM A REVIEW OF THE 2020 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) DINA TRIYOSO, IEDM 2020 PUBLICITY CHAIR MENG-FAN (MARVIN) CHANG, IEDM 2020 PUBLICITY VICE CHAIR EDITED BY DANIEL TOMASZEWSKI, EDS NEWSLETTER EDITOR-IN-CHIEF, BASED ON THE MATERIAL PREPARED BY THE IEDM PUBLICITY TEAM

The annual IEDM conference (www ratory restrictions and all of the other would be ahead. A theme of IEDM .ieee-iedm.org), sponsored by the challenges imposed on us by the 2020, “Innovative Devices for a Bet- IEEE Electron Devices Society, is pandemic, our community has perse- ter Future” reflected the fact that at a the world’s largest, most influential vered and driven the state-of-the-art time of great global uncertainty, elec- forum for the unveiling of break- of electronics technology forward tronics technology was being used throughs in transistors and related yet again.” much more broadly than ever before micro/nanoelectronics devices. The H owever, the virtual format pro- to address the world’s most pressing 66th annual IEDM was held virtually vided a few challenges. “Although challenges. Prof. Datta introduced the December 12–18, 2020 and offered the virtual experience didn’t give us Executive Committee, the Technical a mix of live-streamed events and the ability to see our colleagues in Subcommittees and IEDM planners. on-demand pre-recorded presenta- person, it did provide unique oppor- Thanks to their efforts, the Confer- tions, with a schedule of live Q&A tunities which we tried to maximize,” ence technical program remained at sessions. The expanded schedule said Meng-Fan (Marvin) Chang, IEDM a very good level, with a high num- was intended to give global attend- 2020 Publicity Vice Chair, IEEE Fellow, ber of submissions (580) and a good ees enough time to review the more Distinguished Professor of Electrical acceptance rate (231), in spite of the than 220 papers in the IEDM techni- Engineering at National Tsing Hua pandemic. Prof. Datta introduced the cal program, plus the tutorials and University and Director of Corporate convenient internet platform used to short courses, and to participate in Research at TSMC. “For example, if provide access to both live-streamed the live-streamed events, such as the IEDM were a physical event this year, and pre-recorded IEDM sessions, to plenary presentations, panel discus- nine technical sessions would run in the virtual Exhibit Hall, and to an on- sion and career session. parallel. An attendee likely would find line networking area. He underlined “This year’s format may be differ- it difficult to attend all talks of inter- that on-demand materials would be ent, but what hasn’t changed at all est. But with recorded presentations available for the registered attendees is that IEDM once again offered an available on-demand a week ahead of until the end of January 2021. Next, outstanding technical program that time, that roadblock was eliminated.” he briefly highlighted the Conference showcased important breakthroughs The Conference was initiated by an program. Finally, on behalf of Prof. in key semiconductor and related opening presentation by Prof. Suman Tibor Grasser, the Technical Program technologies, which are essential Datta, the IEDM 2020 General Chair. Chair, and Prof. Barbara De Salvo, the for the progress of modern society,” Prof. Datta underlined that the 66th Technical Program Vice Chair, Prof. said Dina Triyoso, IEDM 2020 Pub- Edition of IEDM was held in a difficult Suman Datta said “Thank you” to all licity Chair and Technologist at TEL time of pandemic, which had affected the presenters and organizers of the Technology Center, America, LLC. all the societies worldwide. However, 66th IEDM and wished them a fruitful “We’re pleased that, despite the labo- he expressed a hope that better days Conference.

10 IEEE Electron Devices Society Newsletter ❍ January 2021

28neds01_Final_DigitalOnly.indd 10 1/20/21 11:14 AM The Conference participants were IEDM 2020 also included a Career- This course covered a range of able to watch three Plenary Presenta- Focused Session featuring industry relevant topics, including next tions, which were live-streamed as and scientific leaders talking about generation nanosheet transis- 45-minute talks followed by 15-min- their personal experiences in the con- tors; packaging technologies ute Q&A sessions: text of career growth: Prof. Tsu-Jae for 3D integration; RF front-end • Monday, Dec. 14: Sri Samavedam, King Liu, IEEE Fellow, Professor & modules; power delivery/regula- Senior VP CMOS Technologies, Dean at University of California-Berke- tion; and monolithic and chiplet imec—“Future Logic Scaling: ley, member of the Board of Directors integration. Atomic Channels to Deconstruct- of Intel Corp, and Dr. Heike Riel, IBM • “Memory-Bound Computing,” or- ed Chips” Fellow, Head of Science & Technology, ganized by Ian Young (Intel). The • Tuesday, Dec. 15: Naga Lead of IBM Research Quantum Eu- topics included the role of per- Chandrasekaran, Senior VP of rope. The session was moderated by sistent memory for high-perfor- Process R&D and Operations, Prof. Suman Datta, University of Notre mance computing; HBM DRAM Micron Technology—“Memory Dame. The session was live-streamed and beyond; memory for secure Technology: Innovations Needed Friday, Dec. 18. computing; PUFs for hardware se- for Continued Technology Six Tutorials, listed below, were curity; alternate SRAM technolo- Scaling and Enabling Advanced held during the time-frame of IEDM as gies; analog memory needs for AI; Computing Systems” on-demand pre-recorded talks avail- and one-shot learning with mem- • Wednesday, Dec. 16: Sungwoo able beginning Dec. 5, whereas the ory-augmented neural networks. Hwang, President, Samsung Ad- corresponding live summary/Q&A ses- Six Focus Sessions, listed be- vanced Institute of Technology— sions were held on Saturday, Dec. 12. low, were held at IEDM 2020 on key “Symbiosis of Semiconductors, • “Quantum Computing Technol- emerging technologies. These talks AI and Quantum Computing” ogies” by Dr. Maud Vinet (CEA covered a range of topics addressing In partnership with the journals Na- Leti) the gaps, challenges, and opportuni- ture and Nature Electronics, IEDM • “Advanced Packaging Technolo- ties for new approaches and technol- 2020 offered a unique Panel Discus- gies for Heterogeneous Integra- ogies, including system-level issues sion entitled “What Can Electronics tion” by Dr. Ravi Mahajan & Dr. and requirements; benchmarks of Do to Solve the Grand Societal Chal- Sairam Agraharam (Intel) current technologies; and R&D direc- lenges Going Forward?”, moderated • “Memory-Centric Computing tions for the new materials, devices, by Ed Gerstner, Director of Journal Systems” by Prof. Onur Mutlu circuits, and modeling/manufactur- Policy & Strategy for Springer Na- (ETH Zurich) ing approaches needed. ture. The Panelists were: Jacqueline • “Imaging Devices and Systems • Device Technologies for Cryogen- Mc Glade, Professor Natural Prosper- for Future Society” by Dr. Yusuke ic Electronics—Cryogenic elec- ity and Sustainable Oceans, Institute Oike (Sony Semiconductor Solu- tronics refers to the operation for Global Prosperity and Engineer- tions) of electronic devices at temper- ing, University College London, and • “Innovative Technology Elements atures from −150 °C (−238 °F) to James Plummer, Professor and for- to Enable CMOS Scaling in 3nm absolute zero (−273 °C or −460 °F). mer Dean of Engineering, Stanford and Beyond—Device Architec- The theoretical performance of University. Following a year of global tures, Parasitics and Materials” electronics in this range is better upheaval and acute challenges, the by Dr. Myung-Hee Na (imec) than that of conventional devic- discussion reflected on the place of • “STT and SOT MRAM Technolo- es because of improved thermal/ electronics and the semiconductor in- gies and Their Applications from electrical conductivity, lower op- dustry in the future world. It brought IoT to AI Systems” by Prof. erating power, reduction of par- together experts from across science, Tetsuo Endoh (Tohoku Univ.) asitic losses, and diminished technology, media, and policy to dis- During the time-frame of the Con- chemical/metallurgical degrada- cuss future directions of microelec- ference, two Short Courses were also tion, to name a few effects. How- tronics, and explored the role future held. On-demand pre-recorded pre- ever, much work is needed to technologies can play in addressing sentations were available beginning realize the full potential of cryo- grand societal challenges, and in cre- Dec. 6, whereas the corresponding genic devices. The session includ- ating a more sustainable, equitable live summary/Q&A sessions took ed the following talks: “CMOS future. It also considered challenges place Sunday, Dec. 13. Cryo-Electronics for Quantum in attracting the best students and the • “Innovative Trends in Device Computing” by J. Craninckx et al evolution of electronics education to Technology to Enable the Next (imec), “Cryo-CMOS Interfaces suit future needs. The Panel was live- Computing Revolution,” orga- for Large-Scale Quantum Com- streamed Thursday, Dec. 17. nized by Anne Vandooren (imec). puters” by F. Sebastiano et al

January 2021 ❍ IEEE Electron Devices Society Newsletter 11

28neds01_Final_DigitalOnly.indd 11 1/20/21 11:14 AM (Delft Univ./UC-Berkeley/Intel), Drive Inverters” by E. Persson et Monolithic 3-D Integration” by “Cryo-CMOS Compact Model- al (Infineon), “Application of WBG K. Saraswat (Stanford). ing” by C. Enz et al (EPFL), “Chip Power Devices in Future Three- • Technologies Enabling 5G and Design for Future Gravitational Phase Variable Speed Drive In- Beyond—5G is the fifth and next Wave Detectors” by F. Tavernier verter Systems—‘How to Handle generation of cellular technolo- et al (KU Leuven), “A Low-Pow- a Double-Edged Sword’” by gy, promising much faster net- er CMOS Quantum Controller J. Kolar et al (ETH Zurich/Politecnico work speeds, bandwidth, lower for Transmon Qubits” by J. Bar- di Torino), “A 16 kV PV Invert- latency, reduced transmission din (Univ. Mass./Google), “III-V er Using Series-Connected 10 kV costs per bit and expanded con- HEMTs for Cryogenic Low Noise SiC MOSFET Devices” by R. Burgos nectivity. It will enable a host of Amplifiers” by J. Grahn (Chalm- et al (Virginia Polytechnic). new communications and com- ers Univ. of Tech/Low Noise Fac- • Future Interconnect Technology— puting approaches and appli- tory AB), “Superconductive Interconnect is the wiring which cations. The session included Single Flux Quantum Logic De- connects transistors and other the following talks: “Millimeter- vices and Circuits: Status, Chal- devices in an integrated circuit Wave Multi-Antenna/MIMO Tech- lenges, and Opportunities” by M. (IC). A key interconnect-related niques for 5G NR Base-Stations” Pedram (USC), “Phonon Blocked issue is that the performance of by R. Hou (Ericsson), “A Deep- Junction Refrigerators for Cryo- advanced ICs is limited by the in- Learning-Enabled Universal DPD genic Quantum Devices” by M. creasing resistance/capacitance System” by C.-L. I et al (China Prunnila (VTT Technical Research of the interconnect as it scales to Mobile Research Institute), “Milli- Centre of Finland). smaller and smaller dimensions. meter-Wave CMOS Phased-Array • GaN and SiC Projections—From Another key issue is the need for Transceiver for 5G and Beyond” Device to System Integration— effective interconnect strategies by K. Okada (Tokyo Institute of Wide-bandgap (WBG) semicon- for a range of 3D and 2.5D chip Technology), “PD-SOI CMOS and ductors have a relatively large architecture and packaging possi- SiGe BiCMOS Technologies for energy bandgap versus sili- bilities. The session included the 5G and 6G Communications” by con semiconductors, leading following talks: “The Overview P. Chevalier et al (STMicroelec- to smaller, faster, and more ef- of Current Interconnect Technol- tronics), “Heterogeneous Inte- ficient devices. These capabili- ogy Challenges and Future Op- gration for High-Frequency RF ties make WBG devices attractive portunities” by M-H Lee (TSMC), Applications” by A. Gutierrez- for a wide range of power ap- “Inflection Points in Intercon- Aitken (Northrop Grumman), plications, but converters pow- nect Research and Trends for 2 nm “Innovative Smart Cut™ Piezo- ered by WBG devices require and Beyond in Order to Solve On-Insulator (POI) Substrates for much innovation. The session in- the RC Bottleneck” by Zs. Tokei 5G Acoustic Filters” by E. Butaud cluded the following talks: “Pla- (imec), “Narrow Interconnects: et al (Soitec/TEMIS Innovation/ nar GaN Power Integration—The The Most Conductive Metals” by CEA-Leti). World is Flat” by K. Chen et al D. Gall et al (Rensselaer Polytech- • Energy Harvesting and Wireless (HKUST), “Progressing –190 °C nic), “Topological Semimetals for Power Transmission—Ambient to +500 °C Durable SiC JFET ICs Scaled Back-End-Of-Line Inter- energy is all around us, wheth- From MSI to LSI” by P. Neudeck connect Beyond Cu” by C-T Chen er from light, heat, motion, vi- et al (NASA Glenn Research Cen- et al (IBM/Univ. Delaware/Insti- bration, stray electric/magnetic ter/Ohio Aerospace Institute/ tute of Physics, Academia Sini- fields, or other sources. Convert- Vantage Partners), “Advances in ca/National Univ. of Singapore), ing it into electrical power, and Research on 300 mm Gallium Ni- “Staggered Metallization with Air transmitting that power without tride-on-Si(111) NMOS Transistor Gaps for Independently Tuned In- wires, is key to the ability to de- and Silicon CMOS Integration” terconnect Resistance and Capac- velop more capable autonomous, by H.W. Then et al (Intel), “GaN itance” by K. L. Lin et al (Intel), wireless, remote, and hard/impos- Power ICs: Reviewing Strengths, “From Interconnect Materials sible-to-connect devices for a va- Gaps, and Future Directions” by and Processes to Chip-Level Per- riety of uses. The session included O. Trescases et al (Univ. Toron- formance: Modeling and Design the following talks: “Toward Sol- to), “Monolithic GaN Power IC for Conventional and Explor- id State 3D Li-ion Micro-Batter- Technology Drives Wide-Bandgap atory Concepts” by V. Huang et ies and Microsupercapacitors Adoption” by D. Kinzer (Navitas), al (Georgia Institute of Technol- for Powering Miniaturized IoT “Gate Drive Concept for dv/dt ogy/Samsung), “Silicon-Com- Devices” by C. Lethien (IEMN- Control of GaN GIT-Based Motor patible Optical Interconnect and RS2E), “High-Power Graphene

12 IEEE Electron Devices Society Newsletter ❍ January 2021

28neds01_Final_DigitalOnly.indd 12 1/20/21 11:14 AM Micro-Supercapacitors” by Solutions), “MRAM DTCO and stacked nanoribbons. This architec- R. Kaner et al (UCLA/Max Planck Compact Models” by J. Song ture employs a vertically stacked Institute of Colloids and Interfaces/ et al (Univ. Minnesota), “Enabling dual source/drain epitaxial process Ariel Univ), “MEMS Vibrational Design Technology Co-Optimi- and a dual metal gate fabrication Energy Harvester for IoT Wireless zation of SRAMs Through Open- process, enabling different conduc- Sensors” by H. Toshiyoshi Source Software” by M. Guthaus tive types of nanoribbons to be built (Univ. Tokyo), “High-Voltage et al (UC-Santa Cruz). so that threshold voltage adjust- Micro-Plasma Switch for Efficient On-demand pre-recorded presen- ments can be made for both top and Power Management of Triboelec- tations within the technical program bottom nanoribbons. The approach tric Kinetic Energy Harvesters” by were available beginning Monday, combines excellent electrostat- P. Basset et al (Univ. Gustave Dec. 7. Live-streamed session sum- ics (subthreshold slope of <75 mV/ Eiffel/Cambridge Univ./Sorbonne maries by the session chairs with dec) and DIBL (<30 mV/V for gates Univ.), “Radiative Wireless Pow- Q&A opportunities took place Mon- ≥30 nm) with a path to significant cell er Transmission: From Indoor to day-Friday, Dec. 14–18. Here are sum- size reduction due to the self-aligned In-Body Applications” by H. Visser maries of several noteworthy IEDM stacking. These devices were used (imec), “Wireless Power Trans- papers which may be assigned to the to build a functional CMOS inverter fer for Internet of Things” by following fast developing disciplines: with well-balanced voltage transfer Y. Kawahara et al (Univ. Tokyo), characteristics. “mmWave Backscatter Front-End CMOS Technology: Embracing Proving 3D Design Viability: 3D ICs for 5G-IoT/WPT Applications” by New Ways to Drive Performance have the potential to drive continued D. Matos et al (Univ. de Aveiro, Stacked NMOS-on-PMOS Nanorib- performance according to Moore’s Sinuta S.A, Instituto Politecnico bons: From planar MOSFETs, to Law, but achieving lower interconnect de Viseu). FinFETs, to gate-all-around (GAA) or latency and power consumption, im- • DTCO of Advanced Logic and nanoribbon devices, novel transistor proved bandwidth and cost efficien- Memory—Given the increasing architectures have played a critical cies is challenging. That’s because it sophistication and complexity of role in driving the performance pre- is difficult to test 3D IC designs once semiconductor devices and soft- dicted by Moore’s Law. In the paper they are produced. A better linkage ware design tools, bringing hard- #20.6, “3-D Self-Aligned Stacked of design and test functions with ware and software developers NMOS-on-PMOS Nanoribbon Tran- process technology is needed to together to work in an integrat- sistors for Continued Moore’s Law improve 3D IC performance. In the ed, efficient manner is needed to Scaling,” Intel researchers described paper #15.1, “A High-Density Logic- produce future devices faster and what may be the next step in that on-Logic 3DIC Design Using Face- at less cost, but there are many evolution: NMOS-on-PMOS transis- to-Face Hybrid Wafer-Bonding on challenges. The session includ- tors built from multiple self-aligned 12 nm FinFET Process,” researchers ed the following talks: “DTCO Launches Moore’s Law Over the Feature Scaling Wall” by V. Moroz et al (Synopsys/IC Knowledge), “Advanced Node DTCO in the EUV Era” by A. Wei et al (Intel), “Next-Generation Design and Technology Co-Optimization (DTCO) of System on Integrated Chip (SoIC) for Mobile and HPC Applications” by Y.-K. Cheng et al (TSMC), “DTCO Including Sus- tainability: Power-Performance- Area-Cost-Environmental Score (PPACE) Analysis for Logic Tech- nologies” by M. Garcia Bardon et al (imec), “Enabling Efficient Design-Technology Interaction by Spec-Driven Extraction Flow” Paper #20.6: (a) a process flow of the vertically stacked dual metal gate process; (b) a TEM image; by H.-L. Changet al (Primarius (c, d) EDS images of the dual metal gate with N-WFM (WFM = work function metal) on the top Technologies/ProPlus Design two nanoribbons and P-WFM on the bottom three nanoribbons.

January 2021 ❍ IEEE Electron Devices Society Newsletter 13

28neds01_Final_DigitalOnly.indd 13 1/20/21 11:14 AM from Arm and GLOBALFOUNDRIES used to build large-area multi-level volatile memory (eNVM). In the paper described a 3D IC test vehicle that graphene (MLG) interconnects on #24.2, “High Density Embedded PCM

demonstrated the benefits of this ap- dielectric (SiO2) and metallic (Cu) Cell in 28 nm FDSOI Technology for proach. It is based on a high-density, substrates. The interconnects are Automotive Micro-Controller Appli- face-to-face wafer-bonding technolo- BEOL-compatible and incorporate cations,” a STMicroelectronics/CEA- gy with 5.76 µm-pitch 3D connections edge-contacting metal vias (versus Leti team detailed an ultra-dense and 12 nm FinFET devices. Its cache- top contacts), in a doped-MLG/Co-via (cell size = 0.019 µm2) embedded coherent interconnect mesh (to allow multi-level structure. The researchers phase-change memory (PCM) tech- synchronized operations in each lay- performed scaling analyses which nology for automotive SoCs that er) operated at up to 2.4GHz, with 10x showed that an increase in total via- meets the stringent AEC-Q100 Grade lower bandwidth density (3.4 TB/s/ resistance in the structure is more 0 standard for automotive reliability. mm2) and energy usage (0.02 pJ/bit) than compensated for by reduced It leverages a 28 nm fully depleted sil- versus state-of-the-art 2.5D/3D bump- wire resistance and parasitics, result- icon-on-insulator (FDSOI) substrate; based technologies. The researchers ing in a ~1.5x improvement in overall novel super-shallow trench isolation said it was an essential step toward circuit performance compared to that (SSTI) for the bit line (requiring no proving the viability of 3D designs of the dual-damascene process. trench etch-and-fill); high-voltage for next-generation high-performance, (5V) triple-gate-oxide transistors; and energy-efficient ICs. Making New Memories a compact bipolar junction transistor CMOS-Compatible Graphene In- High-Density 28 nm FDSOI Embed- (BJT) selector. terconnects: With continued scaling, ded PCM Memory for Automotive: 3D Embedded DRAM Using conventional dual-damascene in- Scores of microcontrollers are used Stacked Anti-Ferroelectric HZO Ca- terconnect technologies suffer from in today’s vehicles, to monitor and pacitors: In the paper #28.1, “Anti-

higher resistance and self-heating, control advanced driver-assistance Ferroelectric HfxZr1-xO2 Capacitors for and diminished reliability. Graphene systems (ADAS), powertrain control, High-Density 3D Embedded-DRAM,” interconnects are good candidates infotainment and comfort systems, Intel researchers discussed their work for interconnects in future technology and others. These SoCs must offer using the antiferroelectric (AFE) mate-

nodes. In the paper #31.1, “Reliability high-performance, low-power opera- rial hafnium-zirconium-oxide (HfZrO2) and Performance of CMOS- Compat- tion and high levels of reliability. As to make a 3D deep-trench capacitor ible Multi-Level Graphene Intercon- the software code which runs auto- for potential use in embedded DRAM nects Incorporating Vias,” a UCSB-led motive systems grows larger, the memories. It demonstrated endur- team described a CMOS-compatible need also grows for more code stor- ance of 1012 cycles even at elevated solid-phase growth technique they age in high-density embedded non- temperatures, and a 1.8 V operating voltage. The researchers used these AFE capacitors in a novel memory architecture for ultra-high bit density: a vertical stack based on one access transistor with multiple AFE capacitors in parallel. Each capacitor represents a single memory bit. A significant density boost was achieved by stacking four AFE capacitors in a vertical fash- ion, with no area increase. A New Force in Ferroelectric Tun- nel Junction Memories: Ferroelectric tunnel junctions (FTJs) are promising for non-volatile memory (NVM) applications like ultralow-power data storage and neuromorphic computing. They feature an ultrathin ferroelectric barrier layer sandwiched between two electrodes. Modulating the barrier resistance or “height” by control- Paper #28.1: A cross-sectional TEM image of stacked vertical capacitors (4X), along with a ling its polarization prevents or allows cross-sectional representation of the 1T-4C memory architecture, showing a future path toward the quantum tunneling of electrons high-density memory. through it, enabling the storage or

14 IEEE Electron Devices Society Newsletter ❍ January 2021

28neds01_Final_DigitalOnly.indd 14 1/20/21 11:14 AM retrieval of data. However, finding an optimum barrier material has been challenging. In the paper #4.1, “Multi- scale Simulation of Ferroelectric Tun- nel Junction Memory Enabled by van der Waals Heterojunction: Compari- son to Experiment and Performance Projection,” a University of Florida-led team discussed their work simulat- ing and building a ferroelectric tunnel junction by vertically stacking thin (~4 nm) layers of a van der Waals ma-

terial (CuInP2S6 ) on a layer of graphene to create atomically think heterojunc- Paper #38.3: (a) a schematic cross-section of a double dot; (b) equivalent circuit of a double dot; tions at the CIPS-graphene interface. (c) tunable tunnel coupling between the double dot for nMOS (upper) and pMOS (lower) devices. The heterojunctions are sandwiched The plunger gates P1 and P2 control the potential of dot 1 and 2, respectively. B2 controls the inter-dot coupling. In the weak coupling regime, dot 1 and 2 are separated. Conductance maps between an SiO2 substrate and a top metal (gold) contact. (van der Waals show isolated points when energy levels between dots are aligned. In the medium coupling forces are weak attractive/repulsive regime, levels of double dots begin to hybridize. Conductance maps show honeycomb patterns. forces between atoms, molecules In the strong coupling regime, two dots merge into one. and surfaces.) Simulations of the performance of these heterojunctions, flexible enough to use in studies of lengths can be used to make detailed verified by laboratory experiments, silicon qubit characteristics is need- 3D representations of a target. It’s a showed a record-high tunneling elec- ed. In the paper #38.3, “A Flexible critical technology for autonomous troresistance ratio of ~6 x 107, pointing 300 mm Integrated Si MOS Platform vehicles, robotics and augmented- the way to a possible new NVM mem- for Electron- and Hole-Spin Qubits reality applications. In the paper #7.2, ory device structure with an exponen- Exploration,” imec researchers de- “Single-Chip Beam Scanner with In- tially higher ON/OFF ratio than existing scribed the first such platform based tegrated Light Source for Real-Time devices, and ~1ns read latency. on industry-standard 300 mm silicon Light Detection and Ranging,” Sam- wafer fabrication technology instead sung researchers reported the first Quantum Computing of specialized laboratory processes. single-chip lidar beam scanner. It Qubits Start to Move From Lab to It uses both optical and electron- opens up the possibility of ultra-low Fab: Qubits are often made from beam lithography to fabricate silicon cost, compact lidar systems because quantum dots, particles a few nano- spin qubits, and enables on-the- it requires no separate light source, meters in size made from semi- fly layout design modifications for unlike current systems which are conductors. However, qubits are devices having either n- or p-type larger and use mechanical beam unstable, with short “coherence ohmic implants, pitches <100 nm, scanners with motors and rotat- times” (i.e., how long they can stay and uniform critical dimensions ing and mirrors. It integrates a fully in a quantum state). Some quantum down to 30 nm. The researchers said functional 32-channel optical phased computers exist, but they use only a the design platform enabled them to array, 36 optical amplifiers, and tun- few qubits, are error-prone and frag- achieve nearly 100% device yields able laser diode onto a 7.5 x 3 mm2 ile, and operate at cryogenic temper- for qubits with 30 nm spacings. They chip, fabricated with III-V-on-Si pro- atures. Silicon-based quantum-dot plan to use it to incorporate addi- cesses. Also, a calibration algorithm qubit systems are attractive for po- tional materials and structures into based on machine-learning prin- tential use in large-scale quantum qubits for further study, and to im- ciples is used in digital signal pro- processors because they have dem- prove cryogenic characterizations. cessing for real-time operation. The onstrated relatively long coherence device achieved real-time 20 frames- times and high-fidelity operation Advances in Imaging per-second operation, at a resolution in laboratory settings, and because Single-Chip Lidar: Lidar (light detec- of 120 x 20 lines, at 10 meters. silicon technology is widely used tion and ranging) is the optical coun- Ultra-High Resolution Mobile and economical compared to other terpart of radar and uses laser light CMOS Imager: In the paper #16.2, “A material systems. But cryogenic ma- instead. It’s extremely fast and lends 0.8 μm Nonacell for 108 Megapixels terial properties and other aspects itself to sophisticated data process- CMOS Image Sensor with FD-Shared of qubit design are still not well- ing, which means that differences in Dual Conversion Gain and 18,000e- understood, and a design platform laser light return times and wave- Full-Well Capacitance,” Samsung also

January 2021 ❍ IEEE Electron Devices Society Newsletter 15

28neds01_Final_DigitalOnly.indd 15 1/20/21 11:14 AM detailed a 0.8 µm-pitch 108-megapix- 18,000e- FWC and 32% quantum ef- reported that with a scaled source/ el (Mp) ultra-high resolution CMOS ficiency (QE), has a pyramidal surface drain distance and gate length, and image sensor for mobile applica- for diffraction (PSD) structure which low-resistance ohmic contacts, tions. As demand for higher-resolu- improves QE at smaller pixel sizes, p-channel GaN HFETs demonstrat- tion image sensors for smartphones and uses 3.5 μm pixels. Low power ed ON currents >420 mA/mm and

and other mobile devices has grown, consumption is achieved with low fT/fMAX~20 GHz. When combined with the number of pixels they contain has iToF leakage current and with the the excellent performance of AlN/ increased from 48 Mp, to 64 Mp, to use of low-resistance Cu-Cu intercon- GaN n-HFET devices that has been 108 Mp. Pixel pitch has decreased to nections. The researchers said these reported previously, these new re- enable higher densities, but this has device architectures enabled high- sults are poised to take this wide- reduced pixel silicon volume as well resolution and wide-dynamic-range bandgap CMOS platform into new as the amount of incident light avail- 3D depth-sensing for both near and application domains in the RF and able at each pixel. These reductions far objects. power electronics arenas. have degraded pixel signal-to-noise Lithographically Defined Organic performance and full well capacity High-Frequency and Substrates for RF: Radio-frequency (FWC, or the number of electrons a Power Devices (RF) ICs use ceramic packaging sub- pixel can collect at saturation level). 20 GHz p-Channel HFETs: CMOS strates, while digital circuits such as Samsung researchers got around technology requires both n- and p- CPUs, GPUs and APUs use organic this with a 3 x 3 shared pixel struc- channel devices, but the perfor- substrates. Ceramics are well-suited ture they call Nonacell. It consists of mance of p-channel devices lags, a for use with low-loss, high-conduc- three shared pinned photodiodes, mismatch which must be addressed tivity metal conductors, but organics whose signals are summed in the to obtain maximum performance support a wider range of dielectric imager’s floating diffusion (FD) and and energy efficiency from future thicknesses, tighter manufacturing whose voltages are averaged. The chips. In the paper #8.3, “GaN/AlN variations, low-surface-roughness

shared-pixel units can be combined p-Channel HFETs with Imax >420 mA/ conductors and finer design rules. All

in various ways to achieve optimum mm and ~20 GHz fT/fMAX,” Cornell and of these are needed for the increased performance in changing light condi- Intel researchers described the first circuit density and performance de- tions—ultra-high 108 Mp resolution GaN-based p-channel transistors manded by tomorrow’s high-frequen- for bright outdoor daylight condi- to break the GHz speed barrier. To cy applications. In the paper #17.5, tions, and 12 MP resolution for low- build them, the researchers took ad- “Organic Package Substrates Using luminescence indoor light. The work vantage of the polarization-induced Lithographic Via Technology for RF to is a step toward much higher image 2D hole gas found in the GaN/AlN THz Applications,” Intel-led research- quality for smartphones and other heterostructure. (Hole gas refers ers detailed a new manufacturing pro- mobile devices. to the population of free holes in a cess for low-loss organic substrates. Low-Power, High-Resolution CMOS metallic conductor, which are free to It uses lithographically defined (ver- Imager for Indirect Time-of-Flight: move about within it much like mol- sus laser-drilled) vias, bringing to- Indirect time-of-flight (iToF) CMOS ecules of gas move in a container. gether tighter process tolerances and image sensors are used for distance “2D” means they are free to move copper interconnect in the substrate. measurements in smartphones and in two dimensions.) The researchers The researchers built structures and gaming systems, and improv- devices like coaxial and coplanar ing their precision while main- waveguides, high-Q RF inductors, taining/decreasing their power filters and others in the frequen- consumption is a key goal. In cy range from 1–330 GHz, which the paper #33.1, “Low Power demonstrated superior electrical consumption and High Resolu- performance versus ceramics. tion 1280 x 960 Gate-Assisted They said performance could be Photonic Demodulator Pixel for improved with new dielectric ad- Indirect Time-of-Flight,” Sony re- hesion techniques and advanced searchers will describe how they organic dielectric build-up films. built a floating-diffusion-storage 40 kV Silicon Vacuum Transis- global-shutter image sensor tor: In the Paper #5.2, “Demon- with a resolution of 1280 × 960 at stration of a ~40 kV Si Vacuum 10 meters, implemented as a 3D- Transistor as a Practical High Fre- stacked, back-illuminated iToF Paper #33.1: A cross-section of the 1.2M pixel gate-assist- quency and Power Device,” an sensor. The iToF sensor achieves ed photonic demodulator (GAPD) for iToF. MIT-led team described the first

16 IEEE Electron Devices Society Newsletter ❍ January 2021

28neds01_Final_DigitalOnly.indd 16 1/20/21 11:14 AM Si vacuum transistor operating at ~40 kV and with the potential to have a semiconductor-like footprint. Such a high voltage level is normally reserved for wide-bandgap materials like SiC and GaN. The proof-of- concept device consists of a gated field emission array (i.e., an electron source), a vacuum drift region and a metal anode. Electrons are emit- ted from the gated field emission array into the vacuum through tunneling, travel through it and are col- Paper #5.2: (a) Tilted and (b) cross-sectional SEMs for gated FEAs. (a) shows an array of gated lected at the anode. The vacuum sharp tips in the middle of a ~200–300 nm aperture, formed through a self-aligned fabrication determines the transport properties process; (b) shows the high aspect ratio nature of the nanowires (~6–10 μm tall) with a and the high-voltage isolation. Us- diameter of 200 nm. On top of this nanowire a sharp tip exists to concentrate the ing this technology as a baseline, the E-field of the surrounding polysilicon gate. researchers provided intrinsic benchmarks for vacuum transistors. They 5.2 kV breakdown voltage, specific on- mature, highly scalable amorphous said the high critical electric field and resistance as low as 13.5 mΩ · cm2, and silicon (a-Si) thin-film transistor unbounded carrier velocity of these low off-state leakage current, leading (TFT) technology used in flat-panel devices could lead to compact, high- to a 2 GW/cm2 figure of merit which displays (FPDs) could be leveraged performance vacuum devices able surpasses that of unipolar SiC Schott- to create a high-precision, high- to outperform solid-state devices on ky barrier diodes. The results show the throughput, online and program- all metrics, making them suitable potential of AlGaN/GaN multi-channel mable microfluidics platform for for a range of high-power and high- devices for medium- and high-voltage bio-sample handling. Electrowetting frequency applications, and also as power applications. is the modification of the wetting next-generation X-ray sources. properties of a surface with an ap- 5 kV AlGaN/GaN Power Schottky Noteworthy Papers on plied electric field. An electrode array Barrier Diodes: For years, bipolar Si Diverse Topics beneath the surface applies voltage PN diodes have been the main diode Large-Area Active-Matrix Microflu- signals in specific locations in se- technology used to build high-voltage idics Platform: In the paper #35.5, quence, and liquid droplets on the (1.7–10 kV) rectifiers for industrial mo- “Large-Area Manufacturable Active surface in those areas move, merge, tor drives, pulsed power systems, and Matrix Digital Microfluidics Platform mix and/or separate by following power grid applications, but the diode for High-Throughput Biosample the electric field. The team used FPD performance is limited by poor re- Handling,” a team led by the Suzhou active-matrix technology to fabricate verse-recovery times. More recently, Institute of Biomedical Engineering a chip containing a 32 × 32 pixel ar- unipolar SiC Schottky barrier diodes and Technology at the Chinese Acad- ray (i.e., an electrode array) in an ac- and junction barrier Schottky diodes emy of Sciences showed how the tive area of 10 cm2. Each pixel can have been demonstrated up to 10 kV, and commercialized at 3.3 kV. GaN, however, has superior physical properties to Si and SiC. In the paper #5.4, “5 kV Multi-Channel AlGaN/GaN Pow- er Schottky Barrier Diodes with Junc- tion-Fin-Anode,” a Virginia Tech-led team described the first multi-kV operation of lateral AlGaN/GaN Schottky diodes. Built on 4-inch GaN-on-sapphire wafers, the devices consist of a stack of five parallel 2DEG (two-direc- Paper #5.4: (left) A 3D schematic of the multi-channel AlGaN/GaN SBD with junction-fin-anode tional electron gas) channels in com- (JFA). The anode metal is partially removed to show the internal structure. (right) Cross-sections bination with a fin-based 3D anode along the cutlines #1- #3, and the equivalent circuit model of the JFA- SBD with the internal structure which wraps the p-n junction voltage distribution at a high reverse bias VR. The diode in the planar p-gate HEMT around the fins. They demonstrated a represents the planar Ni/p-NiO/p-GaN junction.

January 2021 ❍ IEEE Electron Devices Society Newsletter 17

28neds01_Final_DigitalOnly.indd 17 1/20/21 11:15 AM be individually or simultaneously addressed, and manipulation of droplets at single-pixel level with a ~1% volume coefficient of variation was shown. This performance is a substantial improvement over the current state-of-the-art (9-pixel resolution and 4% variation), is scalable to larger array sizes, and opens up possibilities for on-chip diagnostics in point-of-care testing. Nanophotonic, Battery-Free Sen- sor for Glaucoma Monitoring: Glau- coma, one of the leading causes of

blindness, is largely caused by an el- Paper #3.1: (a) For MoS2, Pelgrom lines don’t cross the origin, hence variability doesn’t approach evated intraocular pressure (IOP). Cur- zero in the limit of very large dimensions. Other process-related sources of variability are present.

rent IOP monitoring techniques are 1–2ML MoS2 FETs (EOT = 2.6 nm) have higher σ∆Vt (b) but their slope AVt approaches the Si imprecise, provide no long-term mon- FinFET reference (EOT = 0.8 nm). itoring, and have difficult readouts. In the paper #14.5, “Nanophotonic encryption keys, but such passwords vanced technology nodes and future Sensor Implants with 3D Hybrid Pe- are often logical and easily hacked. A transistors with ultra-scaled chan- riodic-Amorphous Photonic Crystals hardware-based True Random Num- nel lengths, 2D channel materials

for Wide-Angle Monitoring of Long- ber Generator (TRNG) that relies on like molybdenum disulfide (MoS2) Term In-Vivo Intraocular Pressure,” a the randomness of physical phe- promise better control of electro- Samsung/Caltech team described a nomena like manufacturing process statics than Si FinFETs, and hence highly miniaturized (500-μm diameter, variations to generate encryption better immunity to short-channel 200-µm thick) optomechanical nano- keys can’t be easily hacked. However, effects (SCE), which become a photonic sensor implant for long- existing RRAM-based TRNGs don’t relatively larger performance is- term, continuous and on-demand have all the required features, such sue at smaller dimensions. In the IOP monitoring. The battery-free IOP as high speed operation, highly reli- paper #3.1, “Sources of Variability

sensor is made of a flexible, spongy able performance, and simple circuit in Scaled MoS2 FETs,” an imec-led medical-grade silicone containing 3D design. In the paper #39.3, “Novel team performed the first study of

photonic nanostructures, produced Concept of Hardware Security Using variability in nanoscale MoS2 devic- using a colloidal self-assembly process. Gate-switching FinFET Nonvolatile es (channel width = 115 nm; length It functions as a pressure-sensitive Memory to Implement True-Random- = 30 nm). The researchers looked at

optical resonator with a sensitivity of Number Generator,” a National Chiao sources of variability like MoS2 thick- 0.1 nm/mmHg, and delivers IOP read- Tung University-led team described a ness, the impact of bilayer islands

ings when interrogated with invisible TRNG device architecture comprising (i.e., grains) of MoS2, the impact of near-infrared light. The researchers a one-transistor resistance switching a sapphire growth template, and implanted eight sensors in the eyes of memory as a core and a 40 nm pe- resulting electrical impacts. They white rabbits, and demonstrated dy- ripheral circuit. The core is an integra- simulated and built devices with a namic and long-term changes of IOP tion of a metal-insulator-metal (MIM) median subthreshold slope (SS) of

in awake rabbits with an average ac- capacitor on FinFET platform—es- 80 mV/dec and Imax >100 µA/µm, and

curacy of 0.56 mm Hg over the range sentially, a NOR-type resistance-gate found that thinning the MoS2 mate- of 0–40 mm Hg. With further sensor integrated with the FinFET. Its drain rial from three layers to one layer refinements and detector automation, current is randomly distributed as results in strongly reduced SS and it may become a viable choice for pa- a result of time-varying conducting threshold voltage variability. Over- tient-initiated glaucoma management filaments, and the researchers said all, their work showed intrinsic vari- in the home environment. it was an ideal entropy source for a ability is low and comparable with Resistive-Gate FinFETs Enable TRNG. They benchmarked its perfor- Si FinFETs. The researchers said Hardware Security: Digital devices mance and reported that it passed all better control of key process steps are ubiquitous in today’s society, relevant NIST statistical tests for se- like transfer, cleaning and contacts

but internet attack incidents have in- curity applications. would further lower MoS2 device creased dramatically in recent years. Understanding Varia bility in variability, making it suitable for fu-

Software has been used to generate Scaled MoS2 Transistors: For ad- ture technology nodes.

18 IEEE Electron Devices Society Newsletter ❍ January 2021

28neds01_Final_DigitalOnly.indd 18 1/20/21 11:15 AM HIGHLIGHTS OF THE 2020 IEEE PHOTOVOLTAIC SPECIALISTS CONFERENCE

The 47th IEEE Photovoltaic Special- sentation that emphasized the impor- accomplishments. Both Mool (for con- ists Conference (PVSC-47) was held tance of collaboration and teamwork tributions to laser material and inter- this year as an online fully virtual to success between groups adept at actions) and Steven (for contributions event from June 15 to August 21, electronics, device physics, materials to compound semiconductor photo- 2020. While originally planned as an science, chemistry, and manufactur- voltaics) have made significant and in-person event to be held in Calgary, ing (key to translating lab success to lasting impacts in the field of photo- Canada, the circumstances surround- large scale). Dr. Sites went on to ex- voltaics and we congratulate them on ing the novel coronavirus (COVID-19) plore a variety of thin film materials, being elevated to IEEE Fellows! forced cancellation of the Calgary what has worked and what has not, event and a move to a fully virtual how alloying and grading have been conference. Despite the short time introduced to preferentially adjust period to do this, PVSC-47 was quite bandgaps. He discussed some of the successful! A total of 730 papers were strengths of thin films (low cost man- presented virtually at PVSC this year ufacturing, non-crystalline material with an estimated attendance of near- is forgiving), some of the challenges ly 1300 people. PVSC is well recog- (grain interfaces, hard to optimize all nized as an international conference, parts of the structure simultaneous- and this year was no different with at- ly), and some of the future outlook tendance from 60 different countries. (semi transparency for windows/agri- The virtual format also allowed atten- culture, flexible, tandem designs). Dr. dance by many countries that have Sites will be presented with a plaque, not previously attended PVSC, such as well as our applause and congratu- as Somalia, Togo and Namibia! lations, in person at next year’s PVSC. Numerous live sessions were host- Dr. Brett Hallam was this year’s ed during the initial week of the con- Stuart R. Wenham Young Professional ference from June 15th–19th. These Award winner, for his work on ma- sessions included some of the best nipulating hydrogen charge states papers in each of the technical areas (advanced hydrogenation) for defect as well as live Q&A and panel ses- passivation, and development of rapid sions with the authors. In addition, processes to eliminate a light induced the full tutorial program (10 topics) degradation (LID) and a light- and was offered virtually, drawing nearly elevated temperature-induced deg- 400 participants. A number of special radation (LeTID), which he and the Uni- topic sessions on hot carriers and III-V versity of New South Wales (UNSW) technology were also held throughout hydrogenation team subsequently June, allowing researchers in these commercialized. His latest achieve- areas to connect in a virtual panel for- ment is the demonstration of p-type Cz (top) Dr. Seth Hubbard, Conference General mat. Importantly, all of the PVSC-47 heterojunction solar cells with stable Chair, kicks off the 47th PVSC from his virtual papers and presentations were avail- open circuit voltages >735 mV. Dr. headquarters (middle) Dr. James Sites accepts able online through the summer until Hallam made a gracious acceptance (virtually) the William R. Cherry Award (bottom) August 21st, allowing our attendees speech and we look forward to pre- Dr. Christian Breyer answering questions fol- ample time to view and digest the ex- senting him with a plaque at PVSC-48. lowing his excellent Keynote address. citing results presented this year. In In addition, two newly minted fact, at the close of the conference, IEEE Fellows in the PV community Best Student Paper Awards were the total cumulative views of PVSC-47 were recognized at PVSC-47, Drs. issued in each of the technical cate- presentations was nearly 250,000! Mool Gupta and Steven Ringel. Being gories. The award winners are listed The highest award presented at named a Fellow is one of the highest in the table below. Congratulations the conference, the William R. Cherry honors bestowed by IEEE, reserved to all of these students for their ex- Award, was presented this year to for a very select group of members cellent contributions to our field! You Dr. James Sites of Colorado State (less than 0.1% per year), in recogni- can find their proceedings papers on University. Dr. Sites had a great pre- tion of their extraordinary record of IEEE Xplore.

January 2021 ❍ IEEE Electron Devices Society Newsletter 19

28neds01_Final_DigitalOnly.indd 19 1/20/21 11:15 AM Area Last Name Title Affiliation presentation, reviewed each submission. The students presented amazing 1 Kohei Wata- Up-converted photocurrent en- Kobe nabe hancement in modulation-doped University work portraying PV concepts as inte- two-step photon up-conversion grated into society for the near and solar cells distant futures. This year’s winners are 2 Swapnil Investigating the potential of Purdue listed below, congratulations to these Deshmukh amine-thiol solvent system for University up and coming PV scientists and en- high-efficiency CuInSe2 devices gineers!! Links to the videos and nar- ratives can be found at the PVSC-47 3 Felix Predan Wafer-bonded GaInP/GaAs/GaInAs// Fraunhofer GaSb four-junction solar cells ISE website (https://www.ieee-pvsc.org/ with 43.8% efficiency under PVSC47/events-YouthScholars) concentration Joint Markus Advances in epitaxial GaInP/GaAs/ Fraunhofer Solar Energy Video Feifel Si triple junction solar cells ISE Pitches Winners • First place: Solar4Students: 4 Saman Boron-oxygen related light-induced UNSW Alyssa Dora Jafari degradation of Si solar cells: School Pavilions. Transformation between minority Cortez & Jawed Nur. Incoming carrier trapping and recombination 12th graders from Bioscience active centers High School, Phoenix Arizona. 5 Shuai Nie Temperature-dependent photolu- UNSW • Second place: Hybrid Solar Panels. minescence imaging using non- Jasmin Martinez Castillo. Incom- uniform excitation ing Junior for Bioscience High School, Phoenix Arizona. 6 Noor Har- Capping layers design guidelines MIT tono for stable perovskite solar cells via • Third place: Everlasting. Yash machine learning and Veer Pahwa. Yash is in 12th grade and Veer is in 9th grade 7 Ryan Hool Electron irradiation study of meta- UIUC morphic 1.7 eV GaAsP solar cells at Tower Hill School, in Wilmington DE. 8 Sanghyuk Learning from Tetris: A new ap- Korea • Honorary Mentions: Lee proach for the automated configu- Polytechnic • . Faith ration of the interconnection layout University Makin’ it Photovoltaic of BIPV modules for large-scale Skinner and Andrew Kallai. application Faith and Andrew are rising 12th graders at Appoquinimink 9 Bennet Solar Data Tools: Automatic Solar Stanford Meyers Data Processing Pipeline University High School in Middletown, DE. • Aqualidad. Maryan Robledo. 10 Severin A measurement-based gradient- University Maryan is a rising Junior at Nowak descent method to minimize loss of British Bioscience High School, in by dispatching DER reactive power Columbia Phoenix AZ. 11 Michael An assessment of the value princi- University Hopwood pal component analysis for pho- of Central Future Narrative Winners tovoltaic IV trace classification of Florida physically-induced failures • First place: Bon City. Jazmine Cordon. Jazmine is an incom- 12 Amrita Rag- Public Survey Regarding the University ing 9th grader from Sevilla West hoebarsing Acceptance of Photovoltaic of Twente Middle School. Systems in Suriname • Second place: Sincerely, Maisy. Bonnie Law & Mallory Creveling. Bonnie and Mallory are 7th Outreach, Diversity and Inclusion tests, the first to produce a 90 second graders at Gunning Bedford Youth Scholar Program Chair Silvana video “pitch” to portray an idea for a Middle School, in New Castle DE. Ayala Pelaez from National Renewable project in solar energy. The second, to • Third place: Energy Laboratory (NREL) and Youth produce a “future narrative” describ- • The Future of New Solar Cell Outreach Coordinator Michelle Jordan ing through words or images a vision Trees. Irwin Wang. Irwin is an from Arizona State University (ASU) of what a solar powered world might 8th grader at Odyssey introduced our youth scholar pro- look like. At least eight of our PV col- Charter School in Wilmington, gram. This year there were two con- leagues, identified individually in the Delaware.

20 IEEE Electron Devices Society Newsletter ❍ January 2021

28neds01_Final_DigitalOnly.indd 20 1/20/21 11:15 AM • S.O.A.R. Since 3040. Alyssa taics event on June 18th. Using a Keynote Dora Cortez. Alyssa is an in- combination of lecture and breakout Christian Breyer (LUT University coming 12th grader at Biosci- sessions, they introduced concepts Finland) presented the Keynote on ence High School, Phoenix AZ. of diversity and intersectionality, ef- the “Dawn of the Solar Age: On the • Honorary Mentions: fects of gender in the workplace and history of PV in 100% renewable • Follow the Light. Venezia Al- the obstacles it causes. The focus of energy scenarios and future pros- ana Figueroa. Venezia is a 9th the workshop was on five “derailers’’ pects’’, contrasting a brief history grader at Bioscience High which negatively affects representa- from Becquerel to the first silicon PV School, Phoenix Arizona. tion of women in leadership roles, at Bell Labs in 1953 with another his- • Miner 145. Andrew Zhao. An- each discussed in detail: unconscious tory you may be less aware of, the drew is a rising senior at Char- bias, inadequate sponsorship, lack of exploration of a 100% renewable en- ter School of Wilmington, in specific feedback, gender gap in rec- ergy (RE) scenario which has been Wilmington DE. ognition, and work-life conflict. The fi- published in the literature since the • A day in the life in a solar-pow- nal portion of the session focused on mid-1970s. Defossilization of energy ered world. Aidan Hearn. Aid- leading change within an individual’s resources is critical to our collec- an is a 7th grader at Northley organization, using actionable plans tive future, and towards that goal Middle School, in Aston PA. to address each of these details, on photovoltaics is likely to contribute The first annual Minority Carriers both individually and team-wide. as much as 80% from some reports Panel convened on June 16th, 2020 via zoom webinar, was moderated by Dr. Lyndsey McMillon-Brown, NASA Glenn Research Center, with panelists: Prof. Adrienne Stiff-Roberts, Duke University; Prof. Tyler Grassman, The Ohio State University; Dr. Joe Berry, NREL; and Dr. Nikhil Jain, X Display Company. This event provided many diverse individuals and their allies with the space to connect with one another, identify problems within the PV community and generate solutions to make our PV community accu- rately representative of the communities that we serve, and inclusive to all. This solutions-based discussion yielded actionable tasks and practices that attendees can implement in their academic and professional spaces to develop diverse teams, facilitate inclusion, and confront injustices and microaggressions. The panelists also provided advice for allies and advo- cates with guidance to educate themselves about their privilege, become good listeners, practice empathy, and amplify the voices of margin- alized individuals. Jennifer Allyn (Senior Advisor at Women of Renewable Industries and Sustainable Energy, WRISE) and Anne Weisberg (Director of the Women’s Initiative at Paul, Weiss, Rifkind, Wharton & Garrison, LLP) Fig. 1 Data compiled by Dr. Breyer for his keynote address showing various sources for the esti- presented and facilitated a workshop mated PV share of generation (top) as well the PV energy production (bottom) in a for this year’s Woman in Photovol- 100% RE scenario.

January 2021 ❍ IEEE Electron Devices Society Newsletter 21

28neds01_Final_DigitalOnly.indd 21 1/20/21 11:15 AM (Figure 1 top panel). This demands at ates power by facing a hot sun and with a Mott barrier configuration. This least 20,000+ TWh from solar PV by absorbing photons. When facing allows energetically favorable extrac- 2050 to support a 100% RE goal (Fig- cold space and emitting photons, it tion of carriers, excited high into the Γ ure 1 bottom panel). To further work still drives an internal current, which valley, into metastable states in lower towards this future, better “power- shifts a power-generating compo- adjacent L valleys. This removes the to-x” efficiencies are required for nent from the normal position in the need for energy selective contacts. electricity driven chemical process- 4th quadrant of an IV sweep to the This concept was demonstrated in a ing, heating, steel manufacture, wa- 2nd quadrant. This was experimen- device incorporating InAlAs and In- ter desalination, to name a few. In tally verified using a temperature GaAs. From the data, extrapolated

discussions following the talk, Dr. controlled emissive surface to an in- JSC and VOC were promising, but poor Breyer stressed the importance of frared optical diode separated by an performance in the 4th quadrant of challenging outdated assumptions optical chopper. The thermodynam- the IV curve suggested further com- about PV prevalent in the literature, ics was further explored discussing plications with carrier extraction, with asking those tasked with peer review various efficiency limits with the un- suggestions of future work currently to cross check numbers and hold au- derstanding the heat engine was no within reach. thors accountable. longer Sun to Earth via cell, but Sun to universe via Earth. Area 2: Chalcogenide Conference Highlights Eric Chen (ASU) gave an extended PV Roadmap (Panel) Continuing with the tradition of the talk on enhancing internal reflectance Chuck Hages (Area 2 Chair) intro- past few years, the 47th PVSC was in solar cells with angle- and energy- duced the panel, made up of B.J. divided into 12 technical areas cov- selective reflectors. This work intro- Stanbery, Heliovolt/Siva Power; ering cutting-edge developments in duces a modified detailed balance Lorelle Mansfield, NREL; Wyatt science and engineering of photo- model incorporating the thermo- Metzger, NREL; Gang Xiong, First voltaics, ranging from fundamentals dynamic limit, etendue expansion, Solar; and Xuanzhi Wu, Advanced to applications, with an emphasis on parasitic losses, and non-radiative Solar Power Inc. The panel discussed material science, devices, systems, recombination, as well as ideal and some of the recent research direc- solar resources and policy related realistic back reflectors. In exploring tions and challenges to CdTe and matters. To give readers insights on the design space, for energy restrict- CIGS systems. This ranged from the conference’s vast program, this ing optical coatings, no advantage both device design and materials Technical Brief provides an overview (versus simple detailed balance re- science parameters such as Ag and of the conference highlights by area. sults) was seen for band gap ener- S alloying, dopant activation, and For more detailed information, the gies greater than 1.35 eV. Below that bandgap engineering, to manufac- full proceedings are currently avail- value, improvements are possible turing considerations including im- able on IEEE Xplore. which was described comparing en- proving large area uniformity and ergy restriction and angle restriction. efficient material utilization. To fur- Area 1: Fundamentals and Matthew M. Wilkins (University of ther advance understanding, and New Concepts for Future Ottawa) presented an extended talk improve manufacturing, new non- Technologies identifying optimal band gaps for destructive high throughput char- Shanhui Fan (Stanford University) non-ideal intermediate band (IB) solar acterization methods are needed to gave the plenary on the thermody- cells. Here, a new figure of merit for determine band alignment, carrier namics of light and implications for material quality, ν, is introduced that density, recombination velocity, and harvesting solar energy using the depends on a product of absorption intra-grain potential fluctuations. coldness of the universe utilizing and diffusion length. Simudo, a drift With more data, we can better un- nighttime radiative cooling. This ef- diffusion model for IB devices was derstand e.g. disorder impact on

fect was demonstrated experimen- made and used to explore the perfor- VOC, and provide insights on how to

tally using SiO2 and HfO2 dielectric mance function of ν versus material engineer solutions. However, this layers. When exposed on a roof- band gap. The conclusion was that ν also requires improved theoretical top, the sample temperature falls should be greater than 3.5, and bulk understanding of defect chemistries, by as much as 5 °C below ambient band gaps should target 2.2 to 3.2 eV phase segregation, and the effects air temperature, which has implica- for optimal efficiency. David K Ferry of extended defects. Specifically: for tions for closed loop water cooling (ASU) discussed hot carrier solar CIGS, more work is needed to un- for air conditioning applications. Dr. cells using valley photovoltaics. The derstand density of states in alkali- Fan also discussed the concept of a authors suggest taking advantage of doped alloys; and for CdTe, dopant/ thermoradiative generator. In nor- known characteristics of hot carriers impurity interaction and (de)activa- mal conditions, a PV diode gener- in semiconductors and utilize devices tion mechanisms.

22 IEEE Electron Devices Society Newsletter ❍ January 2021

28neds01_Final_DigitalOnly.indd 22 1/20/21 11:15 AM Xuanzhi Wu (Advanced Solar Pow- to maximize indoor light by shift- low 100 °C. The proposed system was er, Inc.) discussed building integrated ing off the micro CPV, and diffusing demonstrated using single junction PV. Building energy use makes up the sunlight through. The European InGaAs and GaAs devices sourced 28% of all energy consumption, mak- Hiperion project pilot production from NREL. Peak efficiencies of 30%

ing it a major contributor to CO2 emis- line, along with Insolight, is inves- (1300 °C, InGaAs) and 31% (2330 °C, sion. CdTe is an excellent candidate tigating highly efficient hybrid CPV/ GaAs) TPV were shown. for BIPV, from its low temperature PV modules across countries and coefficient, long lifetime (vs architec- industry. 36.4% efficiency at 180x Area 4: Silicon Photovoltaic tural structures) and 19% efficiency suns under real outdoor conditions Materials and Devices allowing cost effective power less was demonstrated. In Area 4 ‘Crystalline silicon PV tech- than $0.25/W. It can be made black Felix Predan (Fraunhofer ISE), a nology’ Gabriela Bunea of GAF En- as an external element, or semitrans- student award finalist, presented on ergy gave the plenary presentation. parent, allowing more architectur- a 4-junction wafer bonded GaInP/ In her speech entitled ‘It is time to ally interesting colors and patterns GaAs/GaInAs//GaSb device with a integrate roof & solar’ she showed with several examples shown. Amit concentrated efficiency of 43.8%. The inspiring examples of how the roof- Munshi from Colorado State Univer- ideal bandgap combination presenting business and PV business can be sity discussed use of a cosublimator ed here (1.9 eV/1.4 eV/1.0eV/0.7eV) merged. She shared the companies’ system for incorporating CdSeTe:As has a potential for a 64.5% detailed experiences and vision on bringing material near the rear of the structure balance efficiency at 500x taking into elegant, roof integrated solar op- CdSeTe devices. With some model- account expected radiative limits in tions to the American homeowners.

ing, an implied VOC > 980 mV was pre- each junction. Device EQE showed The company uses a 60-cell, 360-watt

dicted, with a VOC of 1.0 V within reach current densities over 12 mA/cm² in laminate from Solaria with a custom with poly CdTe devices. Andrea Cat- each sub-cell. Based on simulations, frame that allows it to be waterproof toni (CNRS) presented on ultrathin with some modifications/optimiza- with a lower profile and faster instal-

CuInGaSe2 solar cells with reflective tions, a 50.8% efficiency device is lation. This combined installation back contacts incorporating ITO with within reach. Wondwosen Metaferia benefits from having only one crew ZnO diffusion layer. This structure (NREL) gave an extended talk on the for both roofing and integrated PV to enabled a 29.5 mA/cm2 experimen- incorporation of Al in NREL’s dynamic realize lower system costs. tally with 32.8 mA/cm2 expected from hydride vapor phase epitaxy (HVPE) Many presentations focused on simulation. Further simulation incor- system. So far, GaInP devices suffer oxide/polysilicon passivation con-

porating light trapping using TiO2 na- because the necessary window ma- tacts in area 4 showed that this is noimprint predicts 37.2 mA/cm2 using terials (Al-containing) have not been currently the hot research topic in a 300 nm CIGS absorber with over possible due to reactivity of AlCl. the crystalline silicon PV field. A nice

20% efficiency. Here, AlCl3 was presented as an alter- example among these contributions native and used to grow AlGaAs. As is the research from IMEC Belgium Area 3: Multijunction and a front surface field (FSF) for a GaAs presented by Sukhvinder Singh. His Concentrator Technologies solar cell, it yielded similar external work aims at the development of the Ignacio Antón (Universidad Politéc- quantum efficiency to a GaInP FSF. building blocks for the integration of nica de Madrid) gave the plenary on While there are still improvements polysilicon-based passivating con- static concentrator modules with in- to make, this previously “practically tacts in co-plated n-PERT solar cells. tegrated tracking for area-constrict- impossible” method has now been Singh showed that both n-poly and ed PV applications (e.g. building proven possible. Finally, the first re- p-poly layers could be simultane- integrated (BI)/charging stations). port of Al-phosphide growth by HVPE ously achieved by the sintering of i-

Using micro multi-junctions and flat up to 2.62 eV was presented. Tarun poly layers during the POCl3 diffusion panel form factor, internal tracking is Narayan and Leah Kuritzky (Antora and the autodoping from an existing possible using displacement of only Energy) presented a world-record B-doped emitter, respectively. State a few mm. This extends effective op- demonstration of a >30% thermo- of the art dark saturation current tical acceptance angles possible with photovoltaic (TPV) device. Antora density values with very high unifor- conventional CPV systems which Energy is working towards higher mity were measured for n-poly, auto can be further integrated into hybrid heat systems to act as batteries by doped p-poly, and boron emitter. The modules with diffuse capture by sili- electrically heating carbon blocks up viability of a laser oxidation process con below the CPV. A further alterna- to temperatures > 1100 °C at the MW to pattern the front p-poly Si layer tive (CPV with no diffuse collection scale. Heat energy is discharged us- without measurable damage was mechanism) allows transmission of ing TPV, which are water cooled to demonstrated. Finally, a laser abla- diffused sunlight, and is adjustable maintain operational temperatures be- tion and plating process leading to a

January 2021 ❍ IEEE Electron Devices Society Newsletter 23

28neds01_Final_DigitalOnly.indd 23 1/20/21 11:15 AM very low specific constant resistivity boron doped Cz that is removed after (EL) images for end-of-line binning was demonstrated. degradation. This trap appears to act of full and half cells. A data set of The strength of the IEEE PVSC as a precursor for the BO defect as it 20,000 EL images, with associated conferences is the solid base of fun- is removed at the same rate as the BO IV curves, was used to train a con- damental research presented, even defect is generated. volutional neural network to bin de- in an area that covers a mature and vices by efficiency bins with actual commercially dominant technology Area 5: Characterization vs predicted accuracy with an R² of as c-Si PV. A nice example was the Methods over 0.9. work presented by Rachel Woods Teresa Barnes (NREL) gave the ple- from UC Berkeley on novel selec- nary presentation on DuraMAT, a Area 6: Perovskite and tive carrier contacts. Her work was research consortium focused on Organic Solar Cells focused on exploring wider band precompetitive research needs in Next to offering the tutorial on gap materials to reduce parasitic ab- module packaging incorporating perovskite PV technology, Mike Mc- sorption of the front contact of sili- four core national labs (NREL, San- Gehee gave a nice presentation on con heterojunction (SHJ) solar cells. dia, Berkeley and SLAC) along with the current status and challenges of When choosing such a material, hole university and industry researchers this exciting PV technology in Area 6. mobility and valence band (VB) off- and an industrial advisory board. He discussed the progress at devel- set with crystalline silicon (c-Si) are Degradation rate vs time has many oping both low and high band gap often used as starting criteria, but components, some may be recov- perovskites for tandem solar cells. several other material parameters erable (PID), some factors may fall Both highly stable low band gap can also influence band bending at off quickly at startup and level off cells with greater than 19% power the contact interface. Rachel applied (LeTID), and some may be unre- conversion efficiency and triple ha- a combination of simulation and ex- coverable (cracks). Failures missed lide high band gap cells with >20% periments to suggest future p-type by current tests include backsheet stability that do not suffer from carrier-selective contacts and a bet- cracking, potential induced degra- light-induced phase separation have ter understanding of materials selec- dation, grid finger corrosion and been realized. In addition, McGehee tion criteria in SHJ cells. She found delamination, light and elevated presented fundamental insides on a strong influence on fill factor from temperature induced degradations, high band gap perovskites: if Br is thickness, doping, and valence band snail trails, and delamination. Dura- used to shrink the lattice, a signifi-

position, and on VOC from surface MAT resource consists of core areas: cant amount of Cl can be incorpo- defect density. Multi-parameter sen- central data resource; multi-scale, rated. Cl helps raise the band gap, sitivity analyses demonstrate that multi physics modeling; field mod- passivate defects and improve mo- higher valence band offsets can be ule forensics; disruptive acceleration bility. Overcoming the self-limiting tolerated at higher dopings. These science; and module material solu- redox reaction between an interface findings were demonstrated using tions. This work utilizes “big data” of NiO and perovskites, the adding SHJ cells with a hole selective con- and high performance computing of a few percent excess of Al was

tact of p-type NiOx, an underexplored methods to better develop acceler- presented to prevent the formation

material for SHJ. ated tests, understand the results, of PbI2. In addition he shared the re- Another nice example of funda- identify failure modes, and under- sults on perovskite-Si tandems with mental research was the presenta- stand materials to speed up the >27% efficiency and all-perovskite tion of Sam Jafari from UNSW in learning cycle. Oki Gunawan (IBM) tandems with >23% efficiency. This Australia. He reported on his new gave an extended oral presentation was an excellent introduction to the insights related to the boron-oxygen on the carrier-resolved photo-hall ef- various hybrid multi-junctions as (BO) related light-induced degrada- fect, utilizing a rotating dipole line discussed in great detail in the joint tion of boron-doped Czochralski (Cz) system for camelback potential carri- session between Area 3, 4 and 6 silicon solar cells. This study higher confinement. Using lock-in ampli- entitled ‘Battle Royale on Hybrid Tan- lights the fact that despite decades fication and Fourier transforms, it is dem Solar Cells’. of LID-related research, new insights possible to characterize a wide range can be obtained when using new ap- of parameters including recombina- Crosscutting: Battle Royale on proaches, such as those presented in tion lifetime, diffusion length (minor- Hybrid Tandem Solar Cells this paper. He presented his finding ity and majority), as well as carrier Marko Jost (University of Ljubljana, of a transformation between minority type, mobility, and density from a Helmholtz-Zentrum) discussed a carrier trapping and recombination single tool. Yoann Buratti (UNSW), 1.68 eV perovskite/CIGS tandem. A active centers. A minority carrier trap a student award finalist, discussed Fraunhofer certified 24.2% efficiency was revealed in the annealed state of deep learning of electroluminescent was shown, a record for this material

24 IEEE Electron Devices Society Newsletter ❍ January 2021

28neds01_Final_DigitalOnly.indd 24 1/20/21 11:15 AM system! To further characterize this, transparency over 80% may lead to Area 7: Space and as well as understand long-term an efficiency of 27.4%. Specialty Technologies stability, a 2-color led light source at Jason Yu (ASU) discussed blade- James Kinnison (John Hopkins Uni- 470 nm and 940 nm was developed. coated perovskites on textured sili- versity Applied Physics Laboratory) This allows individual biasing of Si con, built on ASU’s development of gave the plenary on the Parker Solar or CIGS bottom cells to investigate fully textured tandems, using a so- Probe mission, which just completed the top perovskite, and vice versa, lution processed perovskite instead its 5th encounter with the sun. Origi- using full IV curves under different il- of vacuum deposition for improved nally proposed in 1958, after 50 years lumination levels. Examining optical manufacturability. Wet etching was of concepts the current mission, optimization on Si or CIGS bottom used to develop sub-micron sized previously known as “Solar Probe cells, the top perovskite cell require- pyramids on the Si surface, followed Plus”, it measures the properties of ments are the same (thickness, Eg), by a blade coating process to apply the solar corona, the acceleration and both systems allow efficiency PTAA and perovskite. The effects of in- of the solar wind, and mechanisms gains over non-tandems. Incorpo- cluding DMSO were presented which that create the solar energetic par- rating insolation and weather data, can limit voids in the final morphol- ticle environment. The spacecraft a Si-tandem is predicted to perform ogy if included in the correct propor- requires a substantial heat shield, 6% lower than CIGS. tions. A textured PDMS top structure which shadows the majority of the Frank Dimroth (Fraunhofer ISE) was also used to reduce reflectance. components. The PV are some of presented a wafer-bonded 34.1% Finally, a 26% tandem device using the only components directly facing GaInP/AlGaAs//Si tandem incorpo- these features was demonstrated the Sun. To maintain operation near

rating a nanostructured resist with with JSC matched at over 19 mA/cm². 150 °C, the PV panels were mounted silvered back layer for increased Daniel Lepkowski (OSU), a stu- on an electrically isolated, thermally absorption in the Si substrate. Im- dent award finalist, discussed strate- conductive ceramic, which was wa- provements from previous designs gies for >23% GaAsP:Si tandem by ter cooled. The arrays split into two included a rear heterojunction top MOCVD. Recent devices have shown sub-sections on movable flaps, a cell, and AlGaAs for middle cell in- 23.35% efficiency (NREL certified), primary one which is completely stead of GaAs for better current which is a 10% absolute improvement shaded at closest approach, and a matching. Two methods were investi- from the first demonstration of this sys- smaller secondary one which gets gated: in the first one, a top tandem tem 5 years ago. Experimental results glancing incidence irradiation. When was grown inverted, then flipped, of test structures were fit, and used to near Venus, the flaps are extended bonded to Si, and the GaAs substrate understand the effects of threading for complete illumination. Now, 2 was removed. For the second meth- dislocations density on performance. years into the mission, performance od, the upper tandem was grown up- Very recently, a GaAsP top cell was is exceeding expectations. This mis- right on GaAs, then bonded sapphire grown with a TDD of 3 5 106 cm−², sion has returned some impressive handle, after removal of the GaAs projecting 1.27 V at 18.5 mA/cm². Us- data on turbulent coronal flow out substrate and CMP, the Si bottom cell ing this relationship, it is reasonable from the Sun, as well as other infor- was bonded and the sapphire handle to expect efficiencies of >27% for this mation about the solar environment was removed. Across wafer uniformi- device once fabricated. not possible to observe without be- ty was better in method 1, but better Tony (Shizhao) Fan (UIUC) pre- ing up close. champion devices were obtained in sented a 25.0% GaAsP/Si tandem by Bao Hoang (Maxar Infrastructure) method 2. MBE. Using a similar structure to the discussed orbit raising to GEO us- Saba Gharibzadeh (KIT), a student previous talk, this work focused on ing electric propulsion which allows award finalist, discussed perovskite reduction of threading dislocations for an 8x increase in specific impulse based tandems as a path towards and dark line crystal defects as moni- versus bulky chemical propellants on 35% efficiency, focusing on voltage tored by EBIC in the 1.7 eV GaAsP board, at the cost of extended time loss, reducing non-radiative recom- top cell. Through incorporation of a spent in high-radiation belts dur- bination, and improving surface pas- non-optically active GaAsP spacer ing this transit. This was simulated sivation. Utilizing a 2D/3D perovskite between the metamorphic grade and against several approaches (super-

heterojunction, a stable VOC of up to active layers, as well as an AlGaAsP sync and sub-sync ) using a variety of 1.31 V was shown. A full 4-terminal BSF instead of GaInP, a reduction in models (AE8, AP8, and IRENE (AE9/ tandem with a Si bottom cell dem- defects was shown at the cell level, AP9)) to predict on-orbit performance onstrating 25.7% stabilized efficien- resulting in a 25% efficient device and degradation of solar cells. Ste- cy was demonstrated, beating the now. A near term 27% efficiency was phen Polly (RIT) presented on the standalone Si cell. Using an alterna- predicted through optimizing device integration of a longpass distributed

tive ITO/IZO system for improved doping to further boost VOC. Bragg reflector ((LP)DBR) below the

January 2021 ❍ IEEE Electron Devices Society Newsletter 25

28neds01_Final_DigitalOnly.indd 25 1/20/21 11:15 AM middle junction of an inverted meta- The conductive back contact system at large scale. A building geometry morphic triple junction for improved had 2.5% more energy production in was modeled to make the most effi- radiation tolerance and lattice match- Las Vegas (high irradiance, hot day), cient use of light throughout the year, ing. The LPDBR suppresses parasitic with 2.7% increase on annualized using a polyomino approach which sub-gap reflectance, and a wide range basis. This was partially from lower generates Tetris-like shapes which of device designs (DBR, LPDBR, sub- temperature, partially from better can be easily interconnected with cell thickness) were simulated in Syn- low light performance. In Boston neighbors and build into large stan- opsys Sentaurus, ultimately showing (lower temperature, lower intensity) dard grids. With the Fraunhofer ISE efficiency gains for a thin device in- there was 4.3% more production on main building as a test-case, model- corporating equivalently thick LPDBR the best day and 3.1% better annual- ing single string layouts, landscape vs a traditional DBR. Justin Lee (The ized for the conductive back contact layouts, portrait layouts and polyomi- Aerospace Corporation) discussed device, showing improvements in no defined layouts, as much as 2.9% on-orbit results from the AeroCu- multiple environments. improvement in performance was be-10 experiment, for quantitative Ian Slauch (University of Minneso- shown for the polyomino design. This comparison of solar cell degradation ta) discussed modeling spectrally-se- paper was awarded the best student measured in situ against modeled, lective reflection in bifacial modules presentation in Area 8. data-driven predictions. It uses a so- to reduce parasite absorption. Using lar cell matrix of varying coverglass an idealized case of reflecting 1200 nm Area 9: PV Modules and thicknesses, dosimeters, and a mi- and longer, >3 °C cooling is possible System Reliability cro charge particle telescope. Early for an Al BSF cell, and slightly less for Arathi Gopinath (Nextracker) gave results show a wide range of data of PERC. Realistic mirrors can give 2% the plenary, discussing reactive ver- space environment and solar cell per- more energy and operate 1.5K cool- sus proactive operation and mainte- formance, including the 2019 Labor er using realistic stacks of dielectric nance modalities in the age of mass Day storm. This experiment is return- materials. For bifacial, up to a 3.9K solar deployment. Weather related ing lots of data, and more in-depth temperature reduction is possible events are the number one source analysis and application to on-orbit depending on irradiance conditions. of PV insurance claims, which is modeling is still to come. Keith McIntosh (PV Lighthouse) pre- only increasing due to global climate sented on simulation and measure- change. With a goal of 100% up time, Area 8: PV Modules Manufactur- ment of mono- and bifacial modules preventative maintenance, and the ing and Applications in a 1D tracking system using a test- prediction for the need of that main- Itai Suez (Silfab Solar) gave plenary ing array in Albuquerque, NM. Sun- tenance is critical. Nextracker utilizes on the emergence of back-contact Solve was used for simulation, using a wide range of data sources for electro-conductive back sheets. This 3D ray tracing (to account for e.g. tracking PV systems, which provide technology provides structured con- frames), a SPICE model, along with visibility of how a plant is operating, nections to any back-contact cell the same temperature modules used provide insights to understand failure technology, and enables the highest by PVSyst. Simulations showed and mechanisms, and enable foresight power density of any current model- identified sources of non-uniformity into predicting failures well before ing technology, including shingling, in current generation. Silvana Ayala they happen to maximize uptime. by very close packing of cells without Pelaez (NREL) discussed a field-array Dirk Jordan (NREL) presented wires or ribbons. A lower tempera- benchmark of commercial bifacial a detailed analysis of temperature ture interconnect process than typi- PV technologies using publically and installation effects of PV system cal soldering, it also reduces thermal available data from a 75 kW single failures from fleet performance of expansion mismatch between com- axis tracking array at NREL. Results 100,000 PV systems across the US. ponents, leading to higher reliabil- show that the SHJ performs best in These data enable understanding of ity as demonstrated with dynamic the summer when it can run cooler, rates of various hardware faults such mechanical load, thermal cycling PERC operated best in the winter with as inverter, breaker, wire, ground fault testing, and humidity freeze/thaw cy- higher albedo from snow with the etc., all broken down by scale (resi- cling results. These modules also run added benefit that bifacial modules dential, commercial, utility). A major cooler due to the larger lateral con- power during cloudy snowy days find was inverters have significantly ductive area for heat spreading of when monofacial do not. Sanghyuk lower failure rates when installed in foils versus traditional polymers. To Lee (Korea Polytechnic University) in- shaded positions. The good news is quantify this, two identical systems troduced us on how to use Tetris as most systems perform as expected, (modules, racking, fixed tilt angle, a new approach to automated con- within 80–90% of their predicted val- etc.) were simulated in PVSyst at two figuration and interconnection lay- ue. Xiaohong Gu (NIST) introduced locations, Las Vegas, and Boston. outs for building integrated modules a method for predicting long term

26 IEEE Electron Devices Society Newsletter ❍ January 2021

28neds01_Final_DigitalOnly.indd 26 1/20/21 11:15 AM performance of PV backsheets, link- work to do to exceed the detailed steel, aluminum, and pulp and paper;

ing lab-based experimental exposure balance limit and realize the impact most of these CO2 emissions can be with outdoor service performance. of third-generation, tandem, and III-V eliminated or entirely re-captured. This work focused on the PET outer technologies. TW scale has new chal- layer, exploring UV (various wave- lenges, which need to be addressed, Special Session on Hot Carrier lengths), temperature, and humidity including how to deal with PV waste, Solar Cells: Current Status and exposure. Damage from carboxylic material availability, Ag reduction/ Bottlenecks acid formation and yellowing in- replacement and PV recycling? We Ian Sellers (University of Oklahoma) creases as UV photon energy increas- need sustainable growth models. moderated a panel (Gavin Conib- es. Humidity does not act alone as a At the grid-level, small scale (island) eer, University of New South Wales; damage factor, but enhances damage 100% RE is possible and currently Stephen M. Goodnick, Arizona State caused by UV. This was used to cre- demonstrated, but more difficult at University; Jean Francois Guille- ate a predictive model, which shows larger scale. There is a need for bet- moles, IPVF, France; Louise C. Hirst, a close match to data from Arizona, ter stability with inverter-based re- University of Cambridge; Art Nozik, with further granularity in humid- sources, better instantaneous power University of Colorado/NREL) to ity data is needed for matching data delivery, and storage such as batter- discuss progress and challenges to from Florida and Maryland data. Nick ies, pumped hydro and solar fuels. the hot carrier solar cell concept, a Bosco (NREL) gave an extended talk Next, Marta Victoria (Aarhus Uni- mechanism to reduce thermalization on multi-scale modeling of electrical- versity) discussed the synergy with loss by capturing energy from pho- ly conductive adhesive interconnects wind and solar towards decarbon- tons with energies well in excess of for reliability testing. These intercon- ization. Marta presented a model the material band gap, normally lost nects are used to bond and connect incorporating energy storage, trans- to photons. This technology has the cells in shingled modules. Traditional- mission, and sector coupling to bal- potential to more than double the ly used maximum stress theory is too ance cost and capabilities across ~30% detailed balance limit to over general for this case, so an alterna- Europe. The model contrasted the 60% efficiency. Panelists discussed tive approach of strain energy release geographic preference for PV and the importance of fundamental re- rate was used to model cohesive and battery storage in southern countries, search, and how carrier and phonon

adhesive failures. Determining an ac- with wind and H2 storage in northern interaction keeps revealing itself to curate stress-free temperature is criti- countries. Keiichi Komoto (Mizuho be more complicated as it is inves- cal, allowing strain to return to initial Research Institute) discussed decar- tigated. While particular material minimums after simulated tempera- bonizing transport. Approaches must systems may come into play for cost ture changes. 3D simulations were consider the source PV generation, effectiveness or manufacturability used to find areas of most interest, the end-use in an electric vehicle (EV) (CIGS, Si, perovskites) hot carrier which defined boundary conditions battery, and transfer through any in- concepts are not necessarily com- for 2D sub-models to explore debond termediaries such as the grid, stor- peting, but can be a complimentary driving force versus growth rate, sav- age, and charging stations. Matthew aspect of these devices. The panel ing computational time. Stocks (Australian National Universi- discussed the two ways hot carriers ty) explored decarbonizing the urban can be used, through carrier selec- Area 10–12: Towards 100% Re- environment using renewable en- tive contacts to extract high voltage, newable Energy Special Session ergy. Energy demands of cooling (air or through multiple exciton gen- Nancy Haegel (NREL) gave the plena- conditioning) dominate within +/- 35 eration that creates more current ry on trajectories and challenges to degrees latitude, which encompasses through an impact-ionization like TW scale electricity generation with 70% of the world population. More process. Topics flowed from valley PV. With total energy average power effort is required in suitable seasonal scattering as a mechanism of slow- of 18.4 TW in 2018, 3.0 TW was elec- storage mechanisms. Christian Brey- ing down carrier relaxation through tricity, and 0.066 TW (2.2–2.5% ) was er (LUT University) discussed decar- bandgap engineering, to thermo- PV. Utility scale LCOE is competitive bonizing industrial processes which electric devices and how they re- now vs traditional sources around account for 27% of all greenhouse late to hot carrier devices. The panel the world, citing US, Germany, and gas (GHG) emissions, and in most of closed on the topic of materials, in- Japan. Further recent work looking the specific sub-sectors; substitutions cluding nitrides, hydrides, anisotro- at 100,000 systems in the United are possible to eliminate GHG using pic materials, and on developing a States, says that most perform as “power-to-x” converting electricity to “new concepts in PV” roadmap and expected, showing a highly reliable hydrogen, fuels, and feedstocks. This round-robin testing of materials be- product. Progress in efficiency and led to a deeper dive on specific in- tween labs. Finally, a challenge was reliability is working, but there’s still dustries: chemical, cement, iron and put to the community to produce hot

January 2021 ❍ IEEE Electron Devices Society Newsletter 27

28neds01_Final_DigitalOnly.indd 27 1/20/21 11:15 AM carrier devices able to participate in The authors acknowledge the the Si-tandem Battle Royale! full Program and Organizing Com- mittees of the PVSC-47, for bringing Closing Remarks together this virtual conference in a While the normal roster of social very short period of time! Without events and activities planned for such a dedicated team, the PVSC Calgary were put on hold this year, would not be possible. We also we were still able to hold the signa- thank the many authors and pre- ture Sun Run 5K race virtually! Par- senters who chose to present their ticipants all ran a 5K in their home outstanding work at PVSC-47, de- locations during the 1st week of the spite the difficult times. Next year conference and sent in their official the PVSC will be held at the Diplo- times. Congratulations to all of this mat Beach Resort near Miami, Flori- year’s participants, a summary of da from June 20–25, 2021. the event can be found at the PVSC- 47 website. As well, this year marks This article was prepared by Dr. the 40th year of the Sun Run, all Stephen Polly, the PVSC-47 Daily thanks to Dr. Larry Kazmerski, who Highlights Coordinator, Dr. N.J. Ek- has been organizing this event at the ins-Daukes, PVSC-47 Assistant Daily PVSC since 1980. On behalf of all the Dr. Larry Kazmerski has been or- Highlights Coordinator, Dr. Arno PVSC community, thank you to Larry ganizing and hosting the PVSC Sun Smets, the PVSC-47 Technical Pro- for organizing, hosting and bringing Run since its inception in San Diego gram Chair, and Dr. Seth Hubbard, so much fun to the PVSC!! in 1980! the PVSC-47 Conference Chair.

REVIEW OF THE 2020 IRPS BY BEN KACZER

The IEEE International Physics Reli- starting on April 28 and running until Sensors, and Aging Aware Designs), ability Symposium (IRPS) has been May 30, 2020—the duration of which Wide Bandgap Devices (with empha- the premiere conference for engi- the recorded presentations were ac- sis on the Reliability of SiC Devices), neers and scientists to present new cessible to the registrants. The vir- Reliability issues of Neuromorphic and original work in the area of mi- tual event was attended by more Computing, and Reliability of RF/ croelectronics reliability for almost than 400 participants. mmW/5G Devices (CMOS, SiGe BiC- 60 years. Drawing participants from The conference encompassed a MOS, SOI, GaAs). the United States, Europe, Asia, and wide range of topics, ranging from Cir- The conference opened tradition- all other parts of the world, IRPS cuit Reliability and Aging, Emerging ally with two days of Tutorials, which seeks to understand the reliability of Memory Reliability, ESD and Latchup, allowed both newcomers and ex- semiconductor devices, integrated Failure Analysis, Gate/MOL Dielec- perts to familiarize themselves with circuits, and microelectronic systems trics, IC Product Reliability, Memory new topics or just to refresh their through an improved understanding Reliability, Metallization/BEOL Reli- existing knowledge. The Tutorial of both the physics of failure as well ability, Neuromorphic Computing instructors are authorities in their as the application environment. Reliability, Packaging and 2.5/3D As- respective reliability fields—either The 2020 IRPS was originally sembly, Process Integration, Reliabil- veteran IRPS presenters for estab- scheduled to be held at the Hilton ity Testing, RF/mmW/5G Reliability, lished topics or invited specialists DFW Lakes Executive Conference Soft Error, System Electronics Reli- in emerging topics. The first two Center, Dallas, TX, between March ability, Transistor Reliability, to Wide- tracks of “Basics of Semiconduc- 29 and April 2, 2020. Due to the Bandgap Semiconductors- GaN. The tor Reliability” included Basic Reli- COVID-19 pandemic, the conference 2020 Special focus topics were Cir- ability Physics, Bias Temperature had to be converted to a virtual event cuit Reliability and Aging (EDA Tools, Instabilities, Self-heating, Terrestrial

28 IEEE Electron Devices Society Newsletter ❍ January 2021

28neds01_Final_DigitalOnly.indd 28 1/20/21 11:15 AM Radiation, Plasma-Induced Damage, uted submissions. Due to the virtual • T. Uemura et al., Samsung Elec- Electromigration, and Materials nature of the conference, the papers tronics—Investigating of SER in Analysis Techniques in Semiconduc- were typically presented as prerecord- 28 nm FDSOI-Planar and Com- tors. A track of Tutorials on “Memo- ed video clips. Poster presenters were paring with SER in Bulk-FinFET ry Reliability” included the topics of allotted limited time to introduce their • Heung-Kook Ko et al., Samsung Charge Trap Memories, MRAMs, and work and, to emulate the poster ses- Electronics—Early Diagnosis and Phase Change Memories, and was sion experience, they could discuss Prediction of Wafer Quality using followed by “Power Devices Reliabil- their work with interested audience Machine Learning on sub-10nm ity” Tutorials on GaN Power Devices, members in separate video calls. Logic Technology and Power IGBT Modules. The last Unfortunately, some popular • Hai Jiang et al., Samsung Elec- Tutorial track on “Circuit & System events, such as the evening IRPS tronics—Advanced self-heating Reliability” covered the Introduc- Workshops and a lunch Panel were model and methodology for tion to RF and Mixed-Signal Circuit cancelled due to having to convert layout proximity effect in Reliability, Designing for Analog the conference relatively abruptly to FinFET technology Reliability, and BTI-HCD Reliability the virtual format. • Huimei Zhou et al., IBM—NBTI Framework. The IRPS subcommittees high- Impact of Surface Orientation The Tutorials were followed by lighted the following contributed in Stacked Gate-All-Around Year-In-Review, a segment always ap- papers: Nanosheet Transistor preciated by IRPS attendees, allowing • C. Prasad et al., Intel—Silicon Re- • Sandeep R. Bahl et al., Tex- them to quickly catch up on recent de- liability Characterization of Intel’s as Instruments—A General- velopments in multiple areas. In this Foveros 3D Integration Technolo- ized Approach to Determine the year’s Year-in-Review several speak- gy for Logic-on-Logic Die Stacking Switching Lifetime of a GaN FET ers covered the past year of literature • E. Landman et al., ProteanTecs— • M. Sampath et al., Purdue Uni- on Circuit Reliability, including the A novel approach to in-field, in- versity—Constant-Gate-Charge EDA aspects, RF/mmW/5G Reliabil- mission reliability monitoring Scaling for Increased Short- ity (CMOS/SiGe and GaN HEMT) and based on Deep Data Circuit Withstand Time in SiC Memory Reliability. • T. Grasser et al., TU Wien—The Power Devices The conference proper started Mysterious Bipolar Bias Temper- After the conference, the following with a live welcome address by ature Stress from the Perspective Awards were announced: the General Chair Prof. Gaudenzio of Gate-Sided Hydrogen Release • Best Paper: Yiming Qu et al., Zhe- Meneghesso, University of Padova, • J. B. Roldan et al., Universidad jiang University—In-Situ Mon- Italy, and an Overview of Technical de Granada—Reversible dielec- itoring of Self-Heating Effect in Program by the Technical Program tric breakdown in h-BN stacks: a Aggressively Scaled FinFETs and Chair Dr. Charles Slayman, Cisco Sys- statistical study of the switching Its Quantitative Impact on Hot tems, USA. The subsequent Plenary voltages Carrier Degradation Under Dy- Keynotes were • Yao-Feng Chang et al., Intel— namic Circuit Operation • Dr. Mike Mayberry, Chief Tech- eNVM RRAM reliability perfor- nology Officer, Intel, USA—The mance and modeling in 22FFL Future of Compute: Reliability FinFET technology and Resiliency in the era of Data • T. Y. Lee et al., GLOBALFOUND- Transformation RIES—Magnetic Immunity • Dr. Oliver Häberlen, Senior Prin- Guideline for Embedded MRAM cipal, Infineon Technologies, Reliability to Realize Mass Pro- Austria—Power Semiconductor duction Reliability—An Industry Perspec- • Tae-Young Jeong et al., Samsung tive on Status and Challenges Electronics—Reliability on EUV • Dr. Gianluca Boselli, Analog ESD Interconnect Technology for 7 nm Self-heating effect (SHE) in aggressively Lab Manager, Texas Instruments, and beyond scaled SOI FinFETs is experimentally and USA—Power scalability challeng- • Yiming Qu et al., Zhejiang Uni- quantitatively investigated by using a sub- es in High-Voltage ESD Design versity—In-Situ Monitoring of nanosecond characterization technique. The bulk of the conference then Self-Heating Effect in Aggressive- consisted of the presentation of 105 ly Scaled FinFETs and Its Quan- • Best Student Paper: A. Kruv et Oral (of which 16 were Invited) and 77 titative Impact on Hot Carrier al., imec—On the impact of me- Poster papers, previously selected by Degradation Under Dynamic Cir- chanical stress on gate oxide 17 subcommittees from 239 contrib- cuit Operation trapping

January 2021 ❍ IEEE Electron Devices Society Newsletter 29

28neds01_Final_DigitalOnly.indd 29 1/20/21 11:15 AM SiC gate-oxide reliability is governed by extrinsic failures due to tiny distortions in the Random Telegraph Noise is used to locate gate-oxide, which act as local oxide thinning. Detrapping from individual gate oxide defects traps during the breakdown process in is studied under externally-applied local me- OxRAM dielectric layer. chanical stress up to ~5 GPa. Next year, IRPS 2021 will be again a virtual event taking place from • Best Poster Paper: E. R. Hsieh et al., • Best Virtual Presentation: March 21 to March 25, 2021. More National Chiao Tung University— T. Aichinger and M. Schmidt, information can be found on https:// A Pulsed RTN Transient Measure- Infineon Technologies—Gate- irps.org/. ment Technique: Demonstration on oxide reliability and failure- the Understanding of the Switch- rate reduction of industrial Ben Kaczer is IRPS 2021 Publicity ing in Resistance Memory SiC MOSFETs Chair and Scientific Director at imec

NEW EDS SERVICE

NEW! EDS Podcasts Available to Everyone!

EDS is pleased to announce our new podcast series. Join us as we host interviews with some of the most successful members of our Society sharing their lives and careers. Their insight and wisdom will be invaluable inspiration and knowledge for those in the engineering field. Stay tuned to our social media channels and website for future announcements on upcoming events.

30 IEEE Electron Devices Society Newsletter ❍ January 2021

28neds01_Final_DigitalOnly.indd 30 1/20/21 11:15 AM U PCOMING T ECHNICAL M EETINGS

5TH IEEE ELECTRON DEVICES TECHNOLOGY AND MANUFACTURING (EDTM) CONFERENCE 2021 MARCH 9–12, 2021, THE CENTURY CITY INTERNATIONAL CONVENTION CENTRE IN CHENGDU, CHINA HTTPS://EWH.IEEE.ORG/CONF/EDTM/2021/

• Reliability Short Courses and Tutorials • Packaging and heterogeneous EDTM 2021 will start with a set of integration short courses and tutorials on March • Yield and manufacturing 9, 2021. Tutorials teach selected top- The IEEE Electron Devices Technol- • Sensor, MEMS and Bio-electronics from the basics to the state-of- ogy and Manufacturing (EDTM) Con- ics the-arts, allowing the attendees to ference 2021 is a four-day meeting to • Flexible and wearable electronics catch up a topic quickly. Short Cours- be held at The Century City Interna- • Nanotechnologies es discuss the latest research and tional Convention Centre in Cheng- • Disruptive technologies—inter- challenges on hot and advanced top- du (China) from March 9–12, 2021. net of things (IoT), artificial in- ics encompassing the EDTM 2021 EDTM is a premium conference telligence (AI), machine learning theme, including heterogeneous in- sponsored by the IEEE Electron De- (ML), neuromorphic & quantum tegration, artificial intelligence (AI) vices Society that provides a unique computing and machine learning (ML), internet forum to discuss and collaborate on World-class researchers in all ar- of everything (IoET), 5G+, autono- a broad range of device/manufac- eas will deliver invited talks, and mous systems, industry 4.0, future turing-related topical areas includ- submissions will be evaluated for computing and quantum informa- ing materials, processes, devices, oral and poster presentation. Authors tion processing, all enabled by elec- packaging, modeling, reliability, and should indicate their preference for tron devices. manufacturing and yield. Since its oral or poster presentation format birth in 2017, EDTM has always been when submitting their abstracts. Important Dates an excellent platform to establish October 25, 2020: Abstracts submis- contact and collaboration with the Publications sion deadline vibrating manufacturing commu- EDTM 2021 papers will be subjected December 20, 2020: Notification of nity. In its 5th edition EDTM will be to IEEE EDS standard review pro- acceptance held for the first time in China, under cesses and IEEE conference publish- the main theme: Intelligent technolo- ing guidelines. The accepted papers COVID-19 Watch gies for smart and connected life. presented at the meeting will be Chengdu remains safe. EDTM 2021 published in the EDTM 2021 pro- is planned as an in-person/on-site Technical Sessions ceedings and may be available on event. Meanwhile, we are closely The EDTM 2021 solicits papers in all IEEE Xplore. Besides, the authors of monitoring the development of types of exploratory device concepts a selected number of high-impact the global COVID-19 outbreak. A within the following broad technical presented papers will be invited to contingency plan will allow virtual areas: submit an extended version of the presentations and participation for • Materials same for the consideration of pub- those with travel restrictions and • Process and tools for Manufac- lication in the IEEE Journal of the concerns. Both safety and participa- turing Electron Devices Society (J-EDS). tion experiences will be ensured for • Semiconductor devices All such submissions must comply EDTM 2021. • Memory technologies with J-EDS author guidelines and • Photonics, imaging and display will be subjected to the standard Mario Lanza • Power and energy devices IEEE and J-EDS review and publica- Soochow University, China • Modeling and simulation tion policy. EDTM 2021 Publicity Co-Chair

January 2021 ❍ IEEE Electron Devices Society Newsletter 31

28neds01_Final_DigitalOnly.indd 31 1/20/21 11:15 AM 2021 IEEE PHOTOVOLTAICS SPECIALIST CONFERENCE (PVSC)

Wenham Young Professional Award for individuals who have made significant contributions at an early stage of their career. We are very excited to host our conference at the Diplomat Hotel, near Mi- ami, Florida. Conveniently located next to both the Miami International Airport and the Fort Lauderdale International Airport, the Diplomat Hotel will offer a convenient location to enjoy both the conference and the surrounding at- tractions, starting with direct access to a private beach, 3 pools, 9 restaurants as well as an Ambassador kids club. As usual with PVSC, we will have a fantastic companion program, with an Everglades National Park tour and alli- gator sightseeing, a riverboat tour, vis- Diplomat Hotel, Bay view its to the beautiful flamingo gardens, and the famous gulfstream racetrack, It is our great pleasure to invite you If you would still like to contribute casino and luxury shopping, as well as to attend the 48th IEEE Photovoltaics technically, please submit your ab- many golf courses. Specialists Conference, which will be stract before our late news deadline The conference Exhibition will held from June 20–25, 2021, at the Dip- on April 25, 2021. showcase the latest developments in lomat Hotel near Miami, Florida, USA. Continuing with the tradition of PV characterization and manufactur- We live at a special time when so- the past few years, the 48th IEEE ing equipment, and is set to further lar electricity has become cost com- PVSC will be divided into 12 technical enhance attendee awareness on latest petitive with conventional electricity areas covering cutting-edge develop- tools and instrumentation as well as in many locations, enabling remark- ments in science and engineering of to facilitate exchange between scien- able growth of the industry. As was photovoltaics, ranging from funda- tists, technical experts and exhibitors. the case in 2019, solar was the biggest mentals to applications, with an em- Don’t miss out on the opportuni- contributor to net expansion of elec- phasis on material science, devices, ties offered by the conference social tricity generating capacity in 2020. In systems, solar resources and policy gatherings and networking events to fact, the IEA PVPS has recently re- related matters. PVSC-48 aims to be get to know your colleagues better, ported that worldwide solar installed a highly interactive venue for both reconnect with old friends and make capacity has now crossed the half TW seasoned PV experts as well as en- new ones. The week kicks off with our mark! The 48th IEEE PVSC will help try-level professionals and students. Exhibitor Reception on Monday eve- sustain this fantastic momentum with The conference provides a unique ning at the Convention Center and hundreds of technical papers from opportunity to meet, share and dis- will conclude with a Conference Re- around the world, reflecting today’s cuss PV-related developments in a ception on Thursday evening. dynamic and expanding markets. The timely and influential forum. Please On behalf of the Organizing, Cher- PVSCs have a rich tradition of bring- consider contributing to PVSC’s tra- ry, and International Committees, we ing together students, innovators, dition as the premier international look forward to welcoming you to the researchers and PV leaders in a vi- conference on PV science and tech- 48th PVSC in Miami, Florida! brant and highly integrative forum to nology and help us propel the world Further details and registration share information, gain knowledge, towards power from the Sun. As can be found at https://www.ieee strengthen collaborations and move well, we will be presenting the pres- -pvsc.org/PVSC48/ forward photovoltaic science and tigious William R. Cherry Award, technology from basic and applied honoring the photovoltaics commu- Sylvain Marsillac research into large scale manufactur- nities’ most outstanding scientist Conference General Chair ing and deployments. or engineer as well as the Stuart R. Old Dominion University

32 IEEE Electron Devices Society Newsletter ❍ January 2021

28neds01_Final_DigitalOnly.indd 32 1/20/21 11:16 AM 2021 IEEE INTERNATIONAL MEMORY WORKSHOP (IMW)

The 13th International Memory Work- and integration, circuit design and re- 3D NAND, DRAM, Embedded memo- shop (IMW) will be held online as a liability, as well as emerging applica- ries, Emerging memories and innova- virtual event from May 16—May 19, tions. Consistent with the increased tion (PCM, RRAM, MRAM, FeRAM…) 2021, due to the outbreak of COVID-19. importance of memory system archi- for storage class memories, data cen- The history of the IMW dates back to tecture and integration, the workshop tric architectures, tremendous growth the NVSMW (Nonvolatile Semicon- also includes increasing coverage of connected objects, and neuromor- ductor Memory Workshop) which be- of the systems in which memories phic memory, quantum computing gan in 1976 and which later merged are deployed and the co-evolution and in-memory computing. The techni- with the ICMTD (International Confer- of memory technology along with cal program is organized to maximize ence on Memory Technology and De- memory systems and applications. networking opportunities and facilitate sign) to become the IMW. The IMW The IMW is the preeminent forum open information exchange among is sponsored by the IEEE Electron De- covering the latest developments, in- workshop contributors, committee vices Society and meets annually in novations, and evolving trends in the members, and attendees. While orga- May. The workshop covers all types memory industry. Typical workshop nized this year as a virtual workshop, of memory technology, is focused attendance exceeds 250 attendees, active participation and discussions will on advancing innovation in memory and the technical program begins with be encouraged by real-time Q&A as technology, and is organized in a way a full day short course given by dis- well as live Panel Discussion Sessions. that provides excellent professional tinguished experts that provides an On behalf of the organizing com- development and networking oppor- excellent professional development op- mittee, I cordially invite you to par- tunities for attendees. portunity for both new and experienced ticipate in the 2021 IMW to continue The IMW is the premier interna- technologists. The single-track technical contributing to the advancement of tional forum for both new and sea- program spans three days and includes innovation in the rapidly evolving soned technologists having diverse an evening poster session for informal memory industry. For additional in- technical backgrounds to share technical discussion with authors as formation, including the call for pa- and learn about the latest develop- well as a panel discussion where ex- pers, key dates, abstract submission ments in memory technology with perts discuss and debate a current hot instructions, registration information, the global community. The scope of topic. The workshop includes invited and technical program details, please workshop content ranges from new talks from industry and research lead- visit the IMW website: http://www memory concepts in early research ers (Key notes in the recent workshops .ewh.ieee.org/soc/eds/imw/. I look for- to the technology drivers currently in were presented by Kioxia, West Digital, ward to e-meeting you in May 2021. volume production as well as emerg- Micron, Applied material, Intel, GLO- ing technologies in development. BALFOUNDRIES, Panasonic, ST Micro, Zhiqiang Wei Topics include new device concepts, IMEC and CEA-Leti,). Tutorial and high- 2021 IMW Publicity Chair technology advancements, scaling light in the recent workshops included Avalanche

JOIN US AT THE LATIN AMERICAN ELECTRON DEVICES CONFERENCE, LAEDC 2021 (VIRTUAL EDITION)

ESTEBAN ARIAS-MÉNDEZ | TECHNICAL ACTIVITIES MARIO ALEMAN | GENERAL CHAIR LAEDC 2021

The third edition of the Latin Ameri- Devices Society (EDS). The last edi- related fields. The conference will be can Electron Devices Conference, tions of the conference were cel- geared to students as well as young LAEDC 2021, will be held virtually ebrated in Colombia and Costa Rica. researchers. Proceedings will be pub- April 19 to 21, 2021. This is a confer- Its main goal is to bring together lished by IEEE and the accepted pa- ence sponsored by the IEEE Electron specialists from all Electron Device pers will be available on IEEE Xplore.

January 2021 ❍ IEEE Electron Devices Society Newsletter 33

28neds01_Final_DigitalOnly.indd 33 1/20/21 11:16 AM The best papers presented at the con- lar energy with its talk: Can Solar PV Invited speakers will complement ference will be considered for publi- save the World? the research papers to be presented. cation in a special issue of the Journal Ravi Todi, Ph.D., Foundry Technol- A poster session will provide the of the Electron Devices Society. ogy Development at Western Digital, first contact to industry and acad- Due to the current pandemic USA; Semiconductor Industry: A sto- emy to many students and young worldwide, all the activities have ry of unprecedented growth and we professionals. been planned to be executed in a are just getting started! Looking forward to seeing you in virtual mode without compromising LAEDC 2021, we invite you to check the quality of the conference and al- General Program includes our official website https://attend lowing a great interaction of the as- .ieee.org/laedc-2021/ and social sistants and sponsors. 18 April MOS-AK workshop media channels for more informa- For this new format, the authors 2021 tion https://www.facebook.com/IEEE are requested to send their video pre- LAEDC. Let us know any question at sentations of accepted papers be- 19–21 Keynote and invited our contact email of the conference fore the event, but they are required April speakers, scientific [email protected] to be online at the scheduled presen- 2021 paper presentations, tation time to check or clarify and an- humanitarian technol- LAEDC 2021 Organizing Com- swer questions. ogy plenary session, mittee student poster pre- • Mario Aleman | General Chair | Distinguish Keynote Speakers sentations, YP & WIE [email protected] Professor David Atienza (EPFL), Pro- session. • Esteban Arias-Méndez | Technical fessor and Director of Embedded Activities | esteban.arias@ Systems Laboratory, École Poly- tec.ac.cr technique Fédérale de Lausanne, Many of us will miss the face-to- • Pablo Moliterno | Web master Switzerland. From IEEE Region 8. face format of the conference and • Arturo Escobosa | Technical Professor Atienza will speak about being able to interact directly. How- Activities Energy-Scalable Many-Core Servers: ever, virtual has the advantage of • Fernando Guarín | Treasurer Follow Your Brain!. offering us reduced prices to partici- • Jacobus Swart | Organizing Professor Martin A. Green, Di- pate and LAEDC 2021 will not be the Committee rector of the Australian Centre for exception. The reduced rates of this • Lluis F. Marsal | Organizing Advanced Photovoltaics, School of edition will allow great participation Committee Photovoltaic and Renewable Ener- of professionals and students. Addi- • Benjamin Iñiguez Nicolau | Orga- gy Engineering, University of New tionally, student scholarships will be nizing Committee South Wales Sydney, Australia; will provided thanks to the collaboration • Luis Procel | Organizing make us think about the future of So- of our sponsors. Committee

34 IEEE Electron Devices Society Newsletter ❍ January 2021

28neds01_Final_DigitalOnly.indd 34 1/20/21 11:16 AM S OCIETY N EWS

BOARD OF GOVERNORS MEETING—DECEMBER 2020

EDS Board of Gov- to join the Newsletter team in Janu- ernors meeting ary 2021. in December was Bin Zhao, EDS Treasurer, present- organized virtu- ed the financial status, reporting a sur- ally due to the plus of $1214K in 2019, 50% of which COVID19 pandem- can be utilized for new initiatives. The ic worldwide. budget for 2020 has been revised due The virtual meet- to the pandemic situation. Both rev- MK Radhakrishnan ing using Webex, enue and expenses have been revised EDS Secretary comprising 3 hours with a substantial reduction in confer- each from 9:00—12:00 US Eastern ences related activities. time on December 12 and 13, 2020. Kazunari Ishimaru, VP of Meetings successfully organized in the midst The meeting was planned to accom- informed that almost all the confer- of the pandemic. As per the L31 re- modate presentation schedules and ences were organized virtually this ports, EDS Chapters had 444 chapter to suit the convenience of the Soci- year. Out of the 17 financially spon- meetings this year. The first ever EDS ety’s global representation compris- sored conferences, 3 were cancelled Global Chapters Summit was orga- ing almost 18 time zones. Almost all and 4 technically co-sponsored con- nized virtually, which was very suc- elected members of the BoG and ferences were cancelled. Most of the cessful with an excellent participation EDS voting Forum members attend- conferences may be organized in hy- from chapters across the globe. ed the virtual meeting on both days. brid format in 2021. Chapter Chairs were able to share EDS President, Meyya Meyyap- Navakanta Bhat, VP of Education best practices and unique issues with pan welcomed all the attendees and informed the successful organization the participants. Based on the suc- informed them that the meeting of 18 webinars in the past 9 months. cess of the first event, the summit will would have presentations by all the The approved summer school probe held regularly in the future. VPs and other officers as scheduled posal will be functional next year. For Patrick Fay, VP for Membership in the agenda. The Q&A was man- 2021, certification and short courses informed that the EDS membership aged by Ravi Todi, President-Elect, programs are planned to build and growth trends are not very attractive with questions and comments sent enhance strong industry connection. and a decline in membership is ob- to him directly by email or Webex EDS Podcast featuring interviews served in almost all Regions except chat. All the motions were present- with illustrious members of our com- Region 9. Undergraduate student ed with the voting to take place via munity will start in 2021 and this will member strength is mostly concentrat- email after the meeting. The pre- be organized by Muhammad Mustafa ed in Region 9 and 10, whereas both sentations were made available Hussain. graduate and undergraduate student through the EDS BoG Agenda link in Joachim Burghartz, VP Publica- memberships are very low in the US. advance, which allowed everyone to tions & Products informed that all He emphasized the need to have con- go through them in advance. High- EDS journals (TED, EDL and JEDS) certed effort to improve the situation. lights of the presentations and delib- are growing in the number of papers After brief discussions on the vi- erations are as follows. submitted and Impact Factor. The ac- ability of extending virtual DL talks, On the first day, December 12, ceptance rate for all three journals re- etc. the meeting was adjourned by Ravi Todi summarized the details of mains more or less the same as in the Meyya Meyyappan. the virtual ExCom meeting held on previous year. The processing time is The second day’s meeting on 13 December 11, 2020. EDS Secretary’s improving for all journals. December 2020 started with the pre- report and Newsletter Status were Murty Polavarapu, VP Regions and sentation by John Dallessase, VP for presented by MK Radhakrishnan and Chapters, reported that EDS has 214 Technical Committees.There are 14TCs the highlights include the selection chapters at present with 5 new chap- and even with the constraints of the of a new Associate Editor-in-Chief for ters in Region 9 and 2 student chap- pandemic situation, the TCs worked the EDS Newsletter, Manoj Saxena, ters in Region 10. Twelve MQs were very efficiently with all TCs participating

January 2021 ❍ IEEE Electron Devices Society Newsletter 35

28neds01_Final_DigitalOnly.indd 35 1/20/21 11:16 AM in various developmental activities journal, showing progress in paper 50% of operating budget funds. Fer- as well as in MQs and DLs. Three TC submission and acceptance. Jesus nando announced the EDS awards Chairs—Benjamin Iniguez, Juzer Vazi del Alamo, Editor-in-Chief of EDL for this year. Robert Dutton was cho- and Claudio Paoloni will be retiring presented EDL status, which shows sen as the EDS Celebrated Member this year and John thanked them for the cycle time for paper accep- and Arokia Nathan received the J. J. their services. tance of EDL as one of the best in Ebers Award. All other awards were Paul Berger, VP Strategic Directions, IEEE publications. Enrico Sangiorgi, also announced. The results of the presented a plan for EDS strategic di- Editor-in-Chief of JEDS, informed BoG election held via online / email rectives to oversee future directions, that there were 5 successful spe- earlier were announced. Samar Saha coordinating with IEEE Future Direc- cial issues for JEDS this year and presented the Fellow evaluation de- tion Committee and similar initiatives the number of submissions has in- tails. There are 16 EDS members el- in sister societies. Certain areas have creased from last year. The impact evated to IEEE Fellows among the been identified, for example, Brain factor of all three journals has been 2021 class of fellows. Patrick McCar- initiative, Quantum information pro- improving every year. ren gave a report summarizing EDS cessing, In-memory computing, and Camilo Velez, YP Committee Chair, office activities. committees are being organized for presented Young Professionals com- After discussion, President Meyya initiating action plans. mittee activities, which have been Meyyappan thanked all participants Suman Datta, 2020 IEDM General progressing. EDS visibility in So- from around the globe for their par- Chair presented the latest status of cial Media platforms are very good. ticipation and support throughout the first ever virtual IEDM this year. Among various platforms, LinkedIn the year, as well as EDS Staff for The Tutorials and Short courses had seems to be more useful to increase their dedicated effort in the midst of excellent participation setting new EDS visibility. the pandemic. He adjourned the vir- attendance records. The conference Fernando Guarin presented the tual meeting at 12:20 pm US Eastern will be virtually available with an in- Humanitarian Activities summary. In Time. teractive platform. 2020, EDS has spent $126K on 10 proj- Giovanni Ghione, Editor-in-Chief ects and $393K on 16 projects from MK Radhakrishnan of TED presented the status of the the previous years, 3% of reserve and IEEE EDS Secretary

MESSAGE FROM EDS PRESIDENT

Dear EDS members: classes—through Webex, Zoom, MS virtual conference for us, actually for Hope you are all Teams, Skype and others. It appears the entire IEEE, was the EDTM (4th keeping well and that students and postdocs are begin- IEEE Electron Devices Technology and safe amid this ning to get limited access to labs in Manufacturing Conference, sched- COVID-19 crisis. some places. Hope this practice con- uled to be held in Penang, Malaysia), I jokingly said at tinues and expands in all regions, as which turned out to be a tremendous the last mid-year research productivity would suffer oth- success. Since then, we have had Board of Gover- erwise tremendously. several successful virtual conferenc- Meyya Meyyappan nors meeting (vir- In EDS also, we have adjusted to a es. We have had very good support EDS President tual meeting, of new normal. The staff has been func- from IEEE Meetings, Conferences & course) that I am tioning fine, working from home and Events (MCE) in terms of logistics poised to continue my virtual Presi- conducting all usual business. All our including the conference platform dency through into 2021. We are all VPs have hit the ground running, tak- tools. Our feeling is, if this practice of looking forward to the day when we ing care of their EDS responsibilities virtual events continues for another can resume business as before. efficiently. First and foremost, all of year or two, IEEE MCE is going to In the meantime, we have all ad- our regular conferences have shifted be overwhelmed with the demands justed to a new normal, mostly con- to the virtual mode. Only a few have from all the Societies and Councils to ducting business—including teaching been canceled in 2020. The first-ever run virtual events. Therefore, we have

36 IEEE Electron Devices Society Newsletter ❍ January 2021

28neds01_Final_DigitalOnly.indd 36 1/20/21 11:16 AM made a prudent decision to invest in with attendees far beyond the Delhi broad membership by email. These creating our own tools and platforms borders. I hope all other Chapters fol- webinar presentations are archived on for running the EDS conferences. low this lead. Please contact Laura Ri- the EDS website for on-demand view- As a part of the new normal, we ello at EDS Office if you need help or ing available only to EDS members. have asked all our chapters to run the further information on running the DL Please contact our VP for Educational DL program virtual. Some chapters program virtual. We have also been of- Activities, Prof. Navakanta Bhat, if you have responded. I want to single out fering webinars on a nearly biweekly have suggestions for speakers or any the Delhi Chapter and Manoj Saxena basis with an excellent set of speakers input on the webinar series and other for the amazing work they have been on a wide range of topics of interest to educational activities. doing: 13 DLs in 30 days in the begin- the EDS audience. The webinar sched- ning and many more since, with ex- ules are announced on the EDS web- Meyya Meyyappan cellent attendance in each case and site and also communicated to our EDS President

MESSAGE FROM THE CHAIR OF THE EDS OPTOELECTRONIC DEVICES COMMITTEE

Dear EDS Members and Readers, and physically distanced conversa- and non-profit organizations as well It is my pleasure tions, our committee is encouraging as citizen scientists, citizen engineers, to write this mes- you to benefit from the webinars at and citizen entrepreneurs. Technolog- sage as the Chair https://eds.ieee.org/education/ ical solutions to increase virtual pres- of the EDS Opto- webinars. EDS’s webinar series de- ence and to limit pandemic impact electronic Devices liver live and archived lectures with on our personal and professional Committee—one luminaries from the field of electron lives are being introduced constant- of the fourteen device engineering. With the recent ly. As we navigate through the pan- Can Bayram technical commit- coverage of topics such as photo- demic, it is vital to stay connected as Chair, EDS Opto- tees in our society. voltaics, opto-electro-mechanics, the EDS society and strengthen our electronic Devices As a volunteer- detectors, and emitters, you will be resolve to come up with solutions Committee driven committee, certain to foster professional growth given the strength of our numbers we serve the soci- from the convenience of your home and expertise. ety primarily through organizing we- or office. You can also enjoy the path In continuing efforts, our com- binars, creating special invited issues to commercialization topic webinars. mittee is discussing a focused opto- in the EDS journals, and contributing Lastly, our committee solicited a electronic session at the IEDM 2021. to the conferences through organiz- photonic disinfection webinar to en- We would like your candid opinion ing special sessions. hance the public visibility of the pan- of the emerging topics by email to We are in the midst of a cultural demic relief efforts the EDS members [email protected]. change. The ripples of the pandemic and electron devices technologies will continue to reshape our person- are behind. al, professional, and academic lives. We are strong. The pandemic relief Can Bayram With reduced travel to conferences, efforts are driven by governments, Chair of the EDS Optoelectronic limited access to research facilities, companies, universities, societies, Devices Committee

January 2021 ❍ IEEE Electron Devices Society Newsletter 37

28neds01_Final_DigitalOnly.indd 37 1/20/21 11:16 AM MESSAGE FROM EDS NEWSLETTER EDITOR-IN-CHIEF

Dear Readers, cycle was initiated in the July 2020 is- Editorial Team, Members of the sue. We are looking forward to read- which is complete IEEE EDS Com- ing the next installment of this series. now. Dr. Stewart munity, welcome The Upcoming Technical Meetings Smith has been ap- to the IEEE EDS section announces four important con- pointed as the Re- Newsletter issue ferences, namely 5th IEEE Electron De- gional Editor for January 2021. vices Technology and Manufacturing Region 8, United Daniel Tomaszewski This Newslet- (EDTM) Conference 2021, IEEE Photo- Stewart Smith Kingdom, Middle EDS Newsletter ter issue brings voltaics Specialists Conference 2021, East & Africa. Dr. Editor-in-Chief you messages 13th International Memory Workshop Smith is with School of Engineer- from Prof. Meyya (IMW), and Latin American Electron ing of the University of Edinburgh, Meyyappan, the President of EDS, Devices Conference (LAEDC) 2021. Scotland, U.K. Stewart, it is my great and from Can Bayram, Chair of the The Regional News section brings pleasure to welcome you, and wish EDS Optoelectronic Devices Commit- as always articles reporting daily work fruitful work for the EDS Newsletter. tee. Furthermore, you can read a sum- of the Society Chapters. Many events At this point I would like to express mary of the EDS BoG virtual meeting, were held virtually. However, in spite of our gratitude to the outgoing Regional held on December 12–13, 2020. the pandemic, there were also in-per- Editor: Jonathan Terry, for his dedica- The Technical Briefs Section is very son meetings organized with precau- tion for the Newsletter and excellent rich in this issue. It brings highlights tionary measures. In the Chapter News job beyond the end of his regular 2nd of three technical conferences of great you can find an interesting report on term. Jonathan, all the best to you ! importance for the electron devices DIPED-2000 with a memory talk devot- Finally, I would like to express my professionals and enthusiasts: the ed to Prof. Voitovich, who passed away thanks to all the Authors of articles in 2020 IEEE International Electron Devic- this year, and an encouraging article this issue, to the Regional Editors and es Meeting, the 47th IEEE Photovoltaic promoting the EDS Student Branch all the members of the Editorial Team. Specialists Conference, and the 2020 Chapter Instituto Tecnológico de Costa Dear Readers, if you have any sug- IEEE International Physics Reliability Rica, recipient of the 2020 IEEE EDS gestions, comments regarding the Symposium. I would like to add that in Student Branch Chapter of the Year Newsletter contents, please do not the Regional News you can also read Award. The latter note together with a hesitate to contact me. I will be very a report on the joint EuroSOI—ULIS story in the Young Professionals about glad to receive your feedback. Please, 2020 Conference. Finally, among the a way of R&D in microelectronics in In- accept the warmest wishes from our Technical Briefs you can find the next dia may be inspiring and instructive for Team for the Year 2021. interesting article concerning a set the ED communities on a global scale. of reports of the International Focus I am happy to announce that a Sincerely, Teams within the IRDS initiative. Our new member joined the Newsletter Daniel Tomaszewski

CONGRATULATIONS TO DR. ROBERT W. DUTTON 2020 IEEE EDS CELEBRATED MEMBER

To honor and rec- can take pride in the accomplishments crystal during the 2020 IEEE Elec- ognize esteem- of these Celebrated Members and draw tron Devices Meeting (IEDM) vir- ed IEEE Electron from the inspiration to advance our field tual event. Devices Society and to achieve more, because it is not For a complete bio for Dr. Dutton, alumni, EDS creat- only their work but ours as well, that can please visit the EDS Celebrated ed the Celebrated help transform the world around us. Member gallery, at https://eds Member Program. Recently, Dr. Dutton was present- .ieee.org/members/celebrated Dr. Robert W. Dutton Those of us in EDS ed with the EDS Celebrated Member -members.

38 IEEE Electron Devices Society Newsletter ❍ January 2021

28neds01_Final_DigitalOnly.indd 38 1/20/21 11:16 AM EDS MEMBERS NAMED RECIPIENTS OF 2021 IEEE TECHNICAL FIELD AWARDS

Hideaki Aochi, ate program in 2007 at the University Ryota Katsumata, of California, Irvine, which was one of a and Masaru Kito’s few such programs at that time. revolutionary BiCS An IEEE Life Fellow, Lee is a pro- concept has be- fessor (retired) with the University of come the standard California, Irvine, California, USA. for realizing high- density and fast Fernando Guarin Ryota Katsumata Masaru Kito IEEE Cledo Brunetti Award three-dimensional EDS Awards Chair For leadership in and contributions to (3D) flash memo- opment Center at KIOXIA Corporation, InGaAs- and GaN-based field-effect ry to meet the needs of the powerful Mie, Japan. transistor technology personal devices of today and the fu- An IEEE Member, Masaru Kito is ture. To overcome the scalability and a group manager with the Advanced A pioneer in driving complexity issues of early 3D flash Memory Development Center at KIOXIA III-V semiconductor memory concepts, the team cre- Corporation, Mie, Japan. research since its ated the new three-dimensional flash early days, Jesús del memory by punch and plug method, IEEE Electronics Packaging Alamo has played which features a multi stacked memo- Technology Award a foundational role ry array with fewer critical lithography For contributions to new silver alloys, in establishing the steps and charge-trapping cells for new bonding methods, flip-chip inter- Jesús del Alamo viability of indium high-density yet cost-effective scalable connect, and education for electron- gallium arsenide memory. Their new concept has been ics packaging (InGaAs) and gallium nitride (GaN) tran- widely used in solid-state drive stor- sistors for high-frequency communica- age systems for smartphones, PCs, Chin C. Lee’s inno- tion, electrical power management and and high-performance computers. vative bonding digital logic applications. With InGaAs- With the capability for greater than a methods and mate- based materials, his research group has terabyte density, the team’s innova- rials and new pack- pursued nanoscale high-electron motive 3D flash memory can also replace aging technologies bility transistors (HEMTs) and metal- hard disk drives, with the benefits of have been integral oxide-field-effect transistors (MOSFETs) no moving parts, smaller footprint, to developing high- for Terahertz applications and achieved and lower power consumption. Chin C. Lee temperature and record performance in many dimensions. high-power elec- In the GaN heterostructure system, his IEEE Andrew S. Grove Award tronics. His work on silver wire bond research has focused on achieving fun- For pioneering and sustained con- reliability resulted in a wider process damental understanding of electrical, tributions to high-density, three-di- window, lower cost, and higher yield in environmental, and thermal reliability mensional flash memory packaging components. He also discov- of HEMTs for radio-frequency and powered that silver alloy is anti-tarnishing, er electronics applications. Transistors An IEEE Senior which has had enormous economic based on del Alamo’s innovations have Member, Hideaki and technical impact for applications in- found use in applications ranging from Aochi is a senior cluding optics, astronomy telescopes, smartphones to fiber-optic systems to expert with the and LED packaging. His fluxless sol- wireless networks. Institute of Mem- dering technology has enabled numer- An IEEE Fellow, Jesús del Alamo ory Technology ous bonding designs and is critical to is the Donner Professor and profes- Research and De - packaging electronics for applications sor of electrical engineering with the Hideaki Aochi velopment at where oxidation effects from solder Massachusetts Institute of Technolo- KIOXIA Corpora- materials can be problematic. Lee also gy, Cambridge, Massachusetts, USA. tion, Kanagawa, Japan. developed solid-state flip-chip intercon- An IEEE Senior Member, Ryota nects and formulated quantum bond- Fernando Guarin Katsumata is a deputy general manag- ing theory. He established a materials EDS Awards Chair er with the Advanced Memory Devel- and manufacturing technology gradu- GlobalFoundries

January 2021 ❍ IEEE Electron Devices Society Newsletter 39

28neds01_Final_DigitalOnly.indd 39 1/20/21 11:17 AM IN MEMORY OF PROF. JAMES D. MEINDL

BY KRISHNA SARASWAT

James Donald Meindl, a towering As much as Meindl was known figure from the earliest days of inte- as a visionary engineer, however, he grated circuitry, died on June 7, 2020 was regarded more so as a master at his home in Greensboro, Georgia. of human potential—particularly, in He was 87. his students. He mentored 90 Ph.D. Meindl was a great visionary, truly candidates during his almost-five- one of the icons of the silicon era, decade academic career at Stanford, who saw early on the potential of RPI, and Georgia Tech. That intellectu- integrated circuitry and who swayed al diaspora has gone on to have pro- the semiconductor industry in new found influence everywhere from the directions for decades. semiconductor industry to university Meindl was born on April 20, 1933 research and administration. in Pittsburgh, Pennsylvania. He re- Meindl authored 4 books, and more ceived his BS, MS and PhD degrees than 600 technical papers, and he was in electrical engineering from Carne- granted 23 patents. He served as the gie-Mellon University in 1955, 1956, founding editor of the IEEE Journal of Prof. James D. Meindl (1933–2020) and 1958 respectively. Solid State Circuits. He was likewise From 1965 to 1967, he was found- and blood-flow measurement tools frequently recognized with industry ing director of the Integrated Elec- that paved the way for medical sys- awards and accolades. In addition to tronics Division of the U.S. Army tems that are widely used today. Later the 2006 IEEE Medal of Honor, he was Electronics Laboratories in Fort Mon- on, anticipating that power consump- elected to membership in the Nation- mouth, New Jersey. tion, not speed or size, would become al Academy of Engineering and the In 1967, he joined Stanford Uni- the major limiting factor on future American Academy of Arts and Sci- versity as John M. Fluke Professor of chip performance, Meindl became a ences. He was a Fellow of the Ameri- Electrical Engineering and founded proponent of low-power electronics, can Association for the Advancement the Integrated Circuits Laboratory. which prized energy efficiency above of Science and an IEEE Life Fellow. In 1987 he co-founded the Center all. In this regard, he was decades Throughout his career, he was a for Integrated Systems (CIS), before ahead of the industry. sought-after advisor and board mem- becoming vice provost of research. In 1986, Meindl became provost ber for many companies, including While at CIS, Meindl was noted as an of Rensselaer Polytechnic Institute. IBM, Intel, Hewlett Packard. His lead- early champion of another Silicon Val- In 1993, he moved to Georgia Tech, ership and advisory roles in govern- ley innovation: the university-industry where he was director of the Joseph ment and industry organizations partnership. He helped forge lasting M. Pettit Microelectronics Research included work with the Semiconduc- relationships between Stanford and Center and the Marcus Nanotechnol- tor Industry Association and the Na- notable semiconductor companies, ogy Research Center and Pettit Chair tional Science Foundation’s National like Intel, Advanced Micro Devices, Professor of Microelectronics. He was Nanotechnology Infrastructure Net- IBM, and HP. At Stanford, Meindl de- founding director of the multi-institu- work. veloped low-power ICs and sensors tional, multidisciplinary Interconnect James D. Meindl is survived by his for a portable reading aid for the Focus Center and led a team of more wife Frederica Meindl of Greensboro, blind, miniature wireless radio-telem- than 60 researchers from Georgia Georgia; son Peter Meindl; daughter etry systems for biomedical research, Tech, Stanford, MIT, RPI, and others. Candace Fleming; brother Edward and noninvasive ultrasonic imaging He retired from Georgia Tech in 2013. Meindl and several grandchildren.

40 IEEE Electron Devices Society Newsletter ❍ January 2021

28neds01_Final_DigitalOnly.indd 40 1/20/21 11:17 AM ANNOUNCEMENT OF THE 2020 EDS UNDERGRADUATE STUDENT SCHOLARSHIP WINNERS

The Electron Devices Society Un- electronic synapses and neurons with Technology Kharagpur. Prior to join- dergraduate Student Scholarship more complex morphology and struc- ing IIT Kharagpur he completed his Program was designed to promote, ture. Yanghao Wang took part in the schooling from Our Own English recognize, and support undergradu- 2018 national undergraduate physics High School, Sharjah in the United ate level study and hands-on expe- competition and won the first prize. He Arab Emirates. Upon completing rience within the Electron Devices won the Peking University Academic his high school studies he gave the Society’s field of interest. Excellence Award in 2019. Besides, he JEE advanced examination in which EDS proudly announces the win- won the prestigious IEEE Electron De- he scored in the top 99.5 percentile ners of the 2020 EDS Undergraduate vices Society undergraduate scholar- among approximately 200,000 candi- Student Scholarships. ship as a recognition of his academic dates which helped him secure a seat experience in 2020. Yanghao Wang in the Electronics and Electrical Com- Yanghao Wang is has published four papers on Nature munication Engineering department a senior student Communications, Science Advances, of IIT Kharagpur. Throughout Azwar’s majoring in micro- Advanced Intelligent Systems and Chi- high school years he loved to study electronics at the nese Science Bulletin until now. His physics, especially topics of electricity school of Electron- contribution is to design and simulate and magnetism. This was the primary ics Engineering brain-inspired algorithms to resolve reason why he chose to pursue his and Computer Sci- some specific and meaningful prob- undergraduate studies in Electronics. ence, Peking Uni- lems utilizing actual electronic devices’ Azwar’s present research interests versity, China and is a student member intrinsic dynamics or non-ideality. His include simulation and modeling of of the IEEE Electron Devices Society. first-authored work in Advanced Intel- GaN HEMTs for power application. He He entered Peking University in 2017 ligent Systems was selected in Editor’s began his research work under prof. after graduating from Shaoxing No.1 Choice and further promoted on Ad- Gourab Dutta of IIT Kharagpur in his high school and passed a series of vanced Science News as a highlight, sophomore year working on the ana- microelectronic professional courses where he first proposed an implemen- lytical modeling of threshold voltage with excellent grades in college. He tation method of biologically plausible of p-GaN HEMTs. pGaN HEMTs are has been participating in academic re- working memory based on neuromor- currently emerging as a promising E- search since the summer of 2018 and phic devices. In a co-authored paper mode GaN HEMT with technological his advisors are Yuchao Yang and Ru published on Nature Communications giants like Samsung and Panasonics Huang. His research interests focus and Science Advances, he respectively having already begun production of on novel memristive devices for neu- utilized the characteristics of nonlinear commercial p-GaN HEMTs. His work romorphic computing: 1) Exploiting neuron devices to construct large- on the analytical model of threshold computing superiorities of electron scale spike synchronization detection voltage was accepted for publication synapses and neurons with spatio- applications and nonlinear synaptic in the journal semiconductor science temporal dynamics. 2) Constructing devices to construct transient chaotic and technology. Azwar also worked biologically plausible memory models neural networks for combinatorial op- on a TCAD based simulation study of and circuit architectures with low pow- timization problems. After completing the threshold voltage of an E-mode er consumption. 3) Designing neuro- his B.A. in 2021, Yanghao Wang will AlGaN/AlGaN HEMT which he then morphic chips with new devices and continue to pursue his Ph.D. degree presented as a poster at the XXth new computing principles which can under the guidance of Ru Huang in Pe- International Workshop on the phys- support advanced but unsuitable for king University, China. ics of Semiconductor Devices held at current hardware brain-inspired algo- Kolkota, India. After concluding his rithms. Now he is a member of the na- Azwar Abdulsalam work on the threshold voltage of E- tional key research and development is a final year stu- mode GaN HEMTs he began his work project dealing with nonvolatile mem- dent currently pur- on the analytical modeling of 2-DEG ristive devices for logic. He also had a suing his Bachelors charge density and gate capacitance summer research internship in West- in Electronics and of p-GaN HEMTs. Recent works have lake University, China, where he ex- Electrical Commu- indicated the advantages of using p- plored the potential of high precision nication from the GaN HEMT as an on-chip capacitor 3D printing technology to manufacture Indian Institute of thus making this work particularly

January 2021 ❍ IEEE Electron Devices Society Newsletter 41

28neds01_Final_DigitalOnly.indd 41 1/20/21 11:17 AM important. This work was then ac- Elison Matioli. Here he worked for and hopes to make a significant con- cepted for publication in the IEEE about six months on a TCAD simula- tribution to the field. Transactions on Electron Devices. tion project on Tri-gate HEMTs. Cur- In the summer of 2020 Azwar was rently he is working on his graduate Samar K Saha involved in a remote project at the application to pursue his passion of EDS Undergraduate Student POWERlabs in EPFL headed by prof. research on semiconductor devices Scholarship Committee Chair

ANNOUNCEMENT OF THE 2020 EDS MASTERS STUDENT FELLOWSHIP WINNERS

The Electron Devices Society Mas- Tu has published two scientific papers Prasanna Venkatesan ters Student Fellowship Program as a primary author on IEEE Electron received his B.Tech was designed to promote, recognize, Device Letters and Journal of Physics degree in Electrical and support Masters level study and D: Applied Physics in his junior year Engineering from research within the Electron Devices and senior year, respectively. He has Indian Institute of Society’s field of interest. proposed degradation mechanisms Technology (IIT) for LTPS TFTs under negative bias Palakkad in 2019

EDS proudly announces the temperature instability of the devices Prasanna with the Department winners of the 2020 EDS with different grain size and proposed Venkatesan Gold Medal. During Masters Student Fellowship degradation mechanisms of hump his B.Tech, Prasan- Hong-Yi Tu was formation with hysteresis effect after na was selected to the prestigious S. N. born in Tainan, Tai- the devices operated under high posi- Bose Scholars Program in 2018. He is wan, in 1997. He tive bias. To date, he has published currently a second year PhD student in received his B.S. 2 articles as primary author and 10 Dr. Asif IslamKhan’s lab at Georgia Insti- degree in materials articles as co-author. Apart from aca- tute of Technology. Prasanna’s interests and optoelectronic demic publication, he has also par- lie at the intersection of electrical engi- science from Na- ticipated in several industry-academic neering, material science and quantum tional Sun Yat-Sen cooperative research projects mainly physics. The sheer curiosity about how University, Taiwan, in 2020. He is cur- solving device performance and reli- things work and a deep desire to con- rently in the five-year bachelor’s and ability issues. In addition, he wins the tribute to the advancement of technol- Master’s degree program pursuing the “Student Engineering Paper Contest” ogy drive Prasanna to learn every day. M.S. degree at National Sun Yat-Sen held by Chinese Institute of Engineers The goal of Prasanna’s research is to University, supervised by Prof. Ting- (CIE) and wins the 2018, 2019 and 2020 push the limits of computing technol- Chang Chang and Prof. Tsung-Ming “College of Engineering Project” in his ogy by exploiting the intricacies in fun- Tsai. His research interests include college for his project poster presen- damental science and understand the low-temperature polycrystalline sili- tation. Furthermore, he is one of the interesting physics of functional materi- con (LTPS) thin-film transistors (TFTs), recipients of the “Undergraduate Stu- als like ferroelectrics and antiferroelec- amorphous metal oxide TFTs, flexible dent Research Scholarship” from both trics. He plans on joining academia after TFT technology, and high electron the Ministry of Science and Technol- completing his PhD. mobility transistors (HEMTs). His cur- ogy (MOST), Taiwan and the National rent research focuses on the reliability Sun Yat-Sen University. He also gets Subramanian S. Iyer issues and optimization of reliability in the “Academic Excellence Award” in EDS Student Fellowship LTPS TFT and metal oxide TFT. Hong-Yi his department. Committee Chair

42 IEEE Electron Devices Society Newsletter ❍ January 2021

28neds01_Final_DigitalOnly.indd 42 1/20/21 11:17 AM ANNOUNCEMENT OF THE 2020 EDS PHD STUDENT FELLOWSHIP WINNERS

The Electron Devices Society PhD mance zinc-tin-oxide thin-film tran- His research focuses on reconfigu- Student Fellowship Program was sistors with process temperatures rable radiofrequency circuits using designed to promote, recognize, compatible with flexible electronics high-performance switches based and support PhD level study and re- and back end of line 3D monolithic on emerging memory technologies, search within the Electron Devices integration. Outside of the lab, Chris such as phage-change memory Society’s field of interest. has been an active member of the (PCM), resistive RAM (ReRAM) and EDS proudly announces three EDS University of Michigan College of En- conductive-bridge RAM (CBRAM). PhD Student Fellowship winners for gineering’s community by serving on Currently, he is working on the 2020: Wangyong Chen—Peking Uni- the Lurie Nanofabrication Lab’s User development, fabrication, and mod- versity (China); Chris Allemang—Uni- Committee, the college’s Diversity, eling of high-performance PCM RF versity of Michigan (USA); Nicolas Equity, and Inclusion Student Ad- switches as well as circuit design Wainstein—Technion—Israel Institute visory Board, and the college’s Cur- and fabrication of reconfigurable RF of Technology (Taiwan). Brief biogra- riculum Committee. Chris’s goals in front-end circuits based on these de- phies of the recipients appear below. participating in these activities were vices. A summary of his findings on Detailed articles about each PhD Stu- to promote student camaraderie and this topic was recently published in dent Fellowship winners and their to create a more inclusive place for the Proceedings of the IEEE. He suc- work will appear in forthcoming is- all students to live, learn, and grow. ceeded to publish more than seven sues of the EDS Newsletter. To foster STEM in underrepresented articles in high-impact factor jour- groups, he has assisted with Electri- nals like IEEE TCAS I, IEEE T-NANO, Christopher R. fy-Sense It Summer Camps where Nature Electronics, and IEEE T-ED. Allemang is a Ph.D. high school students work on small He also has more than six confer- candidate studying team projects focused on program- ence contributions including IEEE electrical and com- ming, microcontrollers, and wire- DRC (late news), MRS, IEEE ISCAS, puter engineering less sensing. During the COVID-19 and IEEE ISVLSI. Mr. Wainstein was in Professor Becky pandemic, Chris has enjoyed going a recipient of the 2020 Yablonovitch Peterson’s group outside for walks with his dog and Research Prize, the 2020 RBNI Prize at the University of playing virtual board games with his for Excellence in Nanoscience and Michigan. Prior to coming to the Univer- friends. When not in a pandemic, he Nanotechnology, the 2020 RBNI sity of Michigan, Chris received a Bache- enjoys playing flag football in a De- Scholarship, the 2019 Jury Award lor of Science in electrical engineering troit LGBT league. The league’s travel for Outstanding Students, and the from the University of South Florida team Chris plays on won first place in Excellence Scholarship from the where he was an undergraduate re- their division at Chicago’s 2019 Pride Andrew and Erna Viterbi Faculty of searcher and Chair of the IEEE Stu- Bowl. He also serves as a moderator Electrical Engineering, Technion—Is- dent Branch. His research interests for an online automotive forum and is rael Institute of Technology, in 2018, include microfabrication for scalable active in politics by volunteering for 2019, and 2020. Teaching has also manufacturing of thin-film electron- various campaigns. played an important role in his ca- ics for back end of line 3D monolithic reer; being involved in teaching ac- integration on silicon CMOS for “More Nicolás Wainstein tivities since his B.Sc. in Uruguay. He than Moore” technologies and cus- is a Ph.D. student was a TA in Physics and EE courses tomizable manufacturing of thin-film at the Andrew at the EE faculty, Universidad de la electronics. His work spans deposi- and Erna Viterbi República. At the Technion, he is a tion and characterization of oxide Faculty of Electri- TA in several courses, such as In- semiconductor materials and devices, cal Engineering, troduction to VLSI and Advanced including atomic-layer deposition of Technion—Israel Architectures and Circuits using multi-component semiconductor ma- Institute of Tech- Memristors. He was also a TA of the terials. The work Chris has performed nology, Haifa, Israel since 2015. He Advanced Analog Integrated Circuit with atomic layer deposition of zinc- received the degree in electrical Design course, given by Prof. Willy tin-oxide semiconductors and alumin- engineering (5-year program) from Sansen (KU Leuven). In his free time, ium oxide passivation layers have the Universidad de la Repúbli- he enjoys running, playing football, contributed to record high-perfor- ca, Montevideo, Uruguay, in 2014. going to the beach, and traveling.

January 2021 ❍ IEEE Electron Devices Society Newsletter 43

28neds01_Final_DigitalOnly.indd 43 1/20/21 11:17 AM Wangyong Chen variations. The simulator provides a doctoral study period, including con- (IEEE Student Mem- powerful tool for comprehensive reference and journal papers on the IEEE ber, EDS Member, liability evaluation at the advanced IEDM, EDL, T-ED and T-NANO. He re- and Young Profes- technology node and traps impact ceived the IEEE IPFA Best Paper Award sionals) received the identification over the entire bias in 2018, and he was invited to deliver B.S. degree in Elec- space. Within the Ph.D. study, he did a report at the ESREF conference in tronics Science and series of works on self-heating effect 2018. He was selected as the Best Technology from in advanced nanoscale devices rang- Paper Award in the Microelectronics Hunan Uni ver sity, Changsha, Chi- ing from experimental characterization Forum of China in 2018. He won the na, in 2016. He is currently pursuing the to modeling and simulation, where an title of outstanding graduate of Hu- Ph.D. degree in Microelectronics analytical model based on the multi- nan Province and Hunan University a n d Solid State Electronics with the stage thermal network to effectively in 2016. He was awarded the National Institute of Microelectronics, Peking address the self- and mutual-heating Scholarship in China 5 times from 2013 University, Beijing, China. His current in the scaled device was developed to 2020. He won the Headmaster’s Fel- research interests include multi-scale and a novel self-heating characteriza- lowship in 2019 which is the top honor reliability modeling and simulation from tion method using the shared intrinsic prize for the graduate student in Pe- devices to circuits as well as experi- series resistance was proposed. He king University, and he was selected mental characterization, including also proposed an efficient variability- as Merit Student and Academic Inno- reliability-aware device-circuit co-de- and reliability- aware device and cir- vation Award from Peking University sign, self-heating characterization. cuit co-design methodology to predict for two consecutive years. He serves He developed the trap dynamics the time-dependent delay degradation as the active reviewer for IEEE T-ED, based 3D Kinetic Monte Carlo simu- and potential critical paths in the digi- EDL and J-EDS, etc. lator to capture the statistical charge tal circuits coupled with self-heating distributions in the multilayer gate effect at arbitrary operating conditions. Subramanian S. Iyer dielectric under arbitrary stress con- He has published 28 technical pa- EDS Student Fellowship ditions in the presence of time-zero pers and owned 3 patents during the Committee Chair

2020 EDS CHAPTER OF THE YEAR AWARD WINNERS

The EDS Chapter July−June period. EDS recently re- 2020 Student Branch Chapter of the of the Year Award vised our Chapter of the Year Award Year Award: IEEE ED/RFID/BIO Costa is presented annu- to award one non-student chapter Rica Institute of Technology Student ally to recognize and one student chapter in any geo- Branch Chapter chapters for the graphic location. quality and quan- The 2020 EDS Chapter of the Year tity of the activi- Award winners: Murty Polavarapu ties and programs Murty Polavarapu EDS Vice-President implemented 2020 Chapter of the Year Award: IEEE EDS Vice-President of of Regions/Chapters during the prior ED Uttar Pradesh Kanpur Chapter Regions/Chapters

44 IEEE Electron Devices Society Newsletter ❍ January 2021

28neds01_Final_DigitalOnly.indd 44 1/20/21 11:17 AM

Call for Nominations – EDS Student Fellowships for 2021

The IEEE Electron Devices Society invites nominations for the 2021 PhD, Masters and Undergraduate Student Fellowships. These annual awards are given to promote, recognize, and support graduate, masters, and undergraduate level study and research within the EDS field of interest. For both Masters and PhD, it is expected that at least one fellowship will be awarded to a student in each of the following geographical regions: Americas, Europe/Middle East/Africa, and Asia/Pacific. For the Undergraduate, it is expected that at least one fellowship to each eligible student in each of the IEEE geographical Regions 8, 9, and 10 and two fellowships in Regions 1-7 not exceeding one from Region 7.

Please visit the EDS website links below to access information about these Fellowships.

EDS Masters Student Fellowship Prize: US $2,000 and an award plaque Submission Deadline: May 15, 2021

EDS PhD Student Fellowship Prize: US $5,000 and travel funds to attend the IEDM for presentation of an award plaque Submission Deadline: May 15, 2021

EDS Undergraduate Student Scholarship Prize: US $1,000 and an award plaque Submission Deadline: May 15, 2021

Please help to promote the EDS Student Fellowships by distributing this information to your colleagues and students. If you have any questions or need further information, please do not hesitate to contact Stacy Lehotzky by email at [email protected]. Thank you!

January 2021 ❍ IEEE Electron Devices Society Newsletter 45

28neds01_Final_DigitalOnly.indd 45 1/20/21 11:17 AM Y OUNG P ROFESSIONALS

INDIA’S RISE IN NANOELECTRONICS RESEARCH

UDAYAN GANGULY, SANDIP LASHKARE, AND SWAROOP GANGULY, IIT BOMBAY

Witnessing a Quiet Evolution At the time of graduation, some pelling indicators. Both EDL and TED are As semiconductor innovations power students would embark on a pilgrim- considered the most exclusive venues to the digital age, India has aspired to age to Indian research-centric insti- publish electron device-related research. contribute to nanoelectronics. Towards tutes to get the “lie of the land”—a India was doing well in both. this, India pushed a strong nanoelec- core instinct for experimentalists. The tronics program starting in 2006. Our news was that IISc and IIT Bombay A Trajectory of Strong Growth study shows that recently India has had proposed two Nanofabrication Fa- The next question was—how long been significantly contributing to Elec- cilities—one at each location. The effort has this been going on? A compara- tron Devices Society related publica- was being led by the Office of Principal tive study of the University of Califor- tions. This evolution has been quiet, Scientific Advisor through the Ministry nia (UC) System, Chinese Academy of largely unnoticed in the humdrum of of Electronics and IT (MeitY). It was a Science (CAS), National Chiao Tung academic and research life. This paper big relief. Yet, there were questions. University (NCTU) Taiwan, and the In- presents the development of the Indian Will academia be able to develop the dian Institute of Technology (IIT) Sys- nanoelectronics R&D ecosystem from Nanofabs? Will new faculty be able to tem revealed the trajectories (Fig. 2). nothing to global competitiveness. The develop a globally competitive R&D Unlike UC, CAS, NCTU, which have lessons from this shared experience program around these new Nanofabs? been publishing regularly, the IIT will help India and other countries who Only time could tell… System had negligible publications aspire to set sail for similar R&D ad- before 2011. Since 2011/2012, the IIT venture, to develop a more grounded, Recent Significant Contributions system has accelerated publication in and robust policy and implementation Fast-forward to 2020, when an IEEE TED as well as in EDL. The publication towards an ambitious future. EDS journal annual performance re- in TED has overtaken other university port analyzed its contributors. In a cor- systems recently and was ranked 1st A Snapshot from the Past ner of the report, there was a strange in 2019. Similarly, the publication in In 2004, the industry was pushing tran- little graph. It showed that India with IEEE EDL has reached a level com- sistor scaling to high performance, 40 papers was ranked 8th in the con- parable to other systems. Starting faster & denser integrated circuits tribution to Electron Device Letters from 2015/2016 a saturation of the IIT manufactured at Intel, AMD, and other (EDL) by countries, whereas the IIT publication rate has been observed. leading semiconductor companies. In System with 34 papers was ranked 9th Citations per paper were comparable academia, Cornell and Stanford nano- among organizations (Fig. 1a,b). This to the journal average—slightly better fabrication facilities were driving na- was curious. In the whirlpool of re- than NCTU and CAS, which are simi- noscience and technology—pushing search, funding, teaching, and fighting larly aged institutions, but worse than cutting-edge nanoscale physics from administrative fires, most academics UC, which is an older player ( Fig. 2). carbon nanotube and quantum dot to would have no bandwidth left to con- While India had significant achieve- the technology of deep-sub-micron template the “overarching” state of In- ments even as early as 2005 in basic CMOS. Indian students would naturally dian R&D—except in anecdotes. But, science ranking in SCOPUS etc. [1], the evolve into contributors in internation- this nugget had to be investigated. growth in nanoelectronics engineering al academia, and the semiconductor Among many questions, the domi- research from negligible contributions industry with rewarding careers. Yet, nant one was whether EDL was an before 2011 to high intensity by 2018 is many dreamed to pursue a career in anomaly. So, we looked up the IEEE a significant success of the program. nanoelectronics research in India. How- Transactions on Electron Devices (TED) ever, semiconductor research was not performance. It was a further surprise. R esolving Growth at a similar intensity there. Essentially, The IIT system was ranked 1st in the con- As the growth trajectory is apparent, engineering institutes in India barely tribution by organizations and India was the question was - what are the thrust- had microfabrication facilities. ranked 3rd (Fig. 1c,d). These were com- ers driving the change? We needed

46 IEEE Electron Devices Society Newsletter ❍ January 2021

28neds01_Final_DigitalOnly.indd 46 1/20/21 11:17 AM F ig. 1. India and the IIT system records among top 10 performances in EDL and TED in 2019 (pie charts limited to the top 10 contributors)

to resolve by institutions, approach (experiment vs modeling), and global collaborations. We chose publications and citations per article as metrics of success—with the sense that one could always follow up with a more detailed study. Lastly, what publications will give a cogent picture? We chose three of them in the domain of electron devices to study the progres- sion from detailed, long-form studies (i.e. TED) to novel and newsworthy (i.e. EDL). To complete the series, we also looked at the International Elec- tron Device Meeting (IEDM). IEDM is the flagship conference where industry & academia showcase the latest and greatest technological development of industrial impact. We considered papers published between the year 2000–2020. While this list is not Fig. 2. A timeline of IIT publications in EDL and TED (Based on data from Web exhaustive, we believe that it shows of Science database 2010–2020) representative trends and questions which may motivate towards a more specific and exhaustive study. institutes [2]. IISc is a postgraduate Bombay, Madras, Delhi, and Kanpur) oriented institute while IITs are un- established in the 1950s have been In stitutions of Success dergraduate oriented, although re- transformative for the global technol- The IITs and IISc have the reputation cently evolving towards postgraduate ogy ecosystem. To replicate their suc- of being top engineering education research. The old IITs (Kharagpur, cess, various new IITs were created

January 2021 ❍ IEEE Electron Devices Society Newsletter 47

28neds01_Final_DigitalOnly.indd 47 1/20/21 11:17 AM Fig. 4. The collaboration of Indian institutes with researchers from other countries.

collaboration is critical to amplifying research contribution further.

Insp iring the Path Forward Research on electron devices in India has unfolded before our eyes over Fig. 3. Frequency of publications by IITs and IISc in 2000–2020. (The publication number in figure the past 15 years. This is related to the is slightly higher than the actual number as mentioned in the text above. This is due to some of key policy and the implementation the papers having multiple IITs collaboration. In such papers, every collaborated IIT has been of the shared Centers of Excellence given a separate count.) in Nanoelectronics (CENs) as rallying points for talented researchers who and some older engineering schools modeling and simulations. So, India grow up across the country thanks to like Roorkee and Banaras Hindu Uni- contributes strongly to physics-based the distributed project funding. Such a versity (Varanasi), were brought into device modeling. Furthermore, 54 pa- successful policy and implementation the IIT system. Publication activity of pers published in EDL (79%) and as should inspire a scale-up of the Indian these institutes in the period 2000– much as 96% of the papers presented ecosystem to contribute to the urgent 2020 is shown in Fig. 3. IIT Bombay at IEDM were based on experimen- national and global needs of an inno- and IISc Bangalore are the top contrib- tal demonstrations. The average ci- vation-driven ecosystem. We believe utors. They have the state-of-the art tations per paper are about similar, that the aspect of the history of R&D in experimental facilities. 13 IITs and IISc approx. 10.5 for both IEDM and EDL India presented in our article will help published 68 papers in EDL, 17 IITs articles and 8.43 for TED papers. It and inspire researchers in other coun- and IISc published 473 papers in TED. appears that an experimental dem- tries to grow the international network A smaller number of publications in onstration improves newsworthiness of research in electron devices—that is EDL by few IITs can be directly related and impact of the published paper. central to the concept of a borderless to lacking state-of-the art processing Electron Devices Society. facilities. Besides, 4 IITs and IISc pub- International Collaborations lished 26 papers at IEDM, which is the An exchange of knowledge with inter- Note s & Acknowledgements most selective conference. national partners plays a significant This is a modified excerpt from a Newer IITs like Indore, Guwahati, role in the research, and we dare to say detailed study available on arXiv Jodhpur, and Gandhinagar, to name is a necessary condition for successful (arXiv:2011.11251). The authors ac- a few, have also started contributing. works in micro- and nanoelectronics, knowledge Prof. Jesus del Alamo, Furthermore, older institutions but reported at the top level conferences MIT, Sunita Verma, Sangeeta Sem- newer entrants to the IIT system like and journals, which are considered in wal, and Nishit Gupta from MeitY, Roorkee and Varanasi have been also this analysis. Among the affiliations Milind Kulkarni from DST, and Prof. productive. This overall performance is of the international teams cooperat- Juzer Vasi, IIT Bombay. encouraging. ing with researchers from the IITs and IISc in India the top 3 countries are the References Intense Experiments USA, Germany, and Singapore (Fig. 4). [1] Department of Science and Tech- & Modeling This graph also indicates opportuni- nology, India, “Research & Statistics at a We found that 131 papers published ties to strengthen ties with countries Glance”, 2020 in TED (28%) were experimental and like Belgium, Taiwan, Brazil, Japan, [2] “QS India University Rankings”, QS 342 papers (72%) were based on and South Korea. Such a network of Top Universities, 2019.

48 IEEE Electron Devices Society Newsletter ❍ January 2021

28neds01_Final_DigitalOnly.indd 48 1/20/21 11:17 AM IEEE YOUNG PROFESSIONALS GERMANY AT ROBERT BOSCH SEMICONDUCTOR HEADQUARTERS

BY MIKE SCHWARZ

The IEEE Young Professionals Ger- many ExCom organized in cooperation with the Robert Bosch GmbH a virtual company visit on September 28, at the semiconductor headquarters of Bosch, Germany. Unfortunately, the worldwide pandemic situation made an onsite visit not possible. Therefore, all the registered participants agreed to make this virtual visit and event happen. From the 30 exclusive slots, 23 students and young professionals attended the virtual event. On top 14 participants from Bosch semiconductor headquarter, i.e. top level management, chief experts and human resources completed a great event. Vice President Dr. Markus Sonnemann presenting “MEMS—enabling technology for future mobil- The one-day event started at 9:15 ity solutions pushing the limits of MEMS” and went until 16:00. In the morning Mirko Hofmann, director of the After the overview Sebastian a lot of Q&A made an interesting ex- MEMS design house had a welcome Strache continued with “Bosch Pow- change between employees and stu- speech to the attendees and guided er Semiconductors and Modules’’. dents/young professionals. together with Mike Schwarz through Mr. Strache introduced the power The afternoon session started with the program of the day. semiconductors and SiC for volume a talk entitled “MEMS Technology”, The first talk was delivered by Ar- production. He also highlighted that given by chief expert Heiko Stahl. min Scharping and was entitled “Site ongoing research is fulfilled by the Mr. Stahl offered various technology presentation and manufacturing Corporate Research Department. A examples and insight and processes area”. The talk gave some insights of few questions came up as examples. which enabled different applications the various possibilities of manufac- Here, it was emphasized that OEMs which are state-of-the art today. Fur- turing available in Reutlingen and in use Power Modules, i.e. inverters thermore, he concentrated on the future also in Dresden´s 300 mm fab. from Bosch for electric cars. needs, where are the hidden aspects An impressive video presenting the The day continued with a talk of and needs to enable MEMS for mass clean room facilities closed the talk. Markus Sonnemann, Vice President production. Afterwards, Ali Aboosaidi from and Head of the predevelopment It was followed by a session of the IEEE YP Germany AG gave an of MEMS, followed with the title workshops and presentations with overview of the activities of the YP in “MEMS—enabling technology for fu- possible job advertisements. Germany. Organizing events and fo- ture mobility solutions pushing the Here, Tobias Hanke from the wa- cusing on exchange/ networking with limits of MEMS”. Here, Mr. Sonnemann fer level test development gave an other YP groups. gave a lot of examples of sensor im- overview of the custom development The event continued with more in- provements by technology and the for MEMS technology in the talk sight by Frederik Schrey from the in- success of predevelopment. “MEMS wafer test”. Various examples tegrated circuit domain of Bosch who The morning session ended with were shown, which emphasized that gave a talk “ASICs and Semiconduc- presentations and experiences of MEMS were non-standard in various tor Technologies for Bosch Systems”. the human resources director Florian domains and showed how to tackle Here, Mr. Schrey concentrated on Schueller and Ulrich Baehr, a former test equipment and test conditions. a portfolio overview and the future Bosch PhD student. Both shared in- Afterwards, Mirko Hofmann, di- possibilities with the 300 mm fab in sights of their Bosch career and of- rector of the MEMS design house, Dresden. fered also entry opportunities. Here, gave a talk entitled “MEMS Design

January 2021 ❍ IEEE Electron Devices Society Newsletter 49

28neds01_Final_DigitalOnly.indd 49 1/20/21 11:17 AM House—Design & Simulation”. Mr. He gave some examples, i.e. on laser modules department, offered more Hofmann concentrated on the princi- dicing and automized pick up tools, to insights in power electronics and pal transducer design and optimiza- overcome these challenges. electrical drives which can vary from tion. He highlighted the challenges After the various insights in tech- a few kilowatts up to several mega- of tolerances, cross coupling and nology, Matthias Laemmlin from watts. Also, he concentrated on the environmental influences caused by Bosch Sensortec gave a talk on SiC development in Reutlingen and the impact of packaging, which need “MEMS Sensors for Consumer Elec- showed finally an impressive video to be considered during the design tronics”. Mr. Laemmlin showed the of overload failures during testing phases prior to the mass production. new solutions of smart sensors, in- and how to actively handle short cir- Ronald Gampp, the director of the cluding embedded algorithms for cuit overload. packaging department gave a talk artificial intelligence for sensors. Fur- The event ended with some final “MEMS Packaging”. He gave more thermore, he gave an overview on conclusion and thanks to all partici- insights on the main concern of me- applications of sensors nowadays. pants and presenters for their active chanical stress induced on the MEMS Finally, Josef Goeppert, direc- contributions and questions during element, which itself is mechanical. tor of power semiconductor and the day.

Did You Know? IEEE and EDS provide temporary Open Access to top papers from the IEEE Electron Device Letters (EDL) and the IEEE Journal on Microelectromechanial Systems (J- MEMS). Every month, EDL Editors select a small number of particularly remarkable articles as Editors' Picks. These are highlighted on the issue cover and enjoy temporary (one month) Open Access. One of these articles is further selected as Cover Article and prominently featured in its main cover graphics. Visit the EDS website for links to the current EDL Editors' Picks. Stay up to date with the latest developments in the MEMS areas with IEEE RightNow Access for J-MEMS. Enjoy temporary Open Access (3 months) to select featured papers from the latest J-MEMS edition. New selections are available quarterly. Join us on social media to receive release announcements.

50 IEEE Electron Devices Society Newsletter ❍ January 2021

28neds01_Final_DigitalOnly.indd 50 1/20/21 11:17 AM C HAPTER N EWS

IEEE UKRAINE SECTION (WEST) MTT/ED/AP/EP/SSC JOINT CHAPTER DIPED-2020 SEMINAR/WORKSHOP DEDICATED TO THE MEMORY OF PROF. NIKOLAI VOITOVICH BY MYKHAYLO ANDRIYCHUK

On September 15–18, the area of electromag- scientists of Eastern Europe and the 2020, the 2020 IEEE netic field propagation Former Soviet Union (FSU) countries XXVth International and antenna theory, and in the worldwide scientific commu- Seminar/Workshop on a multitalented respect- nity, as well as due to the efforts of Direct and Inverse Prob- ed person who passed Prof. Voitovich, the IEEE West Ukraine lems of Electromagnetic away this year at the age Joint Chapter was established. It and Acoustic Wave The- of 80. was one of the first IEEE Chapters ory (DIPED-2020) took Nikolai Voitovich grad- in Ukraine and in the FSU countries. place in Tbilisi, Georgia. uated from Lviv State Initially, the Chapter joined the IEEE The event was co-orga- University in 1961 with Electron Devices and Microwave nized by the IEEE MTT/ Master Degree in Com- Theory & Techniques Societies, and ED/AP Georgia Chapter, putational Mathemat- one year later the IEEE Antennas & Tbilisi State University, Prof. Nikolai Voitovich ics, earned his Ph.D. Propagation Society. The next devel- Ukraine Section (West) (1940–2020) in Radio Physics from opment of the Chapter was joining MTT/ED/AP/EP/SSC the Institute of Radio the IEEE CPMT (now Electronic Pack- Joint Chapter, and Pidstryhach Insti- Engineering and Electronics (IRE), aging) and SSC Societies in 1997 and tute for Applied Problems of Mechan- Moscow, Russia, in 1968, and re- 1999, respectively. The first years of ics and Mathematics, NASU, with the ceived his D.Sc. in Radio Physics the West Ukraine Chapter with Prof. support of the IEEE Electron Devices, from Kharkiv State University in Voitovich as a Chapter Chair were Microwave Theory & Techniques, and 1982. His D.Sc. work “Investigation filled with fruitful and impressive Antennas & Propagation Societies of high-quality resonators and di- work. In 2000, Chapter won the IEEE as the technical co-sponsors. The electric waveguides by means of CPMT 1999 Chapter of the Year Award DIPED-2020 was dedicated to the generalized eigenvalue problems” being one of the first among the IEEE memory of Prof. Nikolai N. Voitovich, was considerable contribution to the Chapters from Eastern Europe and the founder of the first IEEE EDS well-known generalized method of FSU countries earning such a recog- Chapter in Ukraine and co-organizer eigen-oscillations (GMEO), which is nition. That boosted further develop- of the DIPED Seminar/Workshop se- successfully applied to solving the ment of the Chapter’s activity and its ries. This year’s technical program series of internal and external prob- improvement both scientifically and consisted of 32 papers submitted by lems of Electrodynamics. technically, especially in the areas scientists from Georgia, Germany, Prof. Voitovich contributed signifi- related to the parent IEEE Societies. Greece, Israel, Turkey, Russia, USA, cantly to international scientific co- So the next awards were not long and Ukraine, and covered the follow- operation. Thus, starting in 1982, the in coming. In 2001, the Chapter was ing sections: Diffraction and Scatter- scientific forum in the field of high recognized by the 2001 IEEE Region 8 ing, Propagation in Complex Media, frequency Electrodynamics with par- Chapter of the Year; in the second de- Numerical and Optimization Tech- ticipants from Georgia, Poland, Rus- cade of 2000s, the Chapter won the niques, Antenna Design, Fabrication sia, and Ukraine, was originated. Due IEEE Antennas and Propagation Soci- and Testing, Acoustics. to his enthusiasm, the forum took the ety 2017 Outstanding Chapter Award, At the Opening Ceremony, Dr. title “Direct and Inverse Problems of IEEE Electron Devices 2017 Region 8 Mykhaylo Andriychuk, Program Electromagnetic and Acoustic Wave Chapter of the Year Award, and IEEE Committee Secretary, presented the Theory (DIPED)” and became the Microwave Theory and Techniques memory talk about the life stages annual IEEE International Seminar/ Society 2017 MTT-S Outstanding and scientific achievements of Prof. Workshop afterwards. In 1995, ow- Chapter Award. And it is impossible Voitovich, a famous scientist in ing to the IEEE initiative for involving to overestimate the role, efforts, and

January 2021 ❍ IEEE Electron Devices Society Newsletter 51

28neds01_Final_DigitalOnly.indd 51 1/20/21 11:17 AM eagerness of Prof. Voitovich, Theory of Resonant Scattering permanent honorary Chapter and its Application in Radio- Chairman, which always were physics.’’ The memory paper of crucial factors in winning the Prof. Voitovich prepared by his above mentioned awards. Georgian friends and follow- The cooperation with the IEEE ers from Ukraine was included helped to renew the DIPED into the DIPED-2020 Proceed- and make it the annual Semi- ings. The scientific results of nar/Workshop as a joint event his research over the last year’s of both the MTT/ED/AP/EP/ period were presented in two SSC West Ukraine and MTT/ research papers of the above ED/AP/EMC Georgian Chap- Proceedings. Thus, improving ters since 1995. In 1997, the the Chapter activity and car- DIPED became an IEEE event, rying on the traditions of the technically co-sponsored by DIPED Seminar/Workshop will AP, ED, and MTT Societies, be a good remembrance of that enabled the inclusion of Prof. Voitovich who was the DIPED Proceedings into the founder of these both projects. IEEE Xplore Digital Library. This year, the DIPED Semi- The credit for successfully nar/Workshop was arranged holding all DIPEDs is owed online. Prof. Revaz Zaridze, largely to enthusiasm, organi- Organizing Committee Chair- zation efforts, and permanent Dr. Tamar Nozadze, Organizing Committee Secretary, serving the man, Dr. Tamar Nozadze, Orga- care of Prof. Voitovich. DIPED-2020 online sessions nizing Committee Secretary, The scientific results of Dr. Tamar Gogua, responsible Prof. Voitovich are very impressive. 1989, Prof. Voitovich together with his person of the Tbilisi State University, He is the author of 9 monographs, teacher, Prof. Katsenelenbaum and and whole team of our Georgian col- more than 190 papers in the interna- other authors of the GMEO, were rec- leagues did their best to make the tional scientific journals and confer- ognized by the Ukrainian State Award DIPED-2020 successful. ence proceedings. His research works in the Area of Science and Technique gained recognition worldwide. In for the series of scientific papers “The ~Kateryna Arkhypova, Editor

TEC COSTA RICA RECIPIENT OF THE 2020 IEEE ELECTRON DEVICES SOCIETY STUDENT BRANCH CHAPTER OF THE YEAR AWARD

IEEE EDS Student Branch located Costa Rica, the country of There was a lot of work to do Chapter Instituto Tecnológico ¡Pura Vida! and Gallo Pinto, famous ahead. As a new chapter, we didn’t de Costa Rica for its beaches, volcanos, biodiver- have a web page, social media, where * Esteban Arias-Méndez, Chapter Ad- sity, and culture. With a population we could spread the news of the activ- visor and Student Branch Counselor of just 5 million people in 51 000 km2. ities, and logo that represented us. So * Danny Xie-Li, Chapter Chair and The IEEE EDS Student Branch we set a starting rock of the chapter. Student Branch Chair Chapter from Instituto Tecnológico We planned some activities at the uni- de Costa Rica (Costa Rica Institute of versity to start as the chapter. In the From Latin America, in Central Ameri- Technology) or TEC Costa Rica, was last week of February 2020, we were ca, Nicaragua to the north and Pan- founded in January, 2020 by 10 stu- invited to the LAEDC Costa Rica con- ama to the south, surrounded to the dents, some of them with previous ference, where we had the opportuni- east by the Caribbean Sea and to the IEEE volunteering experience and ty to meet many people from different west by the Pacific Ocean there is some new. parts of the world, some people from a

52 IEEE Electron Devices Society Newsletter ❍ January 2021

28neds01_Final_DigitalOnly.indd 52 1/20/21 11:17 AM local industry, and distinguished peo- ing a large number of international the community through our Tele- ple in the field. Later, we invited some attendees. Talks like: “An Introduction gram group chat and social networks of them to share their knowledge with to Open Source Hardware Develop- on Facebook and Instagram. Nowa- the students within our own activities. ment Leveraging Open Source Soft- days, chat apps and social networks As time went by, the pandemic hit our ware Workflows,” “Cybersickness,” are central to good communication. country. That time we had to cancel “Design Thinking”; participation in the For the coronavirus outbreak, these all the activities we had organized be- IEEE UN SDG week organized by the channels were the key for us to easi- cause most of them were face-to-face Student Branch at TEC Costa Rica and ly and quickly move to virtual events. activities, like workshops. even a programming competition Members development should be called “Electron CodeWars” was or- the goal of the chapter, and, to achieve Face-to-Face to Virtual ganized by the chapter members. that, you need good communication As a result of the COVID-19 pandem- channels with them. We encourage ic, the activities could not be tours or Be a Volunteer, a Way to Build a volunteers to organize and develop lectures and face-to-face workshops, Better Tomorrow their own ideas and activities, so they among others. We had to innovate We like to welcome EDS and IEEE can learn by doing, which can im- and bring everything to virtuality. members in our activities as well as prove them academically and profes- We restarted with the talk: “You at people from the community interest- sionally in the near future. If you want home and your mental health with ed in them. The synergy that this gen- to succeed with activities, it’s good to you,” from the Department of Guid- erates can achieve a great impact in have a person in charge and provide ance and Psychology, as a way to re- the world that can last forever. This is support and follow up on time. connect with members and the TEC a motivation for the members to keep Social activities such as virtual community in the middle of times going. If you want to change the world board games are spaces where peo- of uncertainty. you need to put one step in the road. ple can have the opportunity to de- In the end, the virtuality became stress and to meet new friends. In an advantage, because it allowed us Some Recommendations, from other words, make social distance a to invite distinguished national and Our Chapter to Yours social approach in this virtual age. international speakers, which would We like to have constant communi- Work with other student branch- not be possible in person, not count- cation with chapter members and es and student chapters around the

Some EDS Student Branch Chapter members, TEC Costa Rica

January 2021 ❍ IEEE Electron Devices Society Newsletter 53

28neds01_Final_DigitalOnly.indd 53 1/20/21 11:17 AM world to have the opportunity to col- are many talented young people at • Fiscal: Fabián Montero-Villalobos laborate and meet their culture and TEC and we seek to harness all that • Secretary: David Azofeifa-Herrera way of thinking, is relevant for the knowledge to benefit the country. • Treasurer: Mariana Vargas- growth of the person’s thinking for all We face a difficult time this year. Ramírez the society members. The pandemic hit us in different • Vocal 1: Eduardo Quiroga-Alfaro We believe that one of the main ways. Somehow and somewhat you • Vocal 2: Erick Quesada-Fonseca benefits you get as a member is the can start to think that it is the end of • Advisor: Esteban Arias-Méndez possibility to get in contact with peo- everything, but we should take the ple from all over the world, like right pandemic as a challenge, that could Social Media now. And the chapters have to serve make us stronger to face the future. • Facebook: https://www.facebook as connection points, as it provides Stay tuned to our social media, the .com/EDSTECCR extra value for members. best is yet to come. Warm greetings • Instagram: https://www.instagram COVID-19 has affected our regular from Costa Rica, ¡Pura Vida! .com/eds.ieee.tec/ activities worldwide, but also it has been a trigger to get in touch with peo- EDS Student Branch Chapter Contact ple everywhere, and both share, and Board of Directors 2020 * Esteban Arias-Méndez, Advisor, be a part of activities in other countries. • Chair: Danny Xie-Li email: [email protected] Our main interest is to promote sci- • Vice chair: Alejandro Díaz- * Danny Xie-Li, Chair. email: ence, technology, and research. There Pereira [email protected]

EDS CARES: FACE MASK LOOP EXTENDER AND FACE SHIELD FOR SMK 18 SHAH ALAM MUSLIMAH STUDENT AND TEACHERS

Dr. Maizatul Zolkapli and Dr. Ahmad Sabirin Zoolfakar from Universiti Teknologi MARA (UiTM) organized a community program in conjunction with the reopening of school sessions throughout Malaysia after the conditional movement control order (CMCO). Concerned about the students’ wellbeing, especially the female students who wear hi- jab, the pair together with the staff of Electrical Engineering Faculty of EDS members volunteering during the COVID-19 pandemic UiTM utilized their expertise and facilities of available 3D printers faces and at the same time com- shields were handed over to Tuan to produce face mask loop extend- ply with the guidelines set by the Haji Kamali bin Murid, Principal of ers and face shield brackets. It be- Ministry of Education Malaysia. All Sekolah Menengah Kebangsaan comes easier for female students the 560 pieces of face mask loop Seksyen 18 Shah Alam for the use and teachers to put masks on the extenders and 120 pieces of face by students and teachers.

54 IEEE Electron Devices Society Newsletter ❍ January 2021

28neds01_Final_DigitalOnly.indd 54 1/20/21 11:17 AM R EGIONAL N EWS

EUROPE, MIDDLE (TFTs). He discussed direct methods The 2020 IEEE ED Germany Chapter to extract model parameters in the MQ “Non-conventional Devices and EAST & AFRICA temperature range from 150K to 350K. Technologies“ was held from Sep- (REGION 8) The talk “Nanometrology using tember 30th to October 1st, 2020. It MEMS/NEMS devices” was delivered was organized jointly with the Spring ED Poland Distinguished by Prof. Teodor Gotszalk from Wroclaw MOS-AK Workshop and the Sym- Lecturer Mini-Colloquium University of Technology, Poland. The posium on Schottky Barrier MOS —by Krzysztof Górecki speaker presented numerous exam- (SB-MOS) devices (see the separate ples of solutions developed mainly by article). The MQ was attended by A virtual EDS Distinguished Lecturer his team for atomic force microscopy, 71 participants, with 23 IEEE par- (DL) Mini-Colloquium “Semiconduc- scanning thermal microscopy, pho- ticipants and 48 guests. Prof. Mike tor-based sensors—technology, mod- tonics and related disciplines. Schwarz opened the Minicolloquium eling, applications” was held on June The lecture “Phase change elec- as the ED Germany Chapter chair. 27, 2020. It was organized by the ED Po- tro-optical devices for space applica- The first lecture was given by Prof. land Chapter with technical support by tions” was delivered by Prof. Mina Benjamin Iniguez from Universitat the Lodz University of Technology. The Rais-Zadeh (DL) from NASA Jet Pro- Rovira i Virgili on the topic “Analysis meeting consisted of five lectures and pulsion Lab., California Institute of and modeling of OTFTs and IGZO was attended by more than twenty re- Techn., USA. The speaker shared her TFTs from 150 to 350K”. Prof. Iniguez searchers and Ph.D. students. expertise in the area of phase change reviewed recent results regarding the The lecture “Ultralow Power, High- materials for photonics and RF ap- modeling of OTFTs and IGZO TFTs Resolution Sensor Interfaces” was plications. She presented advanced and their benchmarking with mea- given by Prof. Arokia Nathan (DL) concepts of GeTe application for real- surements. Different aspects of the from Cambridge Touch Technologies, ization of electro-optical devices with metal-insulator-semiconductor struc- UK. Prof. Nathan addressed the de- application in Space. ture, facile manufacturing, compat- sign and operational requirements of ibility with flexible substrates were vacuum deposited and printed thin ~Marcin Janicki, Editor discussed. A comparison of carrier film transistors for wearable applica- mobilities in OTFTs and IGZO TFTs tions in which low power and high Germany Chapter Presents was also discussed. signal resolution are critical require- IEEE EDS Mini-Colloquium on Prof. Joachim Burghartz from IMS ments, especially for detection of “Non-Conventional Devices and Chips gave a lecture “Ultra-Thin Si physiological signals. Technologies“ Chips—A New Paradigm in Silicon The talk “Sensor Design—From —by Mike Schwarz Technology”. He broadly discussed Prototype to Series” was delivered by Dr. Mike Schwarz from Robert Bosch GmbH, Germany. The speaker presented a flow and methodology of integration of all the sensor per- spectives, from prototyping to series production. He discussed examples of typical Sensor/MEMS designs including various mechanical and electronic constraints. The lecture “Compact Modeling and Parameter Extraction for Oxide and Organic Thin Film Transistors (TFTs) from 150K to 350K” was given by Prof. Benjamin Iñíguez (DL) from Universitat Rovira i Virgili, Spain. He made a review of the physics and of DC, AC and noise modeling of Or- Prof. Joachim Burghartz during the lecture “Ultra-Thin Si Chips—A New Paradigm ganic and Oxide Thin-Film Transistors in Silicon Technology.”

January 2021 ❍ IEEE Electron Devices Society Newsletter 55

28neds01_Final_DigitalOnly.indd 55 1/20/21 11:18 AM the advantages and challenges of ultra-thin silicon chips. Special focus was given to the piezoresistive effect and its benefits for eliminat- ing temperature effects and vertical stress impact. Dr. Wladek Grabinski from MOS- AK presented a talk “FOSS TCAD/ EDA Tools for Advanced Compact Modeling.” He gave an overview of existing open source tools for process- and device simulation including SPICE-family tools, and mechanical FEM simulators. Next Dr. Frank Schwierz from TU Ilmenau gave a very detailed lecture “2D Electronics—Opportunities and Challenges.” After an introduction of 2D materials, including a discussion Discussion after the talk by Prof. Walter Weber of bandgaps of different 2D semicon- ducting materials, a comparison of their effective masses and the effects to the COVID-19 pandemic. How- who presented a collaborative work of direct source to drain tunneling ever, finally the local organizers of with IMS Chips “Modeling of GaN and its suppression were discussed. NanoP—Competence Center for HEMTs on Silicon Substrate”. Then The final lecture was given by Nanotechnology and Photonics of Lixi Yan from University of Stuttgart Prof. Tibor Grasser from TU Vienna on THM decided to move it to Zoom presented a work “Adopting the In- “Stability and Reliability of 2D Tran- and perform it virtually. It was spon- dustry-standard CMOS Models for Si sistors”. Prof. Grasser addressed ma- sored by THM, the EDS Germany Vertical Power MOSFETs”. terial properties, discussed the typical Chapter, the IEEE Young Profession- The first day was closed after a cof- defects, oxygen vacancies, and their als Germany Affinity Group, and the fee break by a talk “Overview of Gnu- impact on the charging behavior. Fi- AdMOS company. The event was at- cap, the GNU Circuit Analysis Package” nally, effects such as the impact of tended by 69 IEEE members and 115 presented by Al Davis from Gnucap charge defects were discussed. non IEEE members (guests) from 25 Team (USA) and by Axel Fischer from A huge “Thank you” to all the par- countries during the three days. SweepMe! team (Germany) with a talk ticipants and lecturers. The event started with the MOS- “SweepMe!—a modular, flexible, and AK workshop. It was opened by Dr. versatile software platform for device Joint Spring MOS-AK Workshop Wladek Grabinski and Prof. Alexander characterization”. and Symposium on Schottky Kloes. The first presentation was The second day continued with Barrier MOS (SB-MOS) Devices given by Dr. Markus Mohr from Ulm the MOS-AK and a talk “Injection Bar- with IEEE EDS Mini-Colloquium University and entitled “Fabrication rier Modification by Organic Mono- on “Non-Conventional Devices and Application of Nanocrystalline layers” by Dr. Alrun Hauke from and Technologies” Diamond Thin Films and Hybrid Dia- Philipps-Universität Marburg. It was —by Mike Schwarz mond-Silicon Sensor Applications”. followed by a presentation “Quanti- After a short coffee break the tative Investigation of the Interplay The Joint Spring MOS-AK Work- event continued with a talk by Aris- between Intrinsic Transistor Noise shop and Symposium on Schottky teidis Nikolaou from THM on the topic and Circuit Nonlinearities” given by Barrier MOS (SB-MOS) devices “Statistical circuit analysis by NOVA Leopold Van Brandt (UC Louvain). with IEEE EDS Mini-Colloquium on (Noise Based Variability Approach)”. The MOS-AK was closed by the “Non-conventional Devices and It was followed by an overview pre- talks of Dr. Ghader Darbandy and Dr. Technologies” was held from Sep- sentation by Prof. Alexander Kloes Mike Schwarz. Dr. Darbandy present- tember 29 to October 1, 2020. While entitled “Approaches for analytical ed the work “Emerging Devices: RFET it was initially planned for spring (compact) modeling of tunneling cur- and OPBT”. Dr. Schwarz discussed at THM—University of Applied Sci- rent in MOS transistors”. methodologies for high volume ences in Giessen (Germany), it was The afternoon session was opened productions in a lecture “Simula- shifted to the early autumn due by Mahimna Dwivedi from AdMOS tion and Modeling of Semiconductor

56 IEEE Electron Devices Society Newsletter ❍ January 2021

28neds01_Final_DigitalOnly.indd 56 1/20/21 11:18 AM Devices in MEMS”. The MOS-AK was finally attended by 73 participants. After the lunch, Dr. Schwarz opened as German Chapter chair the IEEE MQ “Non-conventional Devices and Technologies” (see a separate detailed article). After the Mini-Colloquium, the 4th Symposium on Schottky Bar- rier MOS Devices was opened with some historical remarks by Prof. Mike Schwarz and Dr. Laurie Calvet. Then they introduced the first speaker Dr. Zhenxing Wang from AMO GmbH. Dr. Wang gave a talk “Metal- Insulator-Graphene RF Diodes: From Devices to Integrated Circuits”. After- Schematic representation of a pressure sensor based on a suspended graphene wards, Dr. Laurie Calvet from Uni- membrane (Image: S. Wagner @ AMOGmbH) versite Saclay Paris presented a talk “Schottky barrier devices for neuromorphic computing”. first journal in the Science Partner noelectromechanical sensors, since After a coffee break Prof. Walter Journal (SPJ) program. The paper is the performance is often crucially Weber from TU Vienna gave some in- an “Invited Paper” for a special edi- dependent on the thickness of the sights on heterostructures during the tion entitled “Progress and challeng- suspended component. In addition, presentation entitled “Nanowire met- es in emerging 2D nanomaterials many 2D materials have unique elec- al-semiconductor heterostructures preparation, processing and device trical, mechanical and optical proper- for functionality enhancement and integration” with the aim of devel- ties that can be used for completely quantum transport”. Finally, Dr. Hans oping the area of 2D materials for new concepts of sensor devices.” Kleemann from TU Dresden pre- sensor applications and integrating The report contains contributions sented a lecture “Schottky-type Con- them into conventional semiconduc- from RWTH Aachen, AMO GmbH, the tacts in Ultra-Short Channel Organic tor technology to contribute. University of the Bundeswehr in Mu- Semiconductor Devices for GHz-Op- “I believe that NEMS sensors nich, the KTH Royal Institute of Tech- eration”. The Symposium on SBMOS based on 2D materials will make a nology, TU Delft, Infineon and the was attended by 40 participants. significant contribution to meeting Kavli Institute of Nanoscience. Differ- Finally, the organizers Prof. the demand for integrated, high- ent readout and integration methods Alexander Kloes, Dr. Wladek Grabinski, performance sensors that result from of different sensors based on the 2D Dr. Laurie Calvet, and Prof. Mike Schwarz applications such as the Internet of materials are discussed here, and thanked all presenters and participants Things (IoT) and autonomous mo- they offer comparisons with the state for this fantastic event. All of you made bility,” said Lemme. The report sum- of the art to demonstrate both chal- it happen! marizes extensive studies that have lenges and opportunities of the nano- successfully demonstrated the fea- electromechanical sensors based on Nanoelectromechanical sibility of using membranes made the 2D materials. Sensors Made of 2D Materials— of 2D materials in pressure sensors, “Sensor devices based on float- an Overview microphones, mass and gas sensors, ing 2D materials are almost always —by Frederica Haupt and explains different sensor concepts smaller than their conventional coun- Mike Schwarz and gives an overview of the rele- terparts, have improved performance vant material properties, production and sometimes even completely Max Lemme with collaborators methods and functional principles of new functionalities,” says Peter G. published recently in the magazine the devices. Steeneken, head of work package 6 RESEARCH an overview article on “Two-dimensional materials are (sensors) in the Graphene flagship nanoelectromechanical (NEMS) sen- ideal for sensors,” says Lemme, “be- and the co-author of the contribution. sors based on floating two-dimen- cause they allow free-standing struc- “However, there are still enormous sional (2D) materials. RESEARCH is tures to be realized that are only a few challenges to show that NEMS sen- a multidisciplinary open access jour- atoms thick. This ultimate thinness sors based on 2D materials can out- nal that was launched in 2018 as the can be a decisive advantage with na- perform conventional devices in all

January 2021 ❍ IEEE Electron Devices Society Newsletter 57

28neds01_Final_DigitalOnly.indd 57 1/20/21 11:18 AM important aspects—for example in The 2020 edition included 4 plenary tum computing: Quantum Annealing, establishing profitable manufactur- talks and 53 regular contributions: 34 Approximate NISQ-Computing, and ing options. The graphene flagship “oral” and 19 “poster” presentations. Fault-tolerant Universal QC. Inside of represents the ideal platform to ad- Pre Recorded videos/commented an IBM Q quantum computing sys- dress these challenges as it encour- slides of each paper (oral or poster) tem (see Figure) were discussed for ages collaboration between leading presentations were available in the various temperature regimes. Dis- global groups to achieve a number respective thematic channels. Dis- cussions on quantum volume (cal- of clearly defined goals. This paper is cussions took place on the general culation score) took place, where the an example of how we can do more or thematic channel (recommended) error rate stands as a dominating is- by bringing together complemen- or as direct conversations with the sue in combination with the number tary expertise.” presenters/authors of the papers of qubits. presented at EuroSOI-ULIS 2020. Afterwards, operation, control 6th Joint EuroSOI—ULIS 2020 A live presentation was arranged and scalability were discussed. Top- Conference only for the first plenary talk of Ce- ics such as Quantum Gates, IBM qu- —by Bogdan Cretu and Mike zar Zota (IBM, Zurich, Switzerland). bits by Josephson qubits/junctions Schwarz Prerecorded video presentations and oscillators were highlighted. of the plenary talks were proposed Additionally, the talk emphasized The 6th joint EuroSOI—ULIS 2020 by Prof. Eddy Simoen (imec, Leu- the typical architectures. Here, the Conference was held from Septem- ven, Belgium), Prof. Jung-Hee Lee focus was especially set to electron ber 1st−30th. Because of COVID-19 (Kyungpook National University, devices for different temperature re- situation, the EuroSOI-ULIS 2020, South Korea) and Prof. Mark Lund- gimes. Generally, electronics in the initially planned to be held at Caen strom (Purdue University, Indiana, cryogenic regime is demanded, e.g. (Normandy, France), became a virtu- USA). The participants could see the logic controllers, signal generators, al conference. The next 2021 edition presentations in advance, and dur- ADCs, LNAs, etc. Furthermore, III-V will be at Caen (Normandy, France) ing the provided time slots only the materials for cryogenic electronics on September 1st−September 3rd, key points of the different presenta- were discussed. and the EuroSOI-ULIS 2022 will take tions were reminded for discussion/ Finally, novel cryogenic devices place at Udine (Italy). exchanges to take place. and materials were introduced. Here, Each year this international confer- The first plenary talk of EuroSOI— important parameters such as the ence brings each year together more ULIS entitled “Novel Electron Devices transconductance in the cryogenic re- than 100 expert researchers in semi- for the Quantum Era” was delivered gime and self heating were in the fo- conductor technologies. This year 75 by Dr. Cezar Zota from IBM Zurich. cus. Especially, the self heating at the participants from 4 continents (Europe Dr. Zota gave a great talk to 33 at- cryo regime is responsible almost in (50 from 11 countries), Asia (10 from 4 tendees during the live session. He 50% for the on-chip temperature. countries), South and North America introduced the participants into the The second plenary talk of Eu- (12 from Brazil and 2 from USA), Aus- Quantum computing topic at IBM. roSOI—ULIS entitled “Horizontal, tralia (1)) attended the conference. He discussed various types of quan- stacked or vertical silicon nanowires: does it matter from a low-frequency noise perspective?” was delivered by Prof. Eddy Simoen from IMEC. Prof. Simoen held a Question and Answer session to 20 attendees during a live session of his recorded talk. In this very interesting talk, Prof Eddy Simoen firstly reminded the audience the basics of 1/f noise and its mechanisms. He showed that the device scaling leads to an increase of the device-to-device 1/f noise disper- sion, while the average value could remain the same. A relationship between the 1/f noise and the device architecture, i.e. Plenary talk “Novel Electron Devices for the Quantum Era” was held in MS Teams horizontal NW FETs on SOI, stacked by Dr. Cezar Zota from IBM Zurich NW FETs and vertical NW FETs was

58 IEEE Electron Devices Society Newsletter ❍ January 2021

28neds01_Final_DigitalOnly.indd 58 1/20/21 11:18 AM discussed. It was pointed out that the Due to a very good electrostatic con- Ioff ratio, these devices are promising mechanism responsible for the 1/f trol, low drain saturation voltage, for low voltage logic applications. noise is the carrier trapping/detrap- low threshold voltage and good sub- The fourth plenary talk entitled

ping (carrier number fluctuations) in threshold characteristics with high Ion/ “Reflections on the Past, Present, and the horizontal NW FETs on SOI and stacked NW FETs, while in the vertical NW FETs the mobility fluctuations prevail. Ways to optimize the 1/f noise level in horizontal NW FETs on SOI were debated, however, it was pointed out that the stacked NW FETs present one decade lower noise than horizontal NW FETs on SOI substrates. Even if the 1/f mechanism is different in the vertical nanowire FETs, the advantage of this architecture from the noise point of view is that it presents a decade lower surface normalized 1/f noise than the stacked NW FETs. The third plenary talk “Fabrication Prof. Eddy Simoen answering questions during his plenary session on “Horizontal, stacked or and characterization of GaN-based vertical silicon nanowires: does it matter from a low-frequency noise perspective?” nanostructure field-effect transistors (FETs)” was given by Prof. Jung-Hee Lee (Kyungpook National University, South Korea). Prof. Lee reminded the importance of III-V based devices for RF and power application, and the critical issues of this III-V technology, e.g. trapping effects leading to a decrease of the output current, and possible ways to improve the device performance. It was argued that the GaN-based Fin- FETs or NW FETs show a suppression of a buffer trapping and reduction of an off-state leakage current, and present fast switching characteristics. The fabrication steps and performances of AlGaN/GaN-based Fin- Plenary talk “Novel Fabrication and characterization of GaN-based nanostructure field-effect transistors (FETs)” was held in MS Teams by Prof. Jung-Hee Lee FETs and GAA GaN vertical nanowire from Kyungpook National University MOSFETs were presented in detail. It was pointed out that using the concept of channel width modulation and simultaneous turn-on, fast switching characteristics with subthreshold swing below the theoretical limit for diffusive transport (60 mV/dec) may be achieved in AlGaN/GaN-based FinFETs. It was highlighted that the device simulation with a multi-level trap model and a self-heating effect reproduces the transfer characteristics of the GAA Plenary talk “Reflections on the Past, Present, and Future of Device Research” was held in MS GaN vertical nanowire MOSFETs. Teams by Prof. Mark Lundstrom from Purdue University

January 2021 ❍ IEEE Electron Devices Society Newsletter 59

28neds01_Final_DigitalOnly.indd 59 1/20/21 11:18 AM Future of Device Research” was giv- Driven Research on Solar Powered 12–21. VLSI was scheduled from June en by Prof. Mark Lundstrom (Purdue Mobility.” Finally, Prof. Magali Estra- 10–14 while the virtual meeting was University, Indiana, USA). da (CINVESTAV, Mexico) talked about available until the end of August. In the visionary presentation, Prof. “Fundamentals of bulk heterojunc- All presentations were available in Lundstrom reminded the past and re- tion organic solar cells: An overview pre-recorded videos, with live Q&A cent evolution of devices and pointed of main parameters, state of the art sessions provided for speakers and out the essential physics of transis- and strategies for improvement.” authors. In order to promote both tors and the transport theory for the activities, the chapter asked experts 21st Century. ~ Mike Schwarz, Editor who participated in both conferences In a very pedagogic way, Prof. to present several major research of Lundstrom explained the electron interest topics for the conferences. SIA ACIFIC transport, the current flow in a nano A & P Six topics were presented: device, the “Fermi window,” the op- (REGION 10) 1) AI and Memory (T. H. Hou), eration at 0K, and the quantized 2) 3D Packaging and conductance. He elaborated on the ED Taipei Chapter Heterogeneous Integration, transport equation in bulk semicon- —by Steve Chung 3) Advanced CMOS ductor, and in the nano-scale to the Manufacturing, macro-scale devices. A Post-Conference Review of 4) Quantum Computing for Several open questions: “Is there 2020 SNW and 2020 VLSI Electrical Engineers (P. W. Li), a new device that will invent its own The ED Taipei Chapter together with 5) Ferroelectric FETs and 2D applications?”, “How do we prepare the EDS NCTU Student Chapter held Materials Devices (C. J. Su), students and working engineers to a one–day workshop on July 10th, 6) Selected Papers from SNW succeed in the 21st Century physical giving post-conference reviews of (K. S. Chang-Liao). electronics?” animated the wonder- the virtual 2020 IEEE Silicon Nano- Three of the six speakers were Dis- ful discussion. The key problematics electronics Workshop (SNW) and the tinguished Lecturers (Profs. P. W. L, H. and concepts of single-electron de- 2020 Symposium on VLSI Technology C. Lin, and K. S. Chang-Liao). The pro- vices were debated. (VLSI). The SNW was initially sched- gram began with Prof. Steve Chung uled from June 12–13 and was avail- giving a brief status of both the SNW Virtual Mini-Colloquium (MQ) able in a virtual format from June and VLSI, and providing an overview on Photonics and Photovoltaics —by Benjamin Iniguez and Mike Schwarz

A Virtual Mini-Colloquium (MQ) on Photonics and Photovoltaics was organized by the ED Spain Chapter, in collaboration with the Department of Electronic, Electrical and Automatic Control Engineering of the Univer- sitat Rovira i Virgili (URV, Tarragona, Attendees of the workshop Spain). It took place on July 31, 2020. The Chair of this MQ was Prof. Benjamin Iñiguez, Full Professor at URV and Chair of the ED Spain Chapter. The MQ included three talks given by EDS Distinguished Lecturers, addressing different issues related to Photonics and Photovoltaics. Prof. Ioannis Kymissis, Columbia University (NY, USA) targeted “LED and OLED Devices for Biomedical Optics”. Prof. Angèle Reinders (Technical Univer- sity of Eindhoven, The Netherlands) ED Taipei Workshop on July 10th; Chair and speakers: Steve Chung, conducted a lecture entitled “Design- P. W. Li, K. S. Chang-Liao, T. S. Chao, B. Y. Tsui, T. H. Hou

60 IEEE Electron Devices Society Newsletter ❍ January 2021

28neds01_Final_DigitalOnly.indd 60 1/20/21 11:18 AM of the major events of the IEEE Elec- tron Devices Society. He encouraged students to join IEEE and EDS, and instructed them on how to be good writers and presenters in the VLSI. In this workshop, the organizer also invited major IC company leaders to have extensive discussions with professors and students. This talk was attended by more than 130 professors, and graduate students, and by leaders from Science Park semiconductor companies.

2020 VLSI-TSA and VLSI-DAT Symposia Since 1983, the VLSI-TSA and VLSI-DAT VLSI-TSA conference, August 13th: Keynote Q&A symposia are among the major and (speaker: Mark Ritter-IBM) and audience premier events on VLSI technology in the region and worldwide. The 2020 be submitted online: https://expo to smart phones, that have made life VLSI-TSA and VLSI-DAT (https://expo .itri.org.tw/2021vlsitsa/Submission. virtually unrecognizable with regards .itri.org.tw/2020vlsitsa) were held The paper submission deadline is the one 50 years ago. This talk was on August 10–13, 2020. Considering November 9, 2020. For further infor- focused on the physics of operation the COVID-19 pandemic worldwide, mation, please contact Miss Caroline of the MOSFET leading towards pres- i.e., travel restrictions, this meeting Huang, [email protected]. ent day challenges of sub-threshold was held in a hybrid form. An onsite operation. Combining memory with physical meeting was organized on IEEE EDS Distinguished Lecture— CMOS presents one possible path- August 10–13 for all the local par- ED/SSC Nanjing Chapter way for massively parallel and highly ticipants, while pre-recorded pre- —by Weifung Sun energy efficient neuromorphic com- sentations were arranged as a video puting systems of the future. presentation available on-demand The EDS/SSCS Nanjing Chapter co- The webinar was successful with for one-month (August 14-Sept. hosted on July 21, 2020, a webinar by more than one hundred scholars and 13) to all the audience. A majority Prof. Merlyne De Souza, a Full Profes- students attending from all around of the ED Taipei Chapter members sor in Electronics at The University of the world. were involved in the organization of Sheffield (UK) and Distinguished Lec- the conference. Prof. Steve Chung turer of the IEEE Electron Devices So- IEEE EDS Invited Lecture—ED served as the Technical Program ciety. The title of her webinar, “From Tainan Chapter Chair of TSA, responsible for all the CMOS to neuromorphic computing, —by Wen-Kuan Yeh virtual program presentation and the with a peek into the future,” was se- on-site meeting. Both TSA and DAT lected as this research direction has The ED Tainan Chapter held an in- symposia are sponsored by the IEEE been chosen to be one of the top 10 vited presentation at Tainan, Taiwan, EDS, CAS, and SSCS. The symposia priorities by local and national Chi- September 24, 2020. Prof. Kuan-Neng attracted over 840 attendees world- nese governments. Chen (IEEE Fellow, Distinguished wide in the technical sessions and At the heart of the electronics Professor, Department of Electronics more than 350 in a series of short revolution, lies a four-terminal tran- Engineering, National Chiao Tung Uni- courses, in which around 57% were sistor: the humble Metal-Oxide- versity) gave a talk “3D Integration, from the industry and 43% from the Semiconductor Field Effect Transistor Advanced Package, and Heteroge- universities. It was truly a very suc- (MOSFET). Combining p and n type neous Integration” at National Cheng- cessful conference, which benefited MOSFETs forms the basic unit of Kung University. This talk focused from the well-controlled environ- complementary logic that inverts a on the advanced package techno- ment in Taiwan, which was nearly signal from ‘1’ to ‘0’ and vice versa. logy including Interposer, CoWoS, immune to the coronavirus. For your Scaling of this transistor according and InFO for related applications. information, next year the confer- to Moore’s law has had a transfor- About 60 attendees and several pro- ence is scheduled to be held April mative effect on society, giving us fessors of universities from south Tai- 19−22, 2021, in Hsinchu. Papers can products from computers, laptops wan attended to meet Prof. Chen.

January 2021 ❍ IEEE Electron Devices Society Newsletter 61

28neds01_Final_DigitalOnly.indd 61 1/20/21 11:18 AM tokyo/chapter/ED-15/2020/Home/ EDTM2020_ReportSession_en.pdf. The next EDTM (IEEE EDTM-2021), is planned as an in-person/on-site event in Chengdu, China, on March 9–12, 2021. (https://ewh.ieee.org/conf/ edtm/2021/index.html)

The Electron Devices and Solid- State Circuits Online Seminar Series ED/SSC Hong Kong Joint Chapter Prof. Kuan-Neng Chen with members of the ED Tainan Chapter on September 24, 2020 —by Qiming Shao

On April 9, 2020, the first Electron IEEE EDS Invited Lecture—ED On July 27, 2020, the report ses- Devices and Solid-State Circuits Xi’an Chapter sion of IEEE EDS 4th Electron De- (EDSSC) Online Seminar Series was —by Ranran Zhao vices Technology and Manufacturing held online via the Zoom platform. (EDTM) Conference 2020 (http://ewh The EDSSC Online Seminar Series is On September 29, 2020, the ED Xi’an .ieee.org/conf/edtm/2020/) was orga- a new series of seminar talks hosted Chapter held an invited presentation at nized. This year the conference was by the IEEE ED/SSC Hong Kong Joint Xidian University, Xi’an, China. Dr. Eric formatted as a full virtual event. Dr. Chapter. The seminars are normally Liao, the general manager of Payton Kazunari Ishimaru, International Ad- co-organized by one of the local institu- Technology, presented his chip research visory Committee of EDTM-2020, re- tions in Hong Kong, such as the Hong story. Dr. Liao demonstrated the key ported on conference activities and Kong University of Science and Tech- and new technologies of Payton Tech- Dr. Shuji Ikeda explained plans for nology (HKUST), University of Hong nology Company. He also introduced to the EDTM in 2021. Kong (HKU), etc. Due to the pandemic, the students the allocation and applica- At the report session, subcommit- the originally scheduled EDSSC 2020 in tion of memory chips, the design and tee members reported the trends of Hong Kong was canceled. The EDSSC production of packages, and the future their respective technical sessions: Online Seminar Series was initiated to development direction of related tech- • Subcommittee on Si Devices, continue to disseminate research fron- nologies. Eric Liao actively and warmly Dr. Masumi Saitoh (Kioxia). tiers and knowledge to local and near- asked questions and interacted with • Subcommittee on Process, by students. the students, who responded positively Dr. Anupam Mitra (Kioxia). Until now, seven EDSSC seminars and shared their own feedback. • Subcommittee on Model- were held and a few seminars are ing, Prof. Risho Koh (Renesas scheduled for the near future. The The Report Session of Electronics). topics covered 5G, neuromorphic EDTM-2020—ED Japan The program and announcement computing, emerging memory, bio- Joint Chapter of this report session are posted on the electronics, etc. Among the invited —by Toshiro Hiramoto and EDS Japan Joint Chapter’s webpage: speakers there were well-established Masaharu Kobayashi https://www.ieee-jp.org/section/ researchers (e.g., IEEE Fellow Prof. Philip H.-S. Wong from Stanford Uni- versity), newly graduated PhDs (e.g., Dr. Xiang Li from Stanford Universi- ty), or excellent PhD candidates (e.g., Mr. Jiahao Han from Massachusetts Institute of Technology). On average, there were roughly 50 enrollments for each seminar. On July 9, 2020, Prof. Tianling Ren gave an IEEE Dis- tinguished Lecture on “Flexible electronic devices for physiological signal monitoring.” The students exhibited their interest in EDSSC-related top- Dr. Eric Liao presenting at the ED Xi’an Chapter on September 29, 2020 ics, asked questions, and provided

62 IEEE Electron Devices Society Newsletter ❍ January 2021

28neds01_Final_DigitalOnly.indd 62 1/20/21 11:18 AM The 14th IEEE-International Conference on Semiconductor Electronics (ICSE 2020) and Appreciation Meeting The 2020 IEEE International Confer- ence on Semiconductor Electronics (ICSE2020) was successfully held from July 28−29 2020. This was the 14th conference in the ICSE series which started in 1992 to gather semiconductor micro- and nanoelectronics researchers from academia and industry. In the light of COVID-19 Pandemic, this year’s 2020 IEEE ICSE was the first ever virtual ICSE conference or- A screenshot from EDSSC seminar (via Zoom) by Dr. Yong-Hui Fan of the ganized through WebEx Platform. Innovation Center of Advanced Devices for Future Communication, Shenzhen, China, The conference was organized by the titled “Technology Trend and Market Opportunity of 5G Industry in China” IEEE Electron Devices Society Malay- positive feedback on these seminars. in a Single Chip for Novel Integrat- sia Section Chapter. The conference To facilitate knowledge sharing, pre- ed Circuits” whilst Prof. Gananath was chaired by IEEE EDS Malaysia sentations were uploaded to YouTube, gave the lecture entitled “Influence Chapter Chair; Prof. Ir. Dr. Norhayati (https://www.youtube.com/channel/ of Structural and Operating Param- Soin. Themed “At the Edge of Nano- UCI58hLw3fM2T14VL3Naq4Hw), and eters on the Performance Character- technology”, 48 papers covering Bilibili (https://space.bilibili.com/ istics of Graphene Nanoribbon Field topics such as device modelling, sim- 581518520). More information about Effect Transistors (GNRFETs)”. 66 ulation and design; device physics the ED/SSC Online Seminar Series local and international participants and characterization; nanoelectronics can be found on our newly launched attended this 2-hour webinar which and processes; VLSI design; electron- ED/SSC Hong Kong Chapter website: was conducted via Cisco Webex ics materials and device fabrication; https://r10.ieee.org/hk-edssc/seminars/. online platform. The participants optoelectronics and photonics tech- enjoyed the lectures and a short nology; electronics materials and ~Ming Liu, Editor discussion wrapped up the session. device fabrication; MEMS/NEMS and Both presentations were also re- lastly emerging technologies & simu- ED Malaysia Kuala corded and the link can be accessed lations were presented at the confer- Lumpur Chapter via the EDS Malaysia Section Chap- ence. The authors were from various —by Maizatul Zolkapli, ter website. countries including Malaysia, India, Ahmad Sabirin Zoolfakar, Haslina Jaafar, Nurul Ezaila Alias, Norazreen Abd Aziz and Aliza Aini Md Ralib

IEEE EDS Malaysia Virtual Distinguished Lecture 2020 IEEE Electron Devices Society (EDS) Malaysia Chapter successfully organized the first virtual distinguished lecture (VDL) on July 27, 2020. Two EDS distinguished lecturers, Prof. Xing Zhou from Nanyang Technolog- ical University, Singapore and Prof. Gananath Dash from Sambalpur University, India were invited by the Chapter. Prof. Xing Zhou delivered a talk “Monolithic Co-integration of III- Prof. Xing Zhou from Nanyang Technological University, Singapore and Prof. Gananath V Materials into Foundry Si-CMOS Dash from Sambalpur University, India

January 2021 ❍ IEEE Electron Devices Society Newsletter 63

28neds01_Final_DigitalOnly.indd 63 1/20/21 11:18 AM China, Germany, United Arab Emir- ates, Nigeria, Bangladesh, Saudi Ara- bia, Iraq, Taiwan, USA, Japan, United Kingdom and Indonesia. The conference was honoured to have 3 esteemed keynote speakers joining this year’s conference. Profes- sor Dr. Zhigang Ji from Shanghai Jiao- tong University, China gave a lecture “Reliability in advanced logic devices and emerging memories—From de- terministic to Stochastic”. Professor Dr. Gananath Dash from Sambalpur Uni- versity, India had a presentation “An Iterative Simulation Method for the Current Voltage Characteristics of Gra- phene Field Effect Transistors” Profes- Members of EDS during the EDS and ICSE2020 appreciation ceremony sor Dr. Nizar Hamidon from Universiti Putra, Malaysia delivered a talk “Nano Semiconductor Electronics (ICSE) short speech during the opening of In Sensor Technology”. which was held on July 28−29, 2020. the ceremony. The conference achieved its main In conjunction with the retreat, the objective of bringing together re- IEEE EDS Committee Meeting no. 8 2020 IEEE EDS Malaysia Chapter searchers from industry and aca- and ICSE2020 meeting no. 12 were Final Year Project Award demia to gather and explore various held. This was the first time for EDS IEEE EDS Malaysia Chapter spon- issues and trends in the field of semi- to conduct such an event, to which sored six awards for 2020 Final Year conductor electronics. Results of the all the past chairs were also invited. Project (FYP) Award organized by best paper/best presenter awards are During the meeting, the Confer- several universities in Malaysia. The as follows: ence and Chapter Chair presented awards are to encourage FYP proj- the appreciation certificates to all ects related to VLSI, MEMS/NEMS 1. Best Paper Award the ICSE2020 Committee members. etc. and to acknowledge student’s Title of Paper: A comparative study Prof. Dato’ Dr. Burhanuddin Yeop work in these areas. on the performance of 1S-1R and Majlis, the advisor of EDS Malaysia The winners are as below. Congrat- Complementary resistive switch- was given the honour to make a ulations to all the award recipients! ing models Authors: Arya Lekshmi Jagath & Nandha Kumar Thulasiraman from No University Award Winner Title University of Nottingham Malay- 1 Universiti Tan Jia Pei Design, Simulation and Con- sia Campus Malaya (UM) struction of Interface circuit for biosensors 2. Best Student Presenter Award 2 Universiti Goh Hui Ying Shape optimization of Piezo- Title of Paper: Numerical Modelling Kebangsaan Ma- electric Transducer for Vibrating of MoS2/h-BN/graphene photode- laysia (UKM) Mesh Nebulizer tector for self-powering application Presenter: Umahwathy Sundararaju 3 Universiti Islam Dilruba Ruhk- Development of a 2D Stretch- Antarabangsa sana able Strain Sensor for Facial from Universiti Kebangsaan Malaysia Malaysia (UIAM) Expressions

The IEEE EDS and ICSE2020 appre- 4 Universiti Nor Farahanim Sol Gel coated optical fibre as a Teknologi Mara bt Nordin pH sensor ciation and retreat meeting was held (UITM) from 19−20 September 2020 at Con- corde Hotel Shah Alam. The ceremo- 5 Universiti Sains Haikal Iqmal Electrochemical detection of tribu- ny was held as a token of appreciation Islam Malaysia bin Hamdan tryin using graphene oxide func- (USIM) tionalized screen printed electrode to all the Conference Committee as fat content measurement members who had worked so hard in ensuring the success of the 2020 6 Universiti Putra Azman Babah Carbon Nanotube Strain Sensor Malaysia (UPM) for Human Motion Detection IEEE International Conference on

64 IEEE Electron Devices Society Newsletter ❍ January 2021

28neds01_Final_DigitalOnly.indd 64 1/20/21 11:18 AM EDS Malaysia 2nd Lecture Series 2020 and ITMA UPM visit The second lecture series was held on September 22, 2020 at Universiti Putra Malaysia (UPM). About 30 attendees, including EDS members and students enjoyed the talk given by Assoc. Prof. Dr. Nafararizal Nayan from Universiti Tun Hussein Onn. He talked about the magnetron sputter- ing technique for versatile thin film deposition. On the same day, after the talk, 12 EDS members visited the Institute of Advanced Technol- FYP EDS Award winner from Universiti Sains Islam Malaysia: Haikal Iqmal bin Hamdan ogy, Universiti Putra Malaysia. The Institute Director, Prof. Dr. Mohd. Nizar b. Hamidon welcomed us by giving an overview of the facilities and services that were available in the institute. We visited the functional devices laboratory, analysis laboratory and the characterization laboratory.

EDS UKM Student Branch Chapter by Norazreen Abd Aziz

A Keysight Webinar 2020 was co- organized on June 10, 2020 by IEEE Electron Devices Society (EDS) UKM The participants of 2nd EDS Lecture Series at Universiti Putra Malaysia Student Branch Chapter in collaboration with Keysight Technologies. The session started with an overview of Keysight Technologies offer and staff. Next, graduates and internship opportunities were presented. Then, a real World IoT & 5G signal testing, and emotional intelligence exploration issues were introduced. Par- ticipants of the sessions were also shown the virtual laboratory presentation on 5G/IoT signal testing using CXA series products. More than 30 Electrical and Electronic Engineer- ing students attended this program and benefited tremendously from the webinar.

~P Susthitha Menon, Editor

Overview by Keysight Technologies personnel

January 2021 ❍ IEEE Electron Devices Society Newsletter 65

28neds01_Final_DigitalOnly.indd 65 1/20/21 11:18 AM ED NIT Silchar Student prising the IEEE EDS members and dia. The title of the presentation was Branch Chapter non-members, including the faculty, “GaN-HEMT based front-end —by T. R. Lenka the UG/PG/PhD scholars of the ECE Transceiver for 5G Communica- Dept. of NIT Silchar, and members tion Technology.” The talk available The ED NIT Silchar Student Branch of other institutions from India and online was held in Kathmandu on Chapter organized a virtual DL Talk abroad. The workshop was coordi- May 30, 2020. It was attended by 21 “GaN-HEMT based front end Trans- nated by Dr. Koushik Guha, Dr. Kavi- people. Among them there were 14 ceiver for 5G Communication Tech- charan, and Dr. Bijit Choudhury of the IEEE members and 7 students and nology” by Prof. Ajit Kumar Panda. Dept of ECE, NIT Silchar along with faculty members. The lecture was held on June 27, Prof. F. A. Talukdar (Branch Counselor) 2020 at the Department of Electron- and Dr. T. R. Lenka (Faculty Advisor). ED MSIT Student Branch ics and Communication Engineer- Chapter Report ing, National Institute of Technology ED Uttar Pradesh Section —by Manash Chanda Silchar, Assam, India. The talk was Chapter, ED15 Kanpur attended by 31 participants, both —by Amit Verma The Chapter organized the 2020 IEEE IEEE members and non-members, VLSI Device, Circuit and System including the faculty, the UG/PG/PhD The ED Kanpur Chapter organized Conference (VLSI-DCS), which was scholars of the Department, and out- two online distinguished lectures, held on July 18–19, 2020. More than side institution members. one by Prof. Mansun Chan, (Dept. of 100 papers were presented apart On July 31, 2020, a virtual DL Talk ECE, Hong Kong University of Sci- from 20 Plenary and Keynote speak- “Challenges and Directions for Na- ence & Technology, Hong Kong) on ers and more than 100 oral/poster noelectronics to Nanotechnology” August 12, 2020 and another by Dr. presentations. by Prof. Durga Misra, New Jersey In- Simon Deleonibus (Chief Scientist of The Chapter in association with stitute of Technology (NJIT), Newark Research (Retired), CEA-LETI, France) the Department of ECE, Meghnad was organized at the Department of on August 26, 2020. Prof. Chan pre- Saha Institute of Technology (MSIT), ECE, NIST Assam, India. In this talk, sented a talk entitled “Memory Mod- Kolkata organized a Technical Talk some of the very recent develop- eling for Neuromorphic Computing” Program by Mr. Sankalp Jain, SoC ments and trends in a nano-scale highlighting the simulation infra- Implementation Engineer, Apple, device design and state-of-the-art structure required for neuromorphic Austin, USA. The event was held on fabrication of the next generation computing and the approach to de- September 15, 2020. About 105 par- electronic devices and Internet of velop memory models that can han- ticipants were present, out of which Things (IoT) devices were present- dle temporal variations of signals in 35 were IEEE members. Moreover, ed. The talk was attended by around neurons according to the in-coming Prof. Sudeb Dasgupta delivered on 90 participants comprising the IEEE signals and data. In the second dis- August 22, 2020 an illuminating talk EDS members and non-members, tinguished lecture, Dr. Deleonibus on low power integrated circuit de- including the faculty, the UG/PG/ presented the talk “New routes and sign. About 96 participants attended PhD scholars of the Department, and paradigms in Device Engineering for the session. Among them there were members of other institutions in In- Nanoelectronics and Nanosystems” 54 IEEE members and 65 non-IEEE dia and abroad. emphasizing on energy and vari- members. All the participants gained The Chapter in association with ability efficiency as being the major many benefits from the lecture. the Department of ECE, NIST Silchar, concerns and opportunities for fu- Assam, India and with the Institute In- ture nanoelectronics development. ED Netaji Subhash Engineering novation Cell, NIT Silchar conducted The lectures were attended by more College Student Branch Chapter a Five Days Online National Work- than 30 people including students —by Saheli Sarkhel shop “Recent Trends in Innovative and faculty, more than half of which CMOS-MEMS Technologies and ap- were IEEE members. The chapter and the Department of plications: Hands on Learning”, The Electronics and Communication En- Workshop was held from Sept 11–15, ED Nepal Chapter gineering, in association with IEEE 2020 under funding from Technical —by Bhadra Pokharel EDS Kolkata Chapter, organized a Education Quality Improvement Pro- two-day webinar “4G and 5G Secu- gramme, Phase III (TEQIP-III). Twelve The IEEE EDS Nepal Chapter orga- rity-Opportunities and Challenges”, invited speakers from India as well as nized a virtual Distinguished Lecture which was held from September from abroad delivered lectures in the by EDS DL Prof. Dr. Ajit Kumar Pan- 26–27, 2020. The webinar was led workshop. The workshop was attend- da, National Institute of Science and by Dr. Ashutosh Dutta, who was an ed by around 100 participants com- Technology, Berhampur, Odisha, In- IEEE fellow, a senior scientist and

66 IEEE Electron Devices Society Newsletter ❍ January 2021

28neds01_Final_DigitalOnly.indd 66 1/20/21 11:18 AM 5G Chief Strategist at Johns Hopkins University, USA. The virtual meeting was attended by 60 students and faculty members.

ED Kalyani Government Engineering College Student Branch Chapter —by Angsuman Sarkar

The IEEE ED Kalyani Government Engineering College Student Branch Chapter organized a series of technical lectures. On June 29, 2020 Dr. Soumya Pandit, Assistant Professor in the Institute Of Radiophysics & Prof. Chang-Liao, Prof. Mridula Gupta (Chairperson of EDS Delhi Chapter) Electronics, University of Calcutta and Dr. Manoj Saxena delivered a talk “Integrated Circuit Amplifier.’’ The lecture was given online using the WebEx platform. 57 possible to organize in-person talks was given on May 5, 2020 by Prof. participants attended virtually this due to the ongoing crisis. During this Mario Lanza from Soochow Univer- event. Next, a Technical Lecture by period 14 DL talks were organized and sity, China. Prof. Lanza gave an in- Dr. Bhaskar Gupta, Professor in these talks provided a wide exposure depth lecture about two-dimensional Jadavpur University, Kolkata, en- to participants about various emerg- (2D) layered materials. titled “An Introduction to RF-MEMS ing areas. All DL talks were jointly On May 6, 2020, a DL “Field Effect Technology’’ was given on June 30, organized by IEEE EDS Delhi Chapter Transistors: From MOSFET to Tunnel- 2020. The talk, given in the online and Department of Electronic Science, FET” was delivered by Prof. Dr. Joao mode using the Webex platform, University of Delhi South Campus. Antonio Martino, University of Sao was attended by 72 participants. The first in the series was the Paulo, Brasil. The speaker gave an over- The chapter organized also the EDS IEEE Distinguished Lecture “High-k view of the main progress steps of FET DL talk by Prof. Paul Berger from Dielectric and Interface Engineering evolution over the last few decades. Ohio State University, USA, who for High Performance Si/Ge MOS Prof. Marcelo Antonio Pavanello, is also with Tampere University, and FinFETs“ by Professor Kuei-Shu University Center of FEI, Brasil, deliv- Finland as a Fulbright-Nokia Distin- Chang-Liao, National Tsing Hua Uni- ered on May 8, 2020 a DL on the topic guished Chair. The Lecture entitled versity, Taiwan, held on April 30, 2020. “Junctionless Nanowire Transistors: “Fully Printable and Autonomously The talk focused on various aspects Electrical Characteristics and Com- Powered Electronic Nodes for the of High-k dielectric engineering and pact Modeling”. Prof. Pavanello dis- Internet of Everything,” was held engineering of interfaces and buffer cussed the emerging devices with on July 16, 2020 in the online mode layers in various advanced devices to particular emphasis on junction- using the WebEx platform. The vir- improve the device performance. less devices. tual meeting was interactive and Dr. Yang Chai from the Hong Kong The next two DLs were organized very useful for all the participants. Polytechnic University delivered on on May 11 and May 12, 2020. First, A total of 70 participants attended May 1, 2020 a Distinguished Lecture Prof. Maria Merlyne De Souza, The this event. on the topic “Two-dimensional Lay- University of Sheffield, UK, gave a lec- ered Materials for Nanoelectronics”. ture “From CMOS to Neuromorphic ED Delhi Chapter Activities The speaker emphasized that two- Computing-A peek into the future”. —by Mridula Gupta and dimensional layered semiconductors Prof. De Souza discussed that com- Harsupreet Kaur possess ultrathin body, atomic scale bining memory with CMOS presents smoothness, dangling bond-free sur- one possible pathway for massively The chapter organized a series of face, reasonable good mobility, and parallel and highly energy efficient online DL talks under “EDS Distin- sizable bandgap, which enables prom- neuromorphic computing systems guished Lecturer Program—Virtual ising applications in nanoelectronics. of the future. Next, Prof. Mina Rais- Lectures” program so that IEEE EDS The DL entitled “Introducing two- Zadeh, NASA Jet Propulsion Labo- members could benefit from the dimensional layered dielectrics in ratory, USA, gave a lecture “Phase expert talks in a time when it is not solid-state microelectronic devices” Change electro-optical devices for

January 2021 ❍ IEEE Electron Devices Society Newsletter 67

28neds01_Final_DigitalOnly.indd 67 1/20/21 11:18 AM space applications”. She emphasized Fay, University of Notre Dame, US. searchers and faculty members at- in particular features of germanium The main message was that to obtain tended the Summer School. On July telluride (GeTe) that undergoes sig- the low latency and high bandwidths 23, 2020, a special public webinar nificant change in refractive index, required on a mobile platform, devic- was organized on the topic “When which can be used for implementing es offering millimeter-wave perfor- to trust a self-driving car…” by Prof. optical switch, modulator, and diffrac- mance with low power consumption Marta Kwiatkowska, FRS, Associate tion gratings. while simultaneously delivering low Head of MPLS Division, Fellow of The DL by Prof. Michael S. Shur, noise figure, high linearity, and the Trinity College Department of Com- Rensselaer Polytechnic Institute, USA, ability to be integrated into complex puter Science University of Oxford. on the topic “State-of-the-Art Silicon systems in compact form factors On July 24, 2020, a special public Very Large Scale Integrated Circuits: are essential. evening webinar on the topic “A Industrial Face of Nanotechnology”, On May 31, 2020, Prof. Benjamin Reinforcement Learning Framework was delivered on May 15, 2020. Prof. Iñiguez from Universitat Rovira i for Mobile Relay Beamforming” was Shur talked about the advent of quan- Virgili, Spain, delivered a DL “Com- held by Professor Athina Petropulu, tum dots and the tremendous evolu- pact Modeling and Parameter Extrac- President-Elect, IEEE Signal Pro- tion of CMOS devices. tion for Oxide and Organic Thin Film cessing Society (2020–2021), Dis- On May 16, 2020, Prof. Arokia Nathan, Transistors (TFTs)”. Prof. Iñiguez distinguished Professor, Department Cambridge Touch Technologies, UK, cussed the recent advances in Organ- of Electrical & Computer Engineer- delivered a DL “Transparent and ic Thin Film Transistors and presented ing, Rutgers, The State University of Flexible Large Area Electronics”. Prof. various compact models. New Jersey. Nathan gave a detailed overview The last DL in the series, entitled The 7th International conference about how amorphous semiconduc- “FOSS TCAD/EDA tools for Compact/ on Microelectronics, Circuits and tors have opened a new realm of ap- SPICE Modeling” was delivered Systems (MICRO 2020) was jointly plications whereby a transparency on June 03, 2020 by Dr. Wladek organized by Applied Computer and a mechanical flexibility associat- Grabinski, MOS-AK Association. Dr. Technology, Kolkata, India and Del- ed with low-temperature processing Grabinski presented an overview of hi Technological University during on flexible substrates are impor- various open source software tools July 25−26, 2020. The conference in tant requirements. used for TCAD/SPICE simulation and the virtual mode was supported by The DL “Trends and challenges discussed the recent advances. IEEE EDS Delhi Chapter. The confer- in Nanoelectronics for the next de- All the DLs reported above were in- ence was attended by more than 100 cade” was delivered on May 20, sightful and comprehensive. They were participants. Prof. Shinichi Takagi, 2020 by Dr. Elena Gnani, University very well received. Each DL had more Department of Electrical Engineer- of Bologna, Italy. Dr. Gnani talked than 100 attendees: students, faculty ing Graduate School of Engineer- about the impact of nanoelectronic members and participants from across ing, The University of Tokyo, Japan devices and in particular, how in the world. Besides the DLs mentioned delivered the keynote address. Vari- the last decade nanoelectronic de- above, the Chapter co-organized the ous other renowned speakers such vices have been a driving force for following two events. as Prof. Jerzy Szymanski, Electrical societal applications and for a green An Online Summer School on Engineering and Informatics, Ka- sustainable world. Advances in Signal Processing and zimierz Pulaski University of Tech- On May 22, 2020, a DL “Accelerat- Machine Learning was jointly orga- nology and Humanities, Poland, Dr. ing commercialization of SiC power nized by MHRD-Institution Innova- Jacopo Iannacci, Centre for Materi- electronics” was delivered by Dr. tion Council, DDUC Chapter, Deen als and Microsystems (CMM), Fon- Victor Veliadis, North Carolina State Dayal Upadhyaya College, Univer- dazione Bruno Kessler (FBK), Trento, University, US. Dr Veliadis gave an sity of Delhi (under the aegis of DBT Italy, Dr. Mohd Faizul Bin Mohd Sa- overview of silicon carbide pow- Star College Program), Department of bri, Associate Professor, Depart- er devices. Emphasis was placed on Electronic Science, University of Delhi ment of Mechanical Engineering, high impact application opportunities and National Academy of Sciences In- University of Malaya, Malaysia also where SiC devices are expected to dis- dia (NASI)—Delhi Chapter from July delivered invited talks. Over 50 pa- place their incumbent Si counterparts. 20, 2020 to July 25, 2020. The Summer pers were presented during the on- The next DL “Advanced III-N De- School was supported by the IEEE line conference. vices for 5G and Beyond” was deliv- Electron Devices Society (EDS), Delhi ered on May 27, 2020 by Prof. Patrick Chapter. More than 400 students, re- ~Manoj Saxena, Editor

68 IEEE Electron Devices Society Newsletter ❍ January 2021

28neds01_Final_DigitalOnly.indd 68 1/20/21 11:18 AM EDS MEETINGS CALENDAR

EDS Meetings Calendar THE COMPLETE EDShttp://eds.ieee.org/ CALENDAR CAN BE FOUND AT OUR WEB SITE: HTTP://EDS.IEEE.ORG. PLEASE VISIT.

2021 15th European Microwave 12 Jan – 14 Jan 2021 Utrecht, Netherlands Integrated Circuits Conference (EuMIC)

2021 5th IEEE Electron Devices 09 Mar – 12 Mar 2021 Chengdu, China Technology & Manufacturing Conference (EDTM)

2021 IEEE International Reliability 21 Mar – 25 Mar 2021 Virtual Event Physics Symposium (IRPS)

2021 22nd International 07 April – 08 April 2021 Santa Clara, CA USA Symposium on Quality Electronic Design (ISQED)

2021 IEEE 34th International 12 April – 15 April 2021 Cleveland, OH USA Conference on Microelectronic Test Structures (ICMTS)

2021 IEEE Latin America Electron 18 April – 20 April 2021 Virtual Event Devices Conference (LAEDC)

2021 32nd Annual SEMI Advanced 02 May – 05 May 2021 DC, WA USA Semiconductor Manufacturing Conference (ASMC)

2021 International Siberian 12 May – 14 May 2021 Kazan, Russia Conference on Control and Communications (SIBCON)

2021 IEEE International Memory 15 May – 18 May 2021 Dresden, Germany Workshop (IMW)

2021 33rd International Symposium 29 May – 02 June 2021 Nagoya, Japan on Power Semiconductor Devices and ICs (ISPSD)

2021 Silicon Nanoelectronics 12 June – 13 June 2021 Kyoto, Japan Workshop (SNW)

January 2021 ❍ IEEE Electron Devices Society Newsletter 69

28neds01_Final_DigitalOnly.indd 69 1/20/21 11:18 AM EDS Meetings Calendar http://eds.ieee.org/

2021 Symposium on VLSI 13 June – 16 June 2021 Kyoto, Japan Technology

2021 IEEE 48th Photovoltaic 19 June – 24 June 2021 Fort Lauderdale, FL USA Specialists Conference (PVSC)

2021 International EOS/ESD 23 June – 25 June 2021 Chengdu, SICHUAN, China Symposium on Design and System (IEDS)

2021 IEEE International 05 July – 08 July 2021 Kyoto, Japan Interconnect Technology Conference (IITC)

2021 9th International Symposium 10 July - 12 July 2021 Changsha, China on Next Generation Electronics (ISNE)

2021 IEEE International Flexible 07 Aug – 10 Aug 2021 Columbus, OH USA Electronics Technology Conference (IFETC)

2021 35th Symposium on 22 Aug – 26 Aug 2021 Campinas, Brazil Microelectronics Technology and Devices (SBMicro)

2021 16th European Microwave 10 Oct – 11 Oct 2021 London, United Kingdom Integrated Circuits Conference (EuMIC)

2021 IEEE/ACM International 31 Oct – 03 Nov 2021 Munich, Germany Conference On Computer Aided Design (ICCAD)

2021 IEEE 8th Workshop on Wide 06 Nov – 08 Nov 2021 Redondo Beach, CA USA Bandgap Power Devices and Applications (WiPDA)

2021 IEEE BiCMOS and 04 Dec – 10 Dec 2021 Monterey, CA USA Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)

70 IEEE Electron Devices Society Newsletter ❍ January 2021

28neds01_Final_DigitalOnly.indd 70 1/20/21 11:18 AM Call for Papers for a Special Issue of IEEE Transactions on Electron Devices on “New simulation methodologies for next-generation TCAD tools”

Technology Computer Aided Design is used to simulate semiconductor processes and devices, a fi eld which has become increasingly complex and heterogeneous. Processing of integrated circuits requires nowadays over 400 process steps, and the resultant devices often have a complicated 3D structure and contain various materials. The full device behavior can only be understood by considering effects on all length scales from atomistic (interfaces, defects etc.) over nanometric (quantum confi nement, non-bulk properties etc.) to full chip dimensions (strain, heat transport etc.), and time scales from femtoseconds to seconds. Voltages, currents and charges have been scaled to such low levels that electronic noise, statistical effects and process variations have a strong impact. Devices based on new materials (e.g. 2D crystals) and physical principles (ferroelectrics, magnetic materials, qubits etc.) challenge standard TCAD approaches. While the simulation methods developed by the physics community can describe the basic device behavior, they often lack important simulation capabilities like, for example, transient simulations or integration with other TCAD tools and are too slow for daily use. Due to the complexity of semiconductor technology, it becomes more and more diffi cult to assess the impact of a change in processing or device structure on circuit performance by looking at a single aspect of an isolated device under idealized conditions. Instead a TCAD tool chain is required that can handle realistic device structures embedded in a chip environment. New methodologies are required for all aspects of TCAD to ensure an effi cient tool chain covering from atomistic effects to circuit behavior based on fl exible simulation models that can handle new materials, device principles and the ensuing large-scale simulations.

This Special Issue of the IEEE Transactions on Electron Devices will feature the most recent developments and the state of the art in the ﬁ eld of TCAD for processing and for device behavior with a focus on new methodologies that improve the tool chain. Papers must be new and present original material that has not been copyrighted, published or accepted for publications in any other archival publications, that is not currently being considered for publications elsewhere, and that will not be submitted elsewhere while under considerations by the Transactions on Electron Devices.

Topics of interest include, but are not limited to:

• Artifi cial Intelligence applied to TCAD • TCAD device models for o new materials (2D materials, oxides, organic semiconductors, oxide semiconductors, nanowire devices etc.) o new device types (magnetic devices, memristors, spintronics, qubits, sensors etc.) o physical effects (ferroelectric dielectrics, thermal transport at nanoscale, atomistic simulation etc.) o simulation conditions that push the limits of standard TCAD: ballistic transport, THz frequencies, cryogenic conditions, device degradation, electromagnetic and plasma waves in active devices, transient simulations, noise and fl uctuations, microscopic simulation of large power devices • Process simulation o Atomistic process simulation to generate structures for atomistic device simulations (including both interconnects and transistors) o Gate stack modeling including dipole diffusion o Stress simulation for nanosheet and forksheet devices and stress simulations including layout effects o Topological simulation o Equipment simulation • New methods for the TCAD tool chain o Self-consistent integration of simulation models into the hierarchy o Device-circuit interaction o Multi-physics and multi-scale integration o Effi cient use of the data produced along the chain o Workfl ow improvements o Methods that improve the turn-around-time for TCAD simulations

Submission instructions: Manuscripts should be submitted in a double column format using an IEEE style ﬁ le. Please visit the following link to download the templates: http://www.ieee.org/publications_standards/publications/authors/author_templates.html In your cover letter, please indicate that your submission is for this special issue.

Submission deadline: February 28, 2021 Publication date: November 2021

Guest Editors: 1. Prof. Fabrizio Bonani, Politecnico di Torino, Italy 2. Dr. Stephen Cea, Intel Corp., USA 3. Prof. Elena Gnani, University of Bologna, Italy 4. Prof. Sung-Min Hong, GIST, Republic of Korea 5. Dr. Seonghoon Jin, Samsung, USA 6. Prof. Christoph Jungemann, RWTH Aachen, Germany 7. Prof. Xiaoyan Liu, Peking University, China 8. Dr. Victor Moroz, Synopsys, USA 9. Dr. Anne Verhulst, imec, Belgium

January 2021 ❍ IEEE Electron Devices Society Newsletter 71

28neds01_Final_DigitalOnly.indd 71 1/20/21 11:18 AM CHANGE IN EDS NEWSLETTER DISTRIBUTION

Attention All EDS Members,

Included in your annual EDS membership benefits are quarterly print copies of the newsletter, as well as electronic versions sent to your preferred email address. In May 2019, the EDS Board of Governors approved to add the op- tion to request a print version of the newsletter for those that have a preference, and making the electronic version the default. There is no extra cost to receive the print copy. When you renew your EDS membership for 2021, if you wish to continue receiving the print copy of the EDS Newsletter, you must indicate this in your IEEE account. Thank you.

72 IEEE Electron Devices Society Newsletter ❍ January 2021