JANUARY 2021 VOL. 28, NO. 1 ISSN: 1074 1879 EDITOR-IN-CHIEF: DANIEL TOMASZEWSKI TABLE OF CONTENTS T ECHNICAL B RIEFS TECHNICAL BRIEFS . 1 • System and High-Volume-Manufacturing Driven More Moore Scaling Roadmap • Highlights of IEDM 2020 SYSTEM AND HIGH-VOLUME- • Highlights of the 2020 IEEE Photovoltaic Specialists Conference MANUFACTURING DRIVEN MORE • Review of the 2020 IRPS UPCOMING TECHNICAL MEETINGS . 31 MOORE SCALING ROADMAP • 5th IEEE Electron Devices Technology and MUSTAFA BADAROGLU1 AND PAOLO A. GARGINI2 Manufacturing (EDTM) Conference 1 • 2021 IEEE Photovoltaics Specialist Conference (PVSC) IEEE IRDS MORE MOORE CHAIRMAN, QUALCOMM, • 2021 IEEE International Memory Workshop (IMW) 2IEEE LIFE FELLOW, I-JSAP FELLOW, CHAIRMAN IRDS • 2021 IEEE Latin American Electron Devices Conference (LAEDC) [email protected], [email protected] SOCIETY NEWS . 35 • Board of Governors Meeting • Message from EDS President • Message from the Chair of the EDS Optoelectronic Devices Committee 1. Introduction • Message from Editor-in-Chief Scaling device features by approximately 30% in each new tech- • Congratulations to Dr. Robert W. Dutton-2020 nology generation supported Moore’s Law doubling the number of IEEE EDS Celebrated Member • EDS Members Named Recipients of 2021 IEEE transistors every 2-years for decades while also improving system Technical Field Awards performance by concurrently increasing transistor drive current • In Memory of James D. Meindl • Announcement of the 2020 EDS Undergraduate and reducing operating voltage. This combination allowed intro- Student Scholarship Winners duction of new functions in innovative System-On-Chip (SoC) • Announcement of the 2020 EDS Masters Student products with better performance and lower cost. The progress Fellowship Winners • Announcement of the 2020 EDS PhD Student of technology scaling has been measured by monitoring PPAC Fellowship Winners (Performance-Power-Area-Cost) improvements, typically hap- • 2020 EDS Chapter of the Year Award Winners • Call for Nominations—EDS Student Fellowships pening with any new technology introduction with a cadence of for 2021 2–3 years. However, pure geometric scaling does not provide any YOUNG PROFESSIONALS . 46 longer the necessary PPAC improvements at the system level due • India’s Rise in Nanoelectronics Research to several reasons: • IEEE Young Professionals Germany at Robert Bosch Semiconductor Headquarters 1) limits of practical power dissipation were reached around the middle of the previous decade and this constraint im- CHAPTER NEWS . 51 • DIPED-2020 Seminar/Workshop Dedicated to the posed a maximum useable frequency of 5–6 GHz, Memory of Prof. Nikolai Voitovich 2) ideal geometric scaling introduces increasing levels of para- • TEC Costa Rica Recipient of the 2020 IEEE EDS Student Branch Chapter of the Year Award sitics that adversely reduce performance, • EDS Cares: Face Mask Loop Extender and Face Shield 3) cost of scaling is increasing faster than in the past due to for SMK 18 Shah Alam Muslimah Student and lithographic limitations demanding multiple exposure per Teacher Volunteers layer and therefore making final products very costly, REGIONAL NEWS . 55 EDS MEETINGS CALENDAR . 69 (continued on page 3) CALL FOR PAPERS—SPECIAL ISSUE OF THE IEEE TRANSACTIONS ON ELECTRON DEVICES . 71 NEWSLETTER DISTRIBUTION CHANGES . 72 YOUR COMMENTS SOLICITED Your comments are most welcome. Please write directly to the Editor-in-Chief of the Newsletter at [email protected] 28neds01_Final_DigitalOnly.indd 1 1/20/21 11:13 AM ELECTRON DEVICES NEWSLETTER SOCIETY EDITORIAL STAFF Editor-In-Chief President Vice President of Membership Daniel Tomaszewski Ravi Todi and Services Lukasiewicz Research Network—Institute of Western Digital Technologies Patrick Fay Microelectronics and Photonics Email: [email protected] University of Notre Dame Email: [email protected] E-mail: [email protected] Treasurer Bin Zhao Vice President of Publications REGIONS 1–6, 7 & 9 United Kingdom, Middle Freescale Semiconductor and Products Eastern, Northeastern & East & Africa E-mail: [email protected] Joachim Burghartz Southeastern USA Stewart Smith Institute for Microelectronics (Regions 1, 2 & 3) Scottish Microelectronics Centre Secretary Stuttgart Rinus Lee E-mail: [email protected] M.K. Radhakrishnan E-mail: [email protected] NanoRel GlobalFoundries E-mail: [email protected] Vice President of Regions/ E-mail: [email protected] Western Europe Chapters Mike Schwarz Jr. Past President Murty Polavarapu Central USA & Canada Technische Hochschule Fernando Guarin Space Electronics Solutions (Regions 4 & 7) Mittelhessen University of GlobalFoundries E-mail: [email protected] Michael Adachi Applied Sciences E-mail: [email protected] Simon Fraser University E-mail: mike.schwarz1980@ Vice President of Strategic E-mail: [email protected] googlemail.com Sr. Past President Directions Samar Saha Paul Berger Prospicient Devices The Ohio State University Southwestern & Western USA REGION 10 E-mail: [email protected] E-mail: [email protected] (Regions 5 & 6) Australia, New Zealand & Muhammad Mustafa Hussain South East Asia Vice President of Education Vice President of Technical University of California—Berkeley Sharma Rao Balakrishnan Navakanta Bhat Committees E-mail: MuhammadMustafa. Universiti Sains Islam Malaysia Indian Institute of Science John Dallessase [email protected] E-mail: [email protected] Email: [email protected] University of Illinois at Urbana- Champaign Vice President of Meetings Email: [email protected] Latin America (Region 9) North East and East Asia Kazunari Ishimaru Edmundo A. Guiterrez-D. Ming Liu Kioxia Corporation INAOE Institute of Microelectronics Email: [email protected] E-mail: [email protected] E-mail: [email protected] REGION 8 South Asia Eastern Europe Soumya Pandit Kateryna Arkhypova University of Calcutta IRE NASU E-mail: [email protected] E-mail: [email protected] IEEE prohibits discrimination, harassment, and bullying. For more information, visit http://www.ieee.org/web/aboutus/whatis/policies/p9-26.html. Scandinavia & Central Europe Marcin Janicki Lodz University of Technology E-mail: [email protected] EDS Board of Governors (BoG) CONTRIBUTIONS WELCOME Elected Members-at-Large Elected for a three-year term (maximum two terms) with ‘full’ voting privileges Readers are encouraged to submit news items concerning the Society and its members. Please send your ideas/articles directly to either Editor-in- 2021 TERM 2022 TERM 2023 TERM Chief or the Regional Editor for your region. The email addresses of all Paul Berger (1) Constantin Bulucea (1) Roger Booth (2) Regional Editors are listed on this page. Email is the preferred form of Navakanta Bhat (2) Daniel Camacho (1) Xiojun Guo (1) submission. Merlyne De Souza (1) John Dallesasse (1) Edmundo A. Gutierrez-D. (2) NEWSLETTER DEADLINES Kazumari Ishimaru (1) Mario Lanza (1) Francesca Iacopi (1) William (Bill) Nehrer (1) Geok Ing Ng (1) Benjamin Iniguez (2) ISSUE DUE DATE Murty Polavarapu (2) Claudio Paoloni (1) P. Susthitha Menon (1) Camilo Velez Cuervo (1) Hitoshi Wakabayashi (1) Manoj Saxena (2) Sumant Sood (2) October July 1st January October 1st April January 1st July April 1st The EDS Newsletter archive can be found on the Society web site at http://eds.ieee.org/eds-newsletters.html. The archive contains issues from July 1994 to the present. IEEE Electron Devices Society Newsletter (ISSN 1074 1879) is published quarterly by the Electron Devices Society of the Institute of Electrical and Electronics Engineers, Inc. Headquarters: 3 Park Avenue, 17th Floor, New York, NY 10016–5997. Printed in the U.S.A. One dollar ($1.00) per member per year is included in the Society fee for each member of the Electron Devices Society. Periodicals postage paid at New York, NY and at additional mailing offices. Postmaster: Send address changes to IEEE Electron Devices Society Newsletter, IEEE, 445 Hoes Lane, Piscataway, NJ 08854. Copyright © 2021 by IEEE: Information contained in this Newsletter may be copied without permission provided that copies are not used or distributed for direct commercial advantage, and the title of the publication and its date appear on each photocopy. 2 IEEE Electron Devices Society Newsletter ❍ January 2021 28neds01_Final_DigitalOnly.indd 2 1/20/21 11:13 AM SYSTEM AND HIGH-VOLUME-MANUFACTURING DRIVEN MORE MOORE SCALING ROADMAP (continued from page 1) 4) there is an increasing imbal- ter is to provide physical, electrical, 10 years, for multiple cloud applica- ance and disconnect between and reliability requirements for a tions. The first step in the roadmap the performance of devices at unified logic and memory technol- process is to identify the ground rules the die level and the perfor- ogy platform to sustain power, per- and their inherent limits set by the mance requirements of the formance, area, cost (PPAC) “scaling unit process modules, devices, and overall system (e.g. memo- guidelines” for mobile and cloud ap- the impact of any parasitics on perfor- ry bandwidth bottleneck) that plications over a time horizon of 15 mance. The second step is to describe creates a significant burden years for Mainstream/High-Volume the standard cell scaling parameters to further enhance system in- Manufacturing (HVM) [1]. Such tech- and how to further tighten key design tegration and performance. nology platform identifies the main rules by means of Design Technology Therefore, for all the above technology drivers and provides the Co-Optimization