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The UNIVAC System 1 Chapter 8 The UNIVAC system 1 /. Presper Eckert, Jr. / James R. Weiner H. Frazer Welsh / Herbert F. Mitchell of Organization the UNIVAC system which all data must pass during transfer between any arithmetic In March the first 2 register and the main or between the 1951, UNIVAC system formally passed its memory memory and the tests and was The arithmetic acceptance put promptly into operation by the input-output registers. registers are shown along Bureau of the Census. the bottom of each connected to the Since the UNIVAC is the first computer diagram high speed bus which can handle both alphabetic and numerical data to reach system. full-scale The L-, F-, X-, and are each operation so far, its operating record and a review of A-registers of one word or 12- the of to character and are concerned with types problems which it has been applied provide an capacity directly the arithmetic milestone in the field of operations. The V- and are of 2- and 10-word interesting ever-widening electronic digi- Y-registers capacity, tal computers. respectively. They are used solely for multiple word transfers The of the within the main Associated organization UNIVAC is such that those functions memory. with the arithmetic registers which do not are the adder directly require the main computer are performed algebraic (AA), the comparator (CF), and the multi- units each counter by separate auxiliary having its own power supply. Thus plier-quotient (MQC). the keyboard to magnetic card to tape, punched magnetic tape Addition-subtraction instructions and to are tape typewritten copy operations delegated to auxiliary The addition-subtraction components. operations are performed in conjunction with the comparator since all numerical are absolute The main computer assembly includes all of those units which quantities with an are concerned with the main magnitudes algebraic sign attached. Before either an directly or central computer opera- addition or subtraction is tions. A block of this performed, the two quantities, one diagram arrangement is shown in Fig. 1. All in the of the elements shown already A-register and the other either from the are contained within the central computer memory or from the casework X-register, depending the instruction, except the supervisory control desk (SC) and the Uni- upon particular 2 are for to which the compared magnitude and sign. The adder can then servos, lines in the upper right section of the diagram inputs be switched connect. so as always to produce a noncomplemented result for The choice of The in any operation. adder input arrangement is there- supervisory control, addition to all the necessary control fore under the control switches and indicator of the comparator. The also lights, contains an input keyboard. Also comparator determines the for the result cabled to the control is proper sign to the usual supervisory a typewriter which is operable according the algebraic rules. by main computer. By means of these two units, limited One additional function the amounts of information can be inserted or removed either at the performed by comparator for addi- tion and subtraction is to control the will of the operator or by the programmed instructions. complementer. This deter- mination is based which - The circuits upon ( + , or is input-output operate on all data entering or leav- operation ) indicated, whether the The and and, the signs are like or unlike. For a subtract ing computer. input output synchronizers properly instruction, time the sign of the subtrahend is reversed before the incoming or outgoing data for either the Uniservos entering the com- (tape The or the parator. comparator then compares the of the devices) supervisory control devices. The input and output signs quantities in order to determine and are each 60 whether the two quantities are subtracted registers (/ O) word (720 characters) temporary or added. storage registers which are intermediate between the main com- puter and the input-output devices. Multiplication instruction The bus high-speed amplifier is a switching central through The multiplication process requires the services of the adder, the tAIEE-lRE 1951. Conf., 6-16, December, comparator, the multiplier-quotient counter and the four arith- 2 Registered trade mark. metic the first of registers. During step multiplication the X-reg- 157 158 Part 2 The instruction-set processor: main-line computers Section 1 Processors with one address per instruction STANDARD PULSES TO ALL UNITS . A , I t I I I I I ' CONTROL BUSSES TO ANO TIMING PULSE FROM SUPERVISORY UNISERVOS GENERATOR CONTROL READ WRITE a BUS BUS CYCLING UNIT (SC) INPUT- (CU) [ T OUTPUT FROM TO CONTROL CONTROL SIGNALS CIRCUITS TO GATES ALL UNITS T CONTROL SIGNALS Hillllli -J--*- --.Ml MAIN MEMORY MEMORY Tl I (MM) SWITCH INPUT OUTPUT I I I (1000 WORDS] SYNCHRONIZER SYNCHRONIZER FUNCTION TABLE (FT) (6 WORDS) I I I CY PC INSTRUCTION MEM. LOCATION DIGITS DIGITS HIGH- HSB II ODD- SPEED EVEN BUS I I I I CHECKER CONTROL AMPLIFIER STATIC REGISTER _»SIGS TO (OEC) INPUT- (HSBA) HSB 26 (SR) OUTPUT CONTROL — DISTRIBUTOR LINE I CIRCUITS I I A i CONTROL SIGS TO I REGS ANO CONTROL CIRC. OVERFLOW I TIME OUT SIGNAL (TO) TO AAS CC t I CHECK I I I I CIRCUITS I ITTTT ALGEBRAIC (MOO COMPARATOR ADDER (CP) INPUT FROM REGS. (AA) AND OTHER UNITS LEGEND: INFORMATION SIGNALS ISIGNAL SIGNAL <1 i*5 •CONTROL SIGNALS 8 PULSES L F X A CC L CR Y V t WORD) (1 WORD) (t WORD) (1 WORD) (1 WORD) (I WORD) (10 WORDS) (2 WORDS) " "SB2A _HSB_£A_ HSB1A am E_XIBACL£QMR-0| i Fig. 1. Block diagram of UNIVAC. Chapter 8 The UNIVAC system 159 ister receives the multiplier from the memory and the comparator position to the left. The multiplier-quotient counter counts each the first determines the sign of the final product by comparing signs transfer, thereby building up the quotient digit. As soon as of the multiplier and multiplicand. During the next three steps the quantity in the A-register, (neglecting its original sign) goes the in the multiplicand, which has been stored in the L-register by some negative, digit the multiplier-quotient counter, not counting the transfer which causes the remainder to is trans- previous instruction, is transferred three times to the A-register go negative, ferred to the and the remainder in the is through the algebraic adder. The result, three times the multi- X-register A-register shifted one to the left. The divisor is then added to the plicand, is then stored in the F-register. During the next 11 steps place until the becomes This time the of multiplication, the successive multiplier digits, beginning with A-register quantity positive. the least significant, are transferred from the X-register to the multiplier-quotient counter must give the complement of the of transfers multiplier-quotient counter. The multiplier-quotient counter then number for the real quotient digit. Special comple- determines whether each particular multiplier digit is less than menting read-out gates provide this method of interpreting the three, or greater than or equal to three. multiplier-quotient counter. releases to the If the former, the L-register the multiplicand The X-register therefore collects the quotient, digit by digit, A-register via the adder, and the multiplier-quotient counter is from the multiplier-quotient counter until the full 11 digits have stepped downward one unit. If the multiplier digit is equal to or been obtained. The quotient is then transferred to the A-register greater than three, the multiplier-quotient counter sends a signal and the sign from the comparator (CP) is affixed during the final to the F-register which releases three times the multiplicand to stage of the divide instruction. the A-register and the multiplier-quotient counter is stepped three The other internal operations of the UNIVAC include many times. Thus a multiplier digit of seven would be processed as two transfer instructions by which words may be moved among the and the extraction transfers from the F-register to the A-register and one transfer from registers memory with and without clearing, instruction certain of the L-register to the A-register, or a total of three transfers. by which digits a word may be extracted into another to the of the When the multiplier-quotient counter reaches zero, the next word according parity corresponding of an extractor shift control multiplier digit is brought in from the X-register, while the A-reg- digits word; instructions; and special instructions such as transfer of in ister, containing the first partial product, is shifted one position breakpoint, control, (explained to the right. subsequent paragraphs) and stop. During the final step of multiplication, the sign is attached to Basic operating cycle the product which has been built up in the A-register. One of the several available instructions causes the least multiplication sig- The basic operating cycle of the UNIVAC is founded upon single nificant as are shifted the limits of the digits, they beyond A-reg- address instructions which specify the memory location of one to the where the ister, to be transferred X-register they replace word. In the case of the arithmetic instructions which require two as are moved to the multiplier digits they multiplier-quotient operands, one of the operands must be moved into the proper counter. Thus 22 can be obtained as well as 11 place products register by some previous instruction. In order to control the place. sequence of instructions, a special counter, called the control counter (CC), retains the memory location from which the succeed- Division instruction ing instruction word is to be obtained. Each time a new instruction The division operation is performed by a nonrestoring method.
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