Matrix Multiplication Beyond Auto-Tuning: Rewrite-Based GPU Code Generation

Total Page:16

File Type:pdf, Size:1020Kb

Matrix Multiplication Beyond Auto-Tuning: Rewrite-Based GPU Code Generation Matrix Multiplication Beyond Auto-Tuning: Rewrite-based GPU Code Generation Michel Steuwer Toomas Remmelg Christophe Dubach University of Edinburgh {michel.steuwer, toomas.remmelg, christophe.dubach}@ed.ac.uk ABSTRACT APIs such as OpenCL or RenderScript are now supported on Graphics Processing Units (GPUs) are used as general pur- most mobile GPUs and new types of mobile applications are pose parallel accelerators in a wide range of applications. emerging, such as real-time 3D scene reconstruction [17]. They are found in most computing systems, and mobile de- However, producing high-performance GPU code is no- vices are no exception. The recent availability of program- toriously hard. Low-level hardware features are directly ex- ming APIs such as OpenCL for mobile GPUs promises to posed to programmers, requiring expert knowledge to achieve open up new types of applications on these devices. high performance. In addition, each type of devices comes However, producing high performance GPU code is ex- with its own performance characteristics, requiring differ- tremely difficult. Subtle differences in device characteristics ent optimizations. This problem is further exacerbated with can lead to large performance variations when different opti- mobile GPUs since optimizations benefitial for desktop GPUs mizations are applied. As we will see, this is especially true (e.g., AMD, Nvidia GPUs) can negatively impact performance for a mobile GPU such as the ARM Mali GPU which has a on mobile GPUs, as we will see later in this paper. very different architecture than desktop-class GPUs. Code Auto-tuners have been proposed to address performance optimized and tuned for one type of GPUs is unlikely to portability issues on GPUs. They are generally based on a achieve the performance potential on another type of GPUs. specialized parametric implementation of a computational Auto-tuners have traditionally been an answer to this per- kernel, such as matrix multiplication, and the tuning process formance portability challenge. For instance, they have been explores the performance space on the targeted hardware. successful on CPUs for matrix operations, which are used However, auto-tuners have two major drawbacks. First, writ- as building blocks in many high-performance applications. ing the parametric implementation for a given kernel requires However, they are much harder to design for different classes non-negligible effort from the programmer. Secondly, and of GPUs, given the wide variety of hardware characteristics. more importantly, the implementation is limited by a finite In this paper, we take a different perspective and show how set of parameters which might not be good at expressing com- performance portability for matrix multiplication is achieved plex composition of optimizations. As we will see, this can using a compiler approach. This approach is based on a result in far from optimal performance when the parametric recently developed generic technique that combines a high- implementation is run on a device it was not originally de- level programming model with a system of rewrite rules. Pro- signed for. In other words, auto-tuning alone is not sufficient grams are automatically rewritten in successive steps, where to solve the performance portability challenge. optimizations decision are made.This approach is truly per- We argue that achieving true performance portability re- formance portable, resulting in high-performance code for quires a more generic mechanism that expresses combina- very different types of architectures such as desktop and mo- tions of optimizations beyond a fixed parametric space. We bile GPUs. In particular, we achieve a speedup of 1.7x over a advocate the use of a recently developed new high perfor- state-of-the-art auto-tuner on the ARM Mali GPU. mance code generation technique based on rewrite rules [23]. Programs are expressed in a high-level functional program- ming model which shields the programmer from hardware 1. INTRODUCTION peculiarities.The compiler is then free to automatically ex- Graphics Processing Units (GPUs) have emerged as power- plore the optimization space using a system of rewrite rules. ful general-purpose parallel accelerators. They have revolu- These rules encode algorithmic transformations as well as tionized the high-performance computing landscape and are hardware-specific low-level optimizations. Recent work [22] about to bring big changes to mobile devices. Programming has shown that this generic compiler approach leads to high performance for desktop-class GPUs from AMD and Nvidia. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed In this paper, we demonstrate that this compiler-based for profit or commercial advantage and that copies bear this notice and the full citation technique is able to succeed where auto-tuners fail to deliver, on the first page. Copyrights for components of this work owned by others than the using matrix multiplication as a use-case. Matrix multiplica- author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or tion is a well studied and useful primitive found at the heart republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]. of many numerical codes and algorithms in areas such as CASES ’16, October 01-07 2016, Pittsburgh, PA, USA machine-learning. In addition, there exist high-performance c 2016 Copyright held by the owner/author(s). Publication rights licensed to ACM. reference implementations and specialized auto-tuners, which ISBN 978-1-4503-4482-1/16/10. $15.00 allow for meaningful comparison. DOI: http://dx.doi.org/10.1145/2968455.2968521 Using the ARM Mali GPU as an example, we show that Desktop GPU Desktop GPU Mobile GPU (Nvidia) (AMD) (ARM) an auto-tuner designed primarily for desktop-class GPUs is 2500 3000 17.5 unable to achieve the full performance potential, resulting 15.0 2000 2500 12.5 in a 40% performance loss. In contrast, our compiler-based 2000 1500 10.0 approach delivers performance on par with the best hand- 1500 1000 7.5 tuned version on each of the three platforms tested. This is GFLOPS 1000 5.0 500 possible due to the generic nature of the rewrite-based code 500 2.5 0 0 0.0 generation technique, which allows us to encode generic op- CLBlast CLBlast CLBlast Hand MAGMA clBLAS timizations that are combined during the exploration process. +CLTune +CLTune +CLTune optimized This includes vectorization and the use of built-in functions, which are highly beneficial for the Mali GPU. Figure 1: Performance comparison between auto-tuned (left To summarize, this paper makes the following contributions: bar) and hand-optimized (right bar) code. Higher is better. We demonstrate the limitations of auto-tuning when • applied on a different class of GPUs; tually not difficult to realise what needs to be done to reach We present how generic optimizations beneficial for the a higher-level of performance for some specific machine, it is • Mali GPU are expressed in a rewrite-based generator; extremely hard to write a parametric kernel which exposes Our experimental results show that a rewrite-based ap- these choices as a finite set of parameters. Especially given • proach is performance portable and even outperforms that a library enabled for auto-tuning, such as CLBlast, is al- hand-tuned code on Mali. ready quite complex with more than 1500 lines of parametric The rest of the paper is organized as follows. The next OpenCL code just for matrix multiplication. section shows that performance is far from portable between What is needed is an approach that easily combines opti- different classes of GPUs. Section 3 presents characteristics of mizations and produce a search space that includes the best the Mali GPU. Section 4 introduces the high-level functional performing implementations for different types of hardware. language and the rewrite-based code generator we adopted. In this paper we propose to use a generic rewrite-based ap- Section 5 discusses optimizations for matrix multiplication, proach [23], which is not specific to matrix multiplication, how they are represented functionally and how they are en- and we show that it succeeds where the auto-tuner fails. This coded as rewrite rules. Sections 6 and 7 present our exper- approach is also simpler to use since the compiler input is a imental setup and show results on how we automatically high-level functional program. For instance, matrix multipli- achieve high performance from a portable, high-level rep- cation is expressed in just five lines of code. resentation of matrix multiplication. Finally, sections 8–10 discuss our work, related work and conclude the paper. 3. MALI GPU CHARACTERISTICS 2. MOTIVATION ARM Mali-T628 GPU. Matrix multiplication is probably one of the most studied The Mali-T628 GPU is a mobile GPU implementing ARMs kernels in the high-performance community. Automatic tun- second generation Midgard micro-architecture. Each core has ing techniques have been applied quite successfully to this two arithmetic pipelines, each of which processes 128-bits of benchmark for over 20 years starting with PHiPAC [4] and data at a time using SIMD operations. A single core can ATLAS [25]. However, auto-tuners rely on a parametric im- simultaneously manage up to 256 threads in hardware, de- plementation (or a parametric code generator) that is highly pending on the amount of registers required by each thread. specialized to the target machine. This approach is well- This large number of threads is used to hide memory laten- suited in cases where little variation exists between different cies, as stalled threads waiting for memory can be overtaken processing units but falls short when the target processing by other threads. units exhibit significant variations.
Recommended publications
  • GPU Developments 2018
    GPU Developments 2018 2018 GPU Developments 2018 © Copyright Jon Peddie Research 2019. All rights reserved. Reproduction in whole or in part is prohibited without written permission from Jon Peddie Research. This report is the property of Jon Peddie Research (JPR) and made available to a restricted number of clients only upon these terms and conditions. Agreement not to copy or disclose. This report and all future reports or other materials provided by JPR pursuant to this subscription (collectively, “Reports”) are protected by: (i) federal copyright, pursuant to the Copyright Act of 1976; and (ii) the nondisclosure provisions set forth immediately following. License, exclusive use, and agreement not to disclose. Reports are the trade secret property exclusively of JPR and are made available to a restricted number of clients, for their exclusive use and only upon the following terms and conditions. JPR grants site-wide license to read and utilize the information in the Reports, exclusively to the initial subscriber to the Reports, its subsidiaries, divisions, and employees (collectively, “Subscriber”). The Reports shall, at all times, be treated by Subscriber as proprietary and confidential documents, for internal use only. Subscriber agrees that it will not reproduce for or share any of the material in the Reports (“Material”) with any entity or individual other than Subscriber (“Shared Third Party”) (collectively, “Share” or “Sharing”), without the advance written permission of JPR. Subscriber shall be liable for any breach of this agreement and shall be subject to cancellation of its subscription to Reports. Without limiting this liability, Subscriber shall be liable for any damages suffered by JPR as a result of any Sharing of any Material, without advance written permission of JPR.
    [Show full text]
  • Mali-400 MP: a Scalable GPU for Mobile Devices
    Mali-400 MP: A Scalable GPU for Mobile Devices Tom Olson Director, Graphics Research, ARM Outline . ARM and Mobile Graphics . Design Constraints for Mobile GPUs . Mali Architecture Overview . Multicore Scaling in Mali-400 MP . Results 2 About ARM . World’s leading supplier of semiconductor IP . Processor Architectures and Implementations . Related IP: buses, caches, debug & trace, physical IP . Software tools and infrastructure . Business Model . License fees . Per-chip royalties . Graphics at ARM . Acquired Falanx in 2006 . ARM Mali is now the world’s most widely licensed GPU family 3 Challenges for Mobile GPUs . Size . Power . Memory Bandwidth 4 More Challenges . Graphics is going into “anything that has a screen” . Mobile . Navigation . Set Top Box/DTV . Automotive . Video telephony . Cameras . Printers . Huge range of form factors, screen sizes, power budgets, and performance requirements . In some applications, a huge difference between peak and average performance requirements 5 Solution: Scalability . Address a wide variety of performance points and applications with a single IP and a single software stack. Need static scalability to adapt to different peak requirements in different platforms / markets . Need dynamic scalability to reduce power when peak performance isn’t needed 6 Options for Scalability . Fine-grained: Multiple pipes, wide SIMD, etc . Proven approach, efficient and effective . But, adding pipes / lanes is invasive . Hard for IP licensees to do on their own . And, hard to partition to provide dynamic scalability . Coarse-grained: Multicore . Easy for licensees to select desired performance . Putting cores on separate power islands allows dynamic scaling 7 Mali 400-MP Top Level Architecture Asynch Mali-400 MP Top-Level APB Geometry Pixel Processor Pixel Processor Pixel Processor Pixel Processor Processor #1 #2 #3 #4 CLKs MaliMMUs RESETs IRQs IDLEs MaliL2 AXI .
    [Show full text]
  • Intel Desktop Board DG41MJ Product Guide
    Intel® Desktop Board DG41MJ Product Guide Order Number: E59138-001 Revision History Revision Revision History Date -001 First release of the Intel® Desktop Board DG41MJ Product Guide February 2009 If an FCC declaration of conformity marking is present on the board, the following statement applies: FCC Declaration of Conformity This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. For questions related to the EMC performance of this product, contact: Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124 1-800-628-8686 This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures: • Reorient or relocate the receiving antenna. • Increase the separation between the equipment and the receiver. • Connect the equipment to an outlet on a circuit other than the one to which the receiver is connected.
    [Show full text]
  • GMAI: a GPU Memory Allocation Inspection Tool for Understanding and Exploiting the Internals of GPU Resource Allocation in Critical Systems
    The final publication is available at ACM via http://dx.doi.org/ 10.1145/3391896 GMAI: A GPU Memory Allocation Inspection Tool for Understanding and Exploiting the Internals of GPU Resource Allocation in Critical Systems ALEJANDRO J. CALDERÓN, Universitat Politècnica de Catalunya & Ikerlan Technology Research Centre LEONIDAS KOSMIDIS, Barcelona Supercomputing Center (BSC) CARLOS F. NICOLÁS, Ikerlan Technology Research Centre FRANCISCO J. CAZORLA, Barcelona Supercomputing Center (BSC) PEIO ONAINDIA, Ikerlan Technology Research Centre Critical real-time systems require strict resource provisioning in terms of memory and timing. The constant need for higher performance in these systems has led industry to recently include GPUs. However, GPU software ecosystems are by their nature closed source, forcing system engineers to consider them as black boxes, complicating resource provisioning. In this work we reverse engineer the internal operations of the GPU system software to increase the understanding of their observed behaviour and how resources are internally managed. We present our methodology which is incorporated in GMAI (GPU Memory Allocation Inspector), a tool which allows system engineers to accurately determine the exact amount of resources required by their critical systems, avoiding underprovisioning. We first apply our methodology on a wide range of GPU hardware from different vendors showing itsgeneralityin obtaining the properties of the GPU memory allocators. Next, we demonstrate the benefits of such knowledge in resource provisioning of two case studies from the automotive domain, where the actual memory consumption is up to 5.6× more than the memory requested by the application. ACM Reference Format: Alejandro J. Calderón, Leonidas Kosmidis, Carlos F. Nicolás, Francisco J.
    [Show full text]
  • Intel® Desktop Board DG965RY Product Guide
    Intel® Desktop Board DG965RY Product Guide Order Number: D46818-003 Revision History Revision Revision History Date -001 First release of the Intel® Desktop Board DG965RY Product Guide June 2006 -002 Second release of the Intel® Desktop Board DG965RY Product Guide September 2006 -003 Added operating system support December 2006 If an FCC declaration of conformity marking is present on the board, the following statement applies: FCC Declaration of Conformity This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. For questions related to the EMC performance of this product, contact: Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124 1-800-628-8686 This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures: • Reorient or relocate the receiving antenna.
    [Show full text]
  • Intel® Desktop Board DG41TX Product Guide
    Intel® Desktop Board DG41TX Product Guide Order Number: E88309-001 Revision History Revision Revision History Date ® -001 First release of the Intel Desktop Board DG41TX Product Guide February 2010 Disclaimer INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Intel Desktop Board DG41TX may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from Intel Corporation by going to the World Wide Web site at: http://intel.com/ or by calling 1-800-548-4725. Intel and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. * Other names and brands may be claimed as the property of others.
    [Show full text]
  • The Bifrost GPU Architecture and the ARM Mali-G71 GPU
    The Bifrost GPU architecture and the ARM Mali-G71 GPU Jem Davies ARM Fellow and VP of Technology Hot Chips 28 Aug 2016 Introduction to ARM Soft IP . ARM licenses Soft IP cores (amongst other things) to our Silicon Partners . They then make chips and sell to OEMs, who sell consumer devices . “ARM doesn’t make chips”… . We provide all the RTL, integration testbenches, memories lists, reference floorplans, example synthesis scripts, sometimes models, sometimes FPGA images, sometimes with implementation advice, always with memory system requirements/recommendations . Consequently silicon area, power, frequencies, performance, benchmark scores can therefore vary quite a bit in real silicon… 2 © ARM2016 ARM Mali: The world’s #1 shipping GPU 750M 65 27 Mali-based new Mali GPUs shipped 140 Total licenses in in 2015 Total licenses licensees FY15 Mali is in: Mali graphics based IC shipments (units) 750m ~75% ~50% ~40% 550m of of of 400m DTVs… tablets… smartphones 150m <50m 2011 2012 2013 2014 2015 3 © ARM2016 ARM Mali graphics processor generations Mali-G71 BIFROST … GPU Unified shader cores, scalar ISA, clause execution, full coherency, Vulkan, OpenCL MIDGARD Mali-T600 GPU series Mali-T700 GPU series Mali-T800 GPU series Unified shader cores, SIMD ISA, OpenGL ES 3.x, OpenCL, Vulkan Presented at HotChips 2015 Mali-200 Mali-300 Mali-400 Mali-450 Mali-470 UTGARD GPU GPU GPU GPU GPU Separate shader cores, SIMD ISA, OpenGL ES 2.x 4 © ARM2016 Bifrost features . Leverages Mali’s scalable architecture . Scalable to 32 shader cores 20% Scalable to 32 Higher energy Shader cores . Major shader core redesign efficiency* .
    [Show full text]
  • AI Acceleration – Image Processing As a Use Case
    AI acceleration – image processing as a use case Masoud Daneshtalab Associate Professor at MDH www.idt.mdh.se/~md/ Outline • Dark Silicon • Heterogeneouse Computing • Approximation – Deep Neural Networks 2 The glory of Moore’s law Intel 4004 Intel Core i7 980X 2300 transistors 1.17B transistors 740 kHz clock 3.33 GHz clock 10um process 32nm process 10.8 usec/inst 73.4 psec/inst Every 2 Years • Double the number of transistors • Build higher performance general-purpose processors ⁻ Make the transistors available to masses ⁻ Increase performance (1.8×↑) ⁻ Lower the cost of computing (1.8×↓) Semiconductor trends ITRS roadmap for SoC Design Complexity Trens ITRS: International Technology Roadmap for Semiconductors Expected number of processing elements into a System-on-Chip (SoC). 4 Semiconductor trends ITRS roadmap for SoC Design Complexity Trens 5 Semiconductor trends Network-on-Chip (NoC) –based Multi/Many-core Systems Founder: Andreas Olofsson Sponsored by Ericsson AB 6 Dark Silicon Era The catch is powering exponentially increasing number of transistors without melting the chip down. 10 10 Chip Transistor Count 2,200,000,000 109 Chip Power 108 107 106 105 2300 104 103 130 W 102 101 0.5 W 100 1970 1975 1980 1985 1990 1995 2000 2005 2010 2015 If you cannot power them, why bother making them? 7 Dark Silicon Era The catch is powering exponentially increasing number of transistors without melting the chip down. 10 10 Chip Transistor Count 2,200,000,000 109 Chip Power 108 107 Dark Silicon 106 105 (Utilization Wall) 2300 104 Fraction of transistors that need to be 103 powered off at all times due to power 130 W 2 constraints.
    [Show full text]
  • Intel® Desktop Board DG43GT Product Guide
    Intel® Desktop Board DG43GT Product Guide Order Number: E68221-001 Revision History Revision Revision History Date -001 First release of the Intel® Desktop Board DG43GT Product Guide June 2009 If an FCC declaration of conformity marking is present on the board, the following statement applies: FCC Declaration of Conformity This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. For questions related to the EMC performance of this product, contact: Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124 1-800-628-8686 This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures: • Reorient or relocate the receiving antenna. • Increase the separation between the equipment and the receiver. • Connect the equipment to an outlet on a circuit other than the one to which the receiver is connected.
    [Show full text]
  • I.MX Graphics Users Guide Android
    NXP Semiconductors Document Number: IMXGRAPHICUG Rev. 0, 02/2018 i.MX Graphics User’s Guide Contents Chapter 1 Introduction ............................................................................................................................................. 6 Chapter 2 i.MX G2D API ............................................................................................................................................ 6 2.1 Overview ...................................................................................................................................................... 6 2.2 Enumerations and structures ....................................................................................................................... 6 2.3 G2D function descriptions .......................................................................................................................... 10 2.4 Support of new operating system in G2D .................................................................................................. 16 2.5 Sample code for G2D API usage ................................................................................................................. 16 2.6 Feature list on multiple platforms.............................................................................................................. 19 Chapter 3 i.MX EGL and OGL Extension Support .................................................................................................... 20 3.1 Introduction ..............................................................................................................................................
    [Show full text]
  • Intel® Desktop Board DQ33HS Product Guide
    Intel® Desktop Board DQ33HS Product Guide Order Number: E20672-001 Revision History Revision Revision History Date -001 First release of the Intel® Desktop Board DQ33HS Product Guide August 2007 If an FCC declaration of conformity marking is present on the board, the following statement applies: FCC Declaration of Conformity This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. For questions related to the EMC performance of this product, contact: Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124 1-800-628-8686 This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures: • Reorient or relocate the receiving antenna. • Increase the separation between the equipment and the receiver. • Connect the equipment to an outlet on a circuit other than the one to which the receiver is connected.
    [Show full text]
  • The Hitchhiker's Guide to Cross-Platform Opencl Application
    The Hitchhiker’s Guide to Cross-Platform OpenCL Application Development Tyler Sorensen and Alastair F. Donaldson Imperial College London, UK IWOCL April 2016 1 “OpenCL supports a wide range of applications… through a low-level, high-performance, portable abstraction.” Page 11: OpenCL 2.1 specification 2 “OpenCL supports a wide range of applications… through a low-level, high-performance, portable abstraction.” Page 11: OpenCL 2.1 specification 3 “OpenCL supports a wide range of applications… through a low-level, high-performance, portable abstraction.” Page 11: OpenCL 2.1 specification We consider functional portability rather than performance portability 4 Example • single source shortest path application Quadro K5200 (Nvidia) Intel HD5500 5 Example • single source shortest path application Quadro K5200 (Nvidia) Intel HD5500 6 Example • single source shortest path application Quadro K5200 (Nvidia) Intel HD5500 7 An experience report on OpenCL portability • How well is portability evaluated? • Our experience running applications on 8 GPUs spanning 4 vendors • Recommendations going forward 8 An experience report on OpenCL portability • How well is portability evaluated? • Our experience running applications on 8 GPUs spanning 4 vendors • Recommendations going forward 9 Portability in research literature • Reviewed the 50 most recent OpenCL papers on: http://hgpu.org/ • Only considered papers including GPU targets • Only considered papers with some type of experimental evaluation • How many different vendors did the study experiment with?
    [Show full text]