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III IIIII US005475630A United States Patent (19) 11 Patent Number: 5,475,630 Briggs Et Al

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III IIIII US005475630A United States Patent (19) 11 Patent Number: 5,475,630 Briggs Et Al III IIIII US005475630A United States Patent (19) 11 Patent Number: 5,475,630 Briggs et al. 45 Date of Patent: Dec. 12, 1995 54 METHOD AND APPARATUS FOR Selection of Quoitient Digits", IEEE-1983-6th Symposium PERFORMING PRESCALED DIVISION on Computer Arithmetic. Ercegovac, M. D. et al., “A Division Algorithm with Pre 75 Inventors: Willard S. Briggs; David W. Matula, diction of Quotient Digits", IEEE-1985-Comp. Sci. both of Dallas, Tex. Dept., Univ. of CA-LA, pp. 51-56. 73 Assignee: Cyrix Corporation, Richardson, Tex. Fandrianto, J. "Algorithm for High Speed Shared Radix 4 Division & Radix 4 Square Root,” 1987-IEEE, pp. 73-79. 21) Appl. No.: 227,494 Ferrari, Domenico, "A Division Method Using a Parallel Multiplier," IEEE-1967-EC-16:224-226 (1967) pp. 22 Filed: Apr. 12, 1994 191-193. Related U.S. Application Data IEEE Std. 754-1985, "Standard for Binary Floating Point Arithmetic'. 63 Continuation of Ser. No. 179,829, Dec. 22, 1993, aban Coonen, J.T., "Specifications For A Proposed Standard For doned, which is a continuation of Ser. No. 8,890, Jan. 25, 1993, abandoned, which is a continuation of Ser. No. Floating Point Arithmetic', Memo UCB/ERLM78/72, 1978 755,310, Sep. 5, 1991, abandoned. UC at Berkeley. Krishnamurthy, E. V., "On Range-Transformation Tech (51) Int. Cl. .............. G06F 7/S2 niques For Division, IEEE Transactions on Computers', vol. (52) 19, Feb. 1970. (58) Krishnamurthy, E. V., "A More Efficient Range Transfor 56 References Cited mation Algorithm for Signed Digit Division', Int. J. Control, 12, 1970, pp. 73–79. U.S. PATENT DOCUMENTS Nandi, et al. "A Simple Technique For Digital Division' 3,828,175 8/1974 Amdahl et al. ......................... 364/765 Commun. ACM 10, 1967, pp. 299-301. 4,337,519 6/1982 Nishimoto....... ... 364f736 4,338,675 7/1982 Palmer et al. ... ... 364/748 (List continued on next page.) 4,707,798 11/1987 Nakano ........... ... 364,765 4,725,974 2/1988 Kanazawa ... ... 364f765 Primary Examiner Roy N. Envall, Jr. 4,991,132 2/1991 Kadota ........ ... 364f765 Assistant Examiner-Chuong D. Ngo 5,020,017 5/1991. Ooms et al. ... 364f761 5,065,352 11/1991 Nakano ................................... 364/765 Attorney, Agent, or Firm-Andrew S. Viger; John L. Maxin FOREIGN PATENT DOCUMENTS 57 ABSTRACT 0149248 7/1985 European Pat. Off.. An arithmetic circuit 10 for performing prescaled division 0411491 6/1991 European Pat. Off. uses a rectangular multiplier 16 and accumulator 30 oper OTHER PUBLICATIONS able to calculate a short reciprocal and scaled dividend and divisor to enable the sequential iterative calculation of large Atkins, Daniel E., "Higher Radix Division Using Estimates radix quotient digits. Each quotient digit can be calculated of the Divisor & Partial Remainders', IEEE-C17-925-934 using a single pass through the rectangular multiplier 16 and (1968). accumulator 30 and can be accumulated to form a full Bose, et al. "Fast Multiply & Divide for a VLSI Floating Point Unit', IEEE-1987-Dept. of EE & Comp. Sci., Univ. precision quotient in a quotient register 36. of Calif.-Berkeley. Ercegovac, M. D., "A Higher-Radix Division with Simple 21 Claims, 3 Drawing Sheets OYCENC t 4 A: y) 2. RECIPRSCA : SE) 0K 2 A3 RCTMGA8 JPIR -66 : ---- 28 -i. RANCFR Cl fisco El) 33STR &A: is) 3, r 5,475,630 Page 2 OTHER PUBLICATIONS Tung, Chin. "A Division Algorithm For Signed-Digit Arith Parikh, Shrikant, "An Architecture For A Rational Arith metic", IEEE Transactions on Computers vol. 17, 1970. metic Unit', 1988, Dissertation Pres. to Comp. Sci & Wong, et al. "Fast Division Using Accurate Quotient Engineering. Approximations' IEEE-1991, Comp. Sci Press. Svoboda, Antonin, "An Algorithm For Division” Inf. Pro Flynn, Michael, "On Division. By Functional Iteration” cess. Mach. 9, 1963 pp. 25–32. IEEE, vol. C-19, No. 8, Aug. 1970. Taylor, George S., "Compatible Hardware For Division & C. V. Freiman et al., "Composite Division Unit', IBM Square Root," IEEE-1981-Comp. Sci. Div., U of CA, Technical Disclosure Bulletine, vol. 9, No. 8, Jan. 1967 pp. Berkeley. 994-995. U.S. Patent Dec. 12, 1995 . Sheet 1 of 3 5,475,630 12 S BUS DIVISOR RESIDUAL LATCH (e) RECIPROCAL SEED LOOK UP FULL SIDE ABL (R) RECTANGULAR MULTIPLIER (yR'R'(2-yR)yRxRedd, (2) 68 PIPELINE REGISTER (yRyR,xRed ) CONSTANT LATCH ACCUMULATOR (f-e dn.dn+Q.d6+Q-(ulp) o LEFT SHIFT 11 LEFT SHIFT 11 FIC. 1 REMAINDER QUOTIENT REGISTER FRACTION (f) 6 LATCH (X,d) n= U.S. Patent Dec. 12, 1995 Sheet 2 of 3 5,475,630 O BEGIN )--50 FORM f-eded+f LOAD x IN FORM d (266) IN ACC, LOAD 74 52- DIVIDEND LATCH IN MULT, LOAD TO d TO DIGIT LATCH AND LOAD y IN DVISOR LATCH PIPE REGISTER | TO REM FRAC LATCH 54 LOOK UP FORM ed IN d (266)-0 76 R IN MULT, LOAD TO LOAD Q TO PIPE REGISTER QUOTIENT REGISTER FORMyR IN MULT 56N TOPEE REGISTER FORM d (2-66) FORM f-eded--f EN ACC, LOAD 78 56N ACCoAD'ToFORM 2-yR'-y "ESI f3 TOODIGITACH REM FRAC LATCH AND DIW RES LATCH FORM ed INFORM d(2)+Q IN ACC, 80 60 FORM R'(2-yR) IN MULT, LOAD TO LOAD NEW Q TO N MULT PPE REGISTER QUOTIENT REGISTER TRUNCATE 62 R(2-yR)=>R -66 FORM f-edged +f FORM d3 (2) EN ACC, LOAD LOAD RTO INMULOAD 10d. TO DIGITATCH AND 82 DIGIT LATCH PIPE REGISTER | . To REM FRAC LATCH 64 yR=>FORM 1+e FORM ed INFORM d(2)+Q IN ACC, 68 IN MULT IN MULT, LOAD TO LOAD NEW Q TO 84 PIPE REGISTER QUOTIENT REGISTER LOAD e FORM TO DIWATCH RES XR-)R-> d+f FORM, (2) "I",FORM f-ed=>d+f "5 IN MULT, LOAD TO d5 TO DIGIT LATCH AND LOAD di TO LOAD f1 TO PIPE REGISTER To REM FRAC LATCH 86 DIGIT LATCH REM FRACTION QUOTENTREGISTER LATCH 5 70 FORM ed IN MULT TO FIG. 2b 72-1 TO PIPE REGISTER FIG. 2 OL U.S. Patent Dec. 12, 1995 Sheet 3 of 3 5,475,630 FROM FIG. 20 88 FORM eds iN FORM d(2)+Q IN ACC, IN MULT, LOAD TO LOAD NEW Q TO PIPE REGISTER QUOTIENT REGISTER 90 EN ACC, LOAD IN MULT, LOAD TO di TO DIGIT LATCH AND PIPE RECISTER f TO REM FRAC LATCH FORM e ds iN FORM d(2)+Q IN ACC, 92 IN MULT, LOAD TO LOAD NEW O TO PIPE REGISTER QUOTIENT REGISTER INFORM MULT, d LOAD(26) TO FORM fied 94 PIPE REGISTER IN ACC FORM d(2)+Q IN ACC, AND CORRECT NEW Q F fied:0 LOAD NEW Q TO QUOTIENT REGISTER ROUND Q IN ACC 98 Q TO SBUS 100 END FIG. 2b 5,475,630 1. 2 METHOD AND APPARATUS FOR ously cited U.S. Pat. Nos. 5,046,038 and 5,144,579. Previ PERFORMING PRESCALED DEVISION ous teachings on prescaled division have prescribed its use for enhancing methods such as SRT division where two to CROSS-REFERENCE TO RELATED four bits of the quotient are determined in each clock cycle APPLICATIONS using shift and add procedures. The prescaling method has also been described with regards to multiple precision This patent is a continuation of a U.S. patent application arithmetic implemented in software, where a multiplicity of Ser. No. 08/179,829 (now abandoned), which is a continu arithmetic operations must be performed in each iteration to ation of Ser. No. 08/008,890 (now abandoned), which is a effect the extension of the quotient by a unit length typically continuation of Ser. No. 07/755,310 (now abandoned). The O of the order of the machine word size. disclosures of U.S. Pat. Nos. 5,046,038 and 5,144,576, Accordingly, a need has arisen for methods and circuits which are commonly assigned, are incorporated by refer which are capable of performing large radix prescaled eCe. division operations to return the full precision quotient and the sense of the remainder in a minimum amount of clock TECHNICAL FIELD OF THE INVENTION 15 cycles. This invention relates in general to the field of electronic devices and more particularly to methods and systems SUMMARY OF THE ENVENTION operable to perform prescaled division. In accordance with the teachings of the present invention, BACKGROUND OF THE INVENTION 20 methods and systems are described which substantially eliminate or reduce disadvantages and problems associated One of the chief concerns of modern day electronic digital with prior art systems performing the division function. system design is the ability to perform arithmetic functions Particularly, an arithmetic system is described which accurately and quickly. One system for performing the comprises circuitry for generating a short reciprocal of a division function is described in U.S. Pat. No. 5,046,038 25 divisor of a division operation. The system further comprises entitled “METHOD AND APPARATUS FOR PERFORM circuitry for prescaling the dividend and divisor by multi ING DIVISION USING A RECTANGULAR ASPECT plying the dividend and divisor by the short reciprocal. RATIOMULTIPLIER” which issued on Sep. 3, 1991 and is Circuitry is then provided to iteratively calculate a sequence assigned to the Assignee of the present invention, the of large radix quotient digits, which, when accumulated, disclosure of which is hereby incorporated by reference into 30 form the full precision quotient of the prescaled division the present application. The advantages attendant with the operation, and indicate the sense of the corresponding exact use of a rectangular aspect ratio multiplier circuit are remainder. described in the previously cited patent and in U.S Pat. No.
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