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Les Fpgas PLAN Les FPGAs Emmanuel Boutillon Cours réalisé à partir de : Nathalie Julien, cours IUP EEA 1999. Jean-Luc Danger, ENST Paris Cours de l’ISEP disponible sur le WEB Pierre Bomel -1- Emmanuel Boutillon PLAN å Comment et pourquoi faire de la logique programmable ? Les technologies de personnalisation ê PAL, EPLD et FPGA Spécificité du développement des CLPs Situation présente et évolution. -2- Emmanuel Boutillon - 1 - Position du problème Matériel Logiciel circuits personnalisés circuits existants microprocesseurs processeurs DSPs circuits mémoires périphériques ASICs logiques programmables FPGA EPLD -3- Emmanuel Boutillon Position du problème L’intérêt des CLP se justifie (depuis 30 ans) par : Le coûts très important des ASICs Le temps de développement d ’un ASIC Les performances faibles du logiciel La non flexibilité des solutions ASIC « Démocratisation » des FPGA -4- Emmanuel Boutillon - 2 - Coût CLP/ASIC NRE Coût à la pièce le seuil augmente si le nombre de portes baisse ASIC seuil mini = 1000 pièces CLP seuil Nombre de pièces -5- Emmanuel Boutillon Temps de conception ASIC Placement spec Code+synth Routage fab FPGA P Time to market spec Code+synth R µP + spec Code logiciel temps -6- Emmanuel Boutillon - 3 - Les performances f fréquence 80 de traitement circuit personnalisé : traitement parallèle 70 60 F clock 50 40 30 processeur : traitement séquentiel 20 f f = clock 10 nb op/cycle 1 2 3 4 8 12 16 20 24 28 32 36 40 44 48 52 Nb opérations/cycle -7- Emmanuel Boutillon Démocratisation de la conception T0 Temps Tfin log10(complexité) Idée Produit 3 P L C I C S Spécifications n A 4 o i n Dé t o a i v d t i a e l RTL l d 5 op a i l V a p e V Porte me 7 n t Affaire de Transistor Spécialistes avec 8 un équipement Masque lourd 10 Fonderie -8- Emmanuel Boutillon - 4 - Intérêts propres aux CLPs ● prototypage ➯ conception rapide de démonstrateurs ➯ autonomie (pas de fondeur) ● Reprogrammation ➯ maintenance in situ -9- Emmanuel Boutillon Comment faire des CLP ? Un circuit classique contient : - des portes logiques ; - des connections entre les portes logiques ; - des éléments de mémorisation (registre et/ou mémoire) ; - des entrées-sorties. - une (ou des) horloges - une structure hiérarchique Le CLP doit donc avoir les mêmes fonctionnalités, avec la notion de « programmabilité ». -10- Emmanuel Boutillon - 5 - Fonction logique simple : Réseau logique Toute fonction logique booléenne peut s'exprimer sous forme canonique exemple : S = A2A1A0 + A2A1A0 + A2A1A0 + A2A1A0 minterme ou terme produit A Matrice ET i produits des entrées Matrice OU S somme des produits j = Réseau logique programmable -11- Emmanuel Boutillon Mémoire fonction logique 2 entrées : f(A1,A0 ) = f(0,0)A1A0 + f(0,1)A1A0 + f(1,0)A1A0 +f(1,1)A1A0 mémoire 4 mots de 1 bit : d = d0A1A0 + d1A1A0 + d2A1A0 + d3A1A0 A0 A1 adresse=entrées F(A1,A0)=d= A1A0 + A1A0 d0=0 d2=1 d1=1 d3=0 liaison non programmable liaison programmable -12- Emmanuel Boutillon - 6 - Mémoire mémoire 16 mots de 2 bits => 2 fonctions logiques de 4 entrées A0 A 1 matrice A 2 ET A3 adresse=entrées figée matrice S0 OU S programmable 1 liaison non programmable liaison programmable -13- Emmanuel Boutillon LOOK UP TABLE (LUT) Une mémoire contient la table de vérité d ’une fonction logique : Ex : Fonction F(a,b,c) = a xor b xor c 000 0 001 1 F(a,b,c) 010 0 011 1 SRAM 100 0 Adresse 101 1 (a,b,c) 110 0 111 1 => Mode de lecture différent du résultat -14- Emmanuel Boutillon - 7 - PAL Programmable Array Logic A B matrice C D ET programmable S matrice 0 S1 OU S figée 2 S3 liaison non programmable liaison programmable somme de produits = Macrocellule PLD : 4 fonctions de 12 mintermes (max) de 3 variables Au déparet #70-85 : programmation « à la main » (fichier de fusibles) -15- Emmanuel Boutillon cellule logique à MUX l utilisée pour la technologie ANTIFUSIBLE équivaut à une LUT cablée e0 mux e 1 sortie e2 e3 sortie = abe0 ou abe1 ou abe2 ou abe3 a b intérêt : surface réduite cellule grain fin -16- Emmanuel Boutillon - 8 - comparatif des réseaux programmables type structure avantage inconvénient ET •Mémoire conséquente si toutes les fonctions nombreuses entrées MEMOIRE n OU => 22 possibles ET • grand nombre d'entrées PAL Nombre de mintermes limité • économique OU MUX Taille très faible Limité à peu d ’entrées -17- Emmanuel Boutillon Programmation des interconnections Par connexion ou non de deux fils F1 F1 F2 F2 Par l’utilisation de multiplexeur F1’ Le nombre de connexions F1 ! réalisables est limité à ce qui existe... F2 -18- Emmanuel Boutillon - 9 - Programmation des registres et E/S D Registre Q clk rst Possibilité de programmer Possibilité d ’utiliser le PAD en mode entrée ou ou non le registre sortie. -19- Emmanuel Boutillon Système d’entrée sortie complet OE DFF OUT broche DFF IN entrée simple sortie simple bidir la broche peut être : entrée avec DFF (structure FPGA) sortie avec DFF (structure FPGA) inutilisée pour faciliter le routage (structure PAL) avec logique JTAG -20- Emmanuel Boutillon - 10 - Gestion des horloges Mise en place d ’un arbre de d ’horloge pour effectuer de la logique synchrone. Principe : système asservi en phase CLK PLL CLK_OUT Õ compensation le "skew" d'horloge Õ multiplication de la fréquence si diviseur dans la boucle de réaction -21- Emmanuel Boutillon Gestion de la complexité Pour les CLP complexes, il est possible de définir des niveaux de hiérarchie du matériel. => Au niveau des interconnections => Au niveau du regroupement de fonctions logiques Il est aussi possible de diviser le circuit en fonctionnalités différentes : => Zone de mémoire RAM => Zone de CLP => Zone spécialisée -22- Emmanuel Boutillon - 11 - Principes du CLP programmation Entrées / Sorties ou configuration Plan de programmation : interconnexion Entrées / Sorties Entrées / Sorties Plan actif : cellules logiques Entrées/Sorties technologies architectures du plan actif : de programmation : - PAL hiérarchique (EPLD) - EEPROM - gate-array (FPGA) - SRAM - mixtes (CPLD ALTERAs) - antifusible -23- Emmanuel Boutillon PLAN å Comment et pourquoi faire de la logique programmable ? Les technologies de personnalisation ê PAL, EPLD et FPGA Spécificité du développement des CLPs Situation présente et évolution. -24- Emmanuel Boutillon - 12 - Les composants logiques programmables : Les technologies de personnalisation Le circuit est personnalisé par création/destruction de connections sur la structure prédéfinie. ➯ Fusibles ➯ Anti-fusibles ➯ UV PROM (obsolète) EEPROM ➯ SRAM ➯ Métalisation ➯ Comparaison des différents techniques. -25- Emmanuel Boutillon Les composants logiques programmables : Technologie de personnalisation : Fusibles métalliques ou Si Lignes métalliques : interconnexions Intact «Programmé» Problème de l’électro-migration Même structure en ligne polysilicium Ou Transistor «grillable» joue le rôle de fusible -26- Emmanuel Boutillon - 13 - Les composants logiques programmables : Technologie de personnalisation : Antifusibles -27- Emmanuel Boutillon Les composants logiques programmables : Technologie de personnalisation : UV-EPROM / EEPROM Non-volatile SAMOS : Stacked MOS -28- Emmanuel Boutillon - 14 - Les composants logiques programmables : Technologie de personnalisation : SRAM Besoin d’une mémoire externe d’initialisation : Processeur associé ou EEPROM série -29- Emmanuel Boutillon Prédiffusés (Gate Array) ● Circuits génériques au «catalogue» (ressources sans les interconnexions finales) ● Développement / production rapides ● Pas d ’utilisation optimale du Si Les ressources peuvent être uniques (par exemple des NAND) ou plus diversifiées Le routage se fait «dessus» : sea of gate ou «à coté» : row-based Les outils de CAO vont permettre de dériver le dessin du ou des masques de connexions en tenant compte du schéma et du circuit choisi Exemple de métalisation pour obtenir un registre. -30- Emmanuel Boutillon - 15 - Comparaison Critères pour les interconnexions : rapidité de propagation à travers l ’interrupteur (produit résistance - capacité parasite) densité possible des interconnexions (surface de la cellule) facilité d ’utilisation (ISP, support, PROM de configuration) maintien de la configuration (volatile) reprogrammablilité (OTP) Type EPROM Antifusible SRAM d'interconnexion Rapidité -+- Dens ité -+-- Facilité +-+ Reprogrammabilité +non++ -31- Emmanuel Boutillon PLAN å Comment et pourquoi faire de la logique programmable ? Les technologies de personnalisation ê PAL, EPLD et FPGA Spécificité du développement des CLPs Situation présente et évolution. -32- Emmanuel Boutillon - 16 - Taxinomie des CLPs (PLD) Circuits logiques programmable (Programmable Logic Device) PLD EPLD-CPLD FPGA PAL GAL SRAM antifuse UVPROM EECMOS isp Les noms peuvent changer selon ! l‘auteur, le fondeur ... -33- Emmanuel Boutillon Vocabulaire (1) a. PAL, GAL ( Programmable Array Logic, Généric Array Logic). b. EPLD-CPLD (Erasable PLD ou Complex PLD) Les EPLD sont programmables électriquement et effaçables aux UV ; Les EEPLD sont effaçables électriquement Principe similaire aux PAL mais avec interconnexions réalisées en techno UVPROM On trouve également les pLSI et ispLSI (in situ programmable) c. FPGA (Field Programmable Gate Array) C ’est un ensemble de blocs logiques élémentaires que l ’utilisateur peut interconnecter pour réaliser les fonctions logiques de son choix La densité des portes est importante et sans cesse en évolution FPGA à SRAM ou LCA Logic Cell Array (1985 par Xilinx) FPGA à antifusibles (1990 Actel) non effaçables -34- Emmanuel Boutillon - 17 - Vocabulaire (2) ASIC Application Specific Integrated Circuit - Circuit intégré conçu
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