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ESP F14 3 Quark SOC and Galileo Architecture Quark SOC and Galileo Architecture (ESP – Fall 2014) Computer Science & Engineering Department Arizona State University Tempe, AZ 85287 Dr. Yann-Hang Lee [email protected] (480) 727-7507 Real-time Systems Lab, Computer Science and Engineering, ASU Current Processor Design q Moore’s law continues to hold true, transistor counts doubling every 18 months v But can no longer rely upon increasing clock rates and instruction-level parallelism to meet computing performance demands q Semiconductor device fabrication process v 65 nm – 2006, 45 nm – 2008, 32 nm – 2010, and 22 nm – 2012 q How to best exploit ever-increasing on-chip transistor counts? v Multi- & many-core (MC) devices are new technology wave v exploiting explicit parallelism in the new devices q Size and Power constraints Real-time Systems Lab, Computer Science and Engineering, ASU 1 Intel Processors q X86 32/64 architecture v 486 – first pipelined x86 design v Pentium – the first x86 superscalar CPU q Processors for v Server (Xeon), desktop (Core i3/i5/i7), mobile (Core i3/i5/i7), and embedded (Atom) v All of them support hypervisor (VM) q Differences v CPUs, memory, and interconnection bandwidth v reliability (quality of dies) and form factor v power and thermal requirements q Uses available clock cycles and power, not to push up higher clock speeds and energy needs Real-time Systems Lab, Computer Science and Engineering, ASU 2 Galileo Board q 400MHz Quark SoC q 256MB DDR3 q Ethernet q USB Host Port q MicroSD Support q I2C, SPI Support q PCI Express Mini Cards q Serial Connectivity q GPIO q Linux on Board Source: http://www.intel.com/content/www/us/en/intelligent-systems/galileo/galileo-overview.html Real-time Systems Lab, Computer Science and Engineering, ASU 3 Intel Quark SoC X1000. q SOC – v CPU core (x86) v cache, internal memory (flash, SRAM) v IO interfaces and external buses v interconnection or switches v misc (clock, JTAG) q Chip size, power and pins v 32nm process in 1st Quark v one-fifth the size and one-tenth the power of low-end Atom chip v 393 solder balls on 15mm2 v 5 power rails (3.3V, 1.8V, 1.5V, 1.05V, 1.0V) Real-time Systems Lab, Computer Science and Engineering, ASU 4 Pins in Quark q Example: High Speed UART Interface, SIU1_RDX SIU1_TXD Default Buffer State Signal Name Dir Term Power Type S4/S5 S3 Reset Enter S0 SIU0_RXD I 20k(H) 3.3V CMOS3.3 Off Off Pull-up Pull-up SIU0_TXD O - 3.3V CMOS3.3 Off Off VOH VOH q Six different power states v S0 – the system is completely powered ON and fully operational v S5 – the system is completely powered OFF v S1, S2, S3 and S4 – sleeping states, the system appears OFF because of low power consumption and retains enough of the hardware context to return to the working state q In Galileo schematics Real-time Systems Lab, Computer Science and Engineering, ASU 5 Quark Core Internal Architecture q 32-bit RISC integer core q Single cycle execution q Instruction pipelining q Floating-point unit q Cache with cache consistency support (16-Kbyte for both data and instructions) q Memory management unit Real-time Systems Lab, Computer Science and Engineering, ASU 6 486 Pipeline Real-time Systems Lab, Computer Science and Engineering, ASU 7 IO Expander and GPIO Multiplexing q CY8C9540A – I2C interfaced expander v with 40 I/O data pins (ports 0-5) independently configurable as inputs, outputs, bi-directional input/outputs, or PWM outputs q To configure a pin v an I2C control message to the chip which includes a register address Real-time Systems Lab, Computer Science and Engineering, ASU 8 X86 ISA Data Representations q Little-endian byte ordering in memory q Words, doublewords, and quadwords do not need to be aligned in memory on natural boundaries. v 2 memory accesses for an unaligned memory access v aligned accesses require only one q Unsigned integer, signed (two's complement) q FP, string of bits, bytes, .. etc. q SIMD packed data q Pointer v Near v Far (logical) Real-time Systems Lab, Computer Science and Engineering, ASU 9 Memory Model q Flat memory model – a single, continuous linear address space of 232 bytes q Segmented model – a logical address consisting of a segment selector and an offset q Real-address mode – for 8086, v 16 segments of 64K q Linear address space à (paging) physical space Real-time Systems Lab, Computer Science and Engineering, ASU 10 Modes of Operation q Protected mode (32 bits address) v native mode (Windows, Linux), full features, separate memory v virtual-8086 mode q Real-address mode (20 bits address) v the programming environment of the Intel 8086 processor with extensions v native MS-DOS q System management mode v power management, system security, diagnostics q IA-32e (Intel 64 architecture) v Compatibility mode – similar to 32-bit protected mode v 64-bit mode – Ø 16 64-bit general purpose registers Ø default address size is 64 bits and its default operand size is 32 bits. Real-time Systems Lab, Computer Science and Engineering, ASU 11 Programmer’s model Real-time Systems Lab, Computer Science and Engineering, ASU 12 Protected Mode Memory Management q Use segment descriptor to protect memory accesses q Each program has a descriptor table to map segments v allow shared segments q Memory access checks Linear address space v Limit, type, privilege level checks. v Restrictions of addressable domain, unused procedure entry-points, Logical addresses Local Descriptor Table DRAM and instruction set. SS ESP 0018 0000002A DS offset (index) 0010 000001B6 18 0001A000 10 00002A00 08 00001A00 IP 00 00003000 0008 00002CD3 LDTR register Real-time Systems Lab, Computer Science and Engineering, ASU 13 Virtual Memory and Paging q Virtual memory v uses disk as part of the memory, thus allowing sum of all programs can be larger than physical memory v Only part of a program must be kept in memory, while the remaining parts are kept on disk. q The memory used by the program is divided into small units called pages (4096-byte). v OS maintains page directory and page tables v Page translation: CPU converts the linear address into a physical address v Page fault: occurs when a needed page is not in memory, and the CPU interrupts the program q Virtual memory manager (VMM) – OS utility that manages the loading and unloading of pages Real-time Systems Lab, Computer Science and Engineering, ASU 14 Page Translation q A linear address is divided into a page directory field, page table field, and page frame offset. q The CPU uses all three to calculate the physical address. Real-time Systems Lab, Computer Science and Engineering, ASU 15 Interrupt and Exception q Interrupt v an asynchronous event that is typically triggered by an I/O device. q Exception v a synchronous event that is generated when the processor detects one or more predefined conditions while executing an instruction. v three classes of exceptions: faults, traps, and aborts. q 18 predefined interrupts and exceptions and 224 user defined interrupts q Access handler procedures through entries in the interrupt descriptor table (IDT) v A call to a handler procedure is similar to a procedure call to another protection level Real-time Systems Lab, Computer Science and Engineering, ASU 16 Interrupt and Exception q Interrupt vector references v an interrupt gate (interrupt enable (IF) flag in the EFLAGS register is cleared) v a trap gate q Gate contains v access rights information v segment selector for the code segment of the handler procedure v an offset into the code segment to entry point of the handler procedure Real-time Systems Lab, Computer Science and Engineering, ASU 17 Interrupt and APIC q Interrupt in 8086 v Two pins: NMI and INTR v Interrupt Acknowledge Cycle to fetch the interrupt vector number from 8259 q APIC v In Pentium and P6 processors v Receives interrupts and send to core for handling v APIC bus: bi-directional data signals (APICD[1:0]) and clock (APICCLK) v Inter-processor interrupt messages for multi-processor systems v static and dynamic (based on the priority of executing tasks) distribution Real-time Systems Lab, Computer Science and Engineering, ASU 18 Interrupt Handling q IO APIC delivers interrupt message to local APIC v Programmable vector number for each interrupt source q Implied priority based on vector number v local APIC determines when to service the interrupt relative to the other activities of the processor v priority = vector / 16 q Locate gate from IDT v Far call to the handler v (SS, ESP), EFLAGS, CS, EIP, and Error code are saved in stack Real-time Systems Lab, Computer Science and Engineering, ASU 19 Hardware Initialization and Reset q Reset processor state v EIP=0000FFF0h, CS=F000h(segment) and FFFF0000h (base) v Disable paging, cache, and in real-address mode q Execute the first instruction at physical address FFFFFFF0H. v The EPROM containing the software initialization code or BIOS should be located at the upper memory space (including this address) v Run in real-mode, invalidate the TLBs, set up a GDT for selector 0x08 (code) and 0x10 (data), switch to protected mode v Start other components on motherboard (FPU, APIC, southbridge, etc.) Real-time Systems Lab, Computer Science and Engineering, ASU 20 Typical x86 System Architecture System q Chipset Processor Memory Host Bus (PSB) v North Bridge 100/133/200MHz v South Bridge 64-bit v AGP Bus Host Clock Firmware Hub North Bridge Clock PCI Clock q Various chipsets (MCH) Gen USB Clock Hublink Clock available from Intel to HubLink Bus SM Bus meet performance CNR requirements South Bridge (ICH) PCI Bus q FSB, DMI/Hub interface 33 MHz 32-bit q System control hub LAN LPC Bus (SCH) – GMCH and ICH are Audio Mouse merged into one chip USB FWH SIO Keybrd IDE Floppy Parallel Serial Real-time Systems Lab, Computer Science and Engineering, ASU 21 Host Bridge in Quark q A central hub that routes transactions to and from Quark CPU core, DRAM controller, and other functional blocks.
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