DOCSLIB.ORG

Powerpc Core Tutorial Introduction

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Powerpc Core Tutorial Introduction PowerPC Core Tutorial Introduction PURPOSE - To explain the features and functions of the PowerPC Core OBJECTIVES: - Identify the main components of the PowerPC Core. - Describe the PowerPC Core programming model. - Identify the different PowerPC Core instruction types. - Describe the PowerPC conditional branching logic. - Describe the PowerPC addressing capabilities. - Identify the features and functions of PowerPC memory management unit. - Describe PowerPC cache operations. - Describe PowerPC exception handling. CONTENTS: - 56 pages - 10 question LEARNING TIME: - 115 minutes PREREQUISITE: - NetComm Roadmap tutorial Welcome to this tutorial on the PowerPC Core. This tutorial describes the features and functions of the PowerPC Core, which is the central control for all MPC860 functions. Upon completion of this tutorial, you’ll be able to identify the main components of the PowerPC Core and describe its programming model. You’ll be able to identify the different instruction types, including conditional branching. You’ll also be able to describe the important features of the PowerPC, including addressing modes, memory management, cache operations, and exception handling. It’s assumed that you have a basic understanding of the MPC860 and the other NetComm products. Click the Forward arrow when you are ready begin the tutorial. Page 1 MPC860 Components 4K System Interface I Cache Unit I Memory Controller MMU Core U-bus 4K BIU D Cache D System Functions MMU Real Time clock TM PowerPC PCMCIA Interface 4 Parallel I/O Internal Interrupt General 16 Memory Baud Rate Controller Purpose Serial Space Generators Timers DMAs; 2 Virtual Parallel 32-Bit RISC µController IDMA Interface and Program ROM Port Internal Timers Peripheral Bus SCC1 SCC2 SCC3 SCC4 SMC1 SMC2 SPI1 I2C Communications Processor Serial Interface Time Slot Assigner Module Let’s begin this tutorial with an overview of the MPC860 communications processor. The three main functional blocks are the Embedded PowerPC, the System Interface Unit, and the Communications Processor Module. The Embedded PowerPC (EPPC) is the main processor unit including caches and memory management units (MMUs). The System Interface Unit (SIU) provides access to the external data bus and the sub-blocks shown. The Communication Processor Module (CPM) sends and receives data over eight different controllers, both multiplexed or non-multiplexed. A 32-bit RISC controls the transfer of data. This section of the NetComm training module describes the EPPC portion of the MPC8xx family of devices. Page 2 EPPC Main Components I-cache/I-MMU interface D-cache/D-MMU interface Core L-Addr L-Data Sequencer Next address Branch Instruction generation unit queue control bus write back bus (2 slots/clock) Special GPR GPR IMUL/ ALU/ LDST LDST Regs (32 X 32) history IDIV BFU address fix data source busses (4 slots/clock) EPPC Main Components, part 1 Next, let’s take a look at the main components of the EPPC. The sequencer provides centralized control of instruction flow to the execution units. The sequencer includes an instruction address generator, a branch unit, and an instruction queue. The instruction address generator determines the address of the next instruction based on information from the sequential fetcher and the branch unit. The branch unit extracts branch instructions from the fetcher and uses static branch prediction on unresolved conditional branches to allow the instruction unit to fetch instructions. The instruction queue holds and distributes the next instructions to be executed. The special purpose register file contains the registers for control, status, and exception handling information. The general purpose register file, or GPR file, contains the registers for normal integer and pointer operations. The GPR history file holds the results from instructions that have been dispatched but not yet retired. Page 3 EPPC Main Components I-cache/I-MMU interface D-cache/D-MMU interface Core L-Addr L-Data Sequencer Next address Branch Instruction generation unit queue control bus write back bus (2 slots/clock) Special GPR GPR IMUL/ ALU/ LDST LDST Regs (32 X 32) history IDIV BFU address fix data source busses (4 slots/clock) EPPC Main Components, part 2 The integer multiply/divide unit executes all integer multiply and divide instructions. The arithmetic logic and bit field unit executes all other integer and bit instructions. The EPPC includes two queues for loading and storing addresses. The load/store address queue is a two-entry queue shared by all load/store instructions. The load/store fixed point data queue is a two-entry, 32-bit wide queue that holds integer data, also known as fixed-point data. Page 4 EPPC Programming Model Overview • EPPC computations are performed register to register. • No stacking mechanism. • Supervisor mode: - Operating system runs in this mode. - Entire model is available. - Changes for different EPPC implementations. • User mode: - Doesn’t contain system functions. - Used for applications. - Same for all EPPC implementations. In the EPPC, all computations are performed register to register. Information is saved to registers and restored from registers. There is no dedicated stack pointer or automatic stacking mechanism. These functions must be provided using software. The EPPC programming model includes two modes, supervisor mode and user mode. Supervisor mode is the highest privilege and is the mode that the operating system runs in. In supervisor mode, the entire programming model is available to the CPU. Note that supervisor mode is different for different EPPC implementations. In the user mode, or problem mode, the resources that have system-wide impact are not available. Unknown programs, such as applications and untested programs, run in this mode. Applications can run on any EPPC implementation because they all have the same user programming model. The user programming model is essentially a subset of the supervisor model. Let’s take a detailed look at these two models. Page 5 EPPC Programming Model 031 031 GPR0 General Special XER LR GPR1 Purpose Purpose ... Registers Registers CTR ... TB GPR30 TBU GPR31 User Programming Model Instruction Pointer Condition Register (same for all EPPC implementations) 031Supervisor Programming Model Machine State Register contains: MSR ( changes for different EPPC implementations) •State info •Exception enables •MMU enables Standard SPRs Additional SPRs DSISR SPRG1 SPR80-82: SPR560-570: bit manipulation DAR SPRG2 Icache & Dcache of MSR[RI&EE] control/status DEC SPRG3 SRR0 TB(R/W) SPR144-630: SPR784-826: Debug & MMU SRR1 TBU(R/W) development programming support model SPRG0 PVR EPPC Programming Model, Part 1 The user programming model includes thirty-two general-purpose registers, where each register is 32 bits wide. All of these registers operate operate the same way except for some special cases for GPR0. EPPC computations are performed register to register. Information is saved to, and restored from, registers. Another register included in the user programming model is the condition register, CR, consisting of eight, 4-bit fields. We’ll discuss this register in more detail later in the tutorial. The user programming model includes five special purpose registers. SPR1 is the integer exception register, XER, which is used for multi-precision arithmetic. This register includes bits to record overflow, carry, and summary overflow. The link register, LR, stores the return address when a call to a subroutine is invoked. The counter register, CTR, is commonly used as a counter register in loop programs, or as a pointer for some branch instructions. The other two special purpose registers, TB and TBU, are used for the Time Base, which is part of the PowerPC architecture. This is a 64-bit periodically increasing value that can be used as a time stamp. You can access the Time Base through these registers on a read-only basis. Note that the Time Base registers are read-write in Supervisor mode but read-only in User mode. These registers also have different SPR numbers in the two modes. In the supervisor programming model, there is the machine state register, MSR, which contains information about the machine state, such as enabling exceptions or interrupts. There is also a set of standard special purpose registers. The first two standard SPRs are the data storage interrupt source register (DSISR) and the data address register (DAR). These two registers store information when certain exceptions occur, especially error exceptions. The decrementer register, DEC, also functions as part of the PowerPC architecture. The value in this register constantly decrements, and it’s possible to generate an interrupt when the decrementer value reaches zero. Page 6 EPPC Programming Model 031 031 GPR0 General Special XER LR GPR1 Purpose Purpose ... Registers Registers CTR ... TB GPR30 TBU GPR31 User Programming Model Instruction Pointer Condition Register (same for all EPPC implementations) 031Supervisor Programming Model Machine State Register contains: MSR ( changes for different EPPC implementations) •State info •Exception enables •MMU enables Standard SPRs Additional SPRs DSIR SPRG1 SPR80-82: SPR560-570: bit manipulation DAR SPRG2 Icache & Dcache of MSR[RI&EE] control/status DEC SPRG3 SRR0 TB(R/W) SPR144-630: SPR784-826: Debug & MMU SRR1 TBU(R/W) development programming support model SPRG0 PVR EPPC Programming Model, Part 2 The next two registers, the save and restore registers (SRR0 and SRR1), are always used in exception processing. The processor’s exception
Load more

Recommended publications
  • Memory Protection at Option
    Memory Protection at Option Application-Tailored Memory Safety in Safety-Critical Embedded Systems – Speicherschutz nach Wahl Auf die Anwendung zugeschnittene Speichersicherheit in sicherheitskritischen eingebetteten Systemen Der Technischen Fakultät der Universität Erlangen-Nürnberg zur Erlangung des Grades Doktor-Ingenieur vorgelegt von Michael Stilkerich Erlangen — 2012 Als Dissertation genehmigt von der Technischen Fakultät Universität Erlangen-Nürnberg Tag der Einreichung: 09.07.2012 Tag der Promotion: 30.11.2012 Dekan: Prof. Dr.-Ing. Marion Merklein Berichterstatter: Prof. Dr.-Ing. Wolfgang Schröder-Preikschat Prof. Dr. Michael Philippsen Abstract With the increasing capabilities and resources available on microcontrollers, there is a trend in the embedded industry to integrate multiple software functions on a single system to save cost, size, weight, and power. The integration raises new requirements, thereunder the need for spatial isolation, which is commonly established by using a memory protection unit (MPU) that can constrain access to the physical address space to a fixed set of address regions. MPU-based protection is limited in terms of available hardware, flexibility, granularity and ease of use. Software-based memory protection can provide an alternative or complement MPU-based protection, but has found little attention in the embedded domain. In this thesis, I evaluate qualitative and quantitative advantages and limitations of MPU-based memory protection and software-based protection based on a multi-JVM. I developed a framework composed of the AUTOSAR OS-like operating system CiAO and KESO, a Java implementation for deeply embedded systems. The framework allows choosing from no memory protection, MPU-based protection, software-based protection, and a combination of the two.
    [Show full text]
  • A Minimal Powerpc™ Boot Sequence for Executing Compiled C Programs
    Order Number: AN1809/D Rev. 0, 3/2000 Semiconductor Products Sector Application Note A Minimal PowerPCª Boot Sequence for Executing Compiled C Programs PowerPC Systems Architecture & Performance [email protected] This document describes the procedures necessary to successfully initialize a PowerPC processor and begin executing programs compiled using the PowerPC embedded application interface (EABI). The items discussed in this document have been tested for MPC603eª, MPC750, and MPC7400 microprocessors. The methods and source code presented in this document may work unmodiÞed on similar PowerPC platforms as well. This document contains the following topics: ¥ Part I, ÒOverview,Ó provides an overview of the conditions and exceptions for the procedures described in this document. ¥ Part II, ÒPowerPC Processor Initialization,Ó provides information on the general setup of the processor registers, caches, and MMU. ¥ Part III, ÒPowerPC EABI Compliance,Ó discusses aspects of the EABI that apply directly to preparing to jump into a compiled C program. ¥ Part IV, ÒSample Boot Sequence,Ó describes the basic operation of the boot sequence and the many options of conÞguration, explains in detail a sample conÞgurable boot and how the code may be modiÞed for use in different environments, and discusses the compilation procedure using the supporting GNU build environment. ¥ Part V, ÒSource Files,Ó contains the complete source code for the Þles ppcinit.S, ppcinit.h, reg_defs.h, ld.script, and MakeÞle. This document contains information on a new product under development by Motorola. Motorola reserves the right to change or discontinue this product without notice. © Motorola, Inc., 2000. All rights reserved. Overview Part I Overview The procedures discussed in this document perform only the minimum amount of work necessary to execute a user program.
    [Show full text]
  • Memory Management
    Memory Management These slides are created by Dr. Huang of George Mason University. Students registered in Dr. Huang’s courses at GMU can make a single machine readable copy and print a single copy of each slide for their own reference as long as the slide contains the copyright statement, and the GMU facilities are not used to produce the paper copies. Permission for any other use, either in machine-readable or printed form, must be obtained form the author in writing. CS471 1 Memory 0000 A a set of data entries 0001 indexed by addresses 0002 0003 Typically the basic data 0004 0005 unit is byte 0006 0007 In 32 bit machines, 4 bytes 0008 0009 grouped to words 000A 000B Have you seen those 000C 000D DRAM chips in your PC ? 000E 000F CS471 2 1 Logical vs. Physical Address Space The addresses used by the RAM chips are called physical addresses. In primitive computing devices, the address a programmer/processor use is the actual address. – When the process fetches byte 000A, the content of 000A is provided. CS471 3 In advanced computers, the processor operates in a separate address space, called logical address, or virtual address. A Memory Management Unit (MMU) is used to map logical addresses to physical addresses. – Various mapping technologies to be discussed – MMU is a hardware component – Modern processors have their MMU on the chip (Pentium, Athlon, …) CS471 4 2 Continuous Mapping: Dynamic Relocation Virtual Physical Memory Memory Space Processor 4000 The processor want byte 0010, the 4010th byte is fetched CS471 5 MMU for Dynamic Relocation CS471 6 3 Segmented Mapping Virtual Physical Memory Memory Space Processor Obviously, more sophisticated MMU needed to implement this CS471 7 Swapping A process can be swapped temporarily out of memory to a backing store (a hard drive), and then brought back into memory for continued execution.
    [Show full text]
  • Arm System Memory Management Unit Architecture Specification
    Arm® System Memory Management Unit Architecture Specification SMMU architecture version 3 Document number ARM IHI 0070 Document version D.a Document confidentiality Non-confidential Copyright © 2016-2020 Arm Limited or its affiliates. All rights reserved. Arm System Memory Management Unit Architecture Specifica- tion Release information Date Version Changes 2020/Aug/31 D.a• Update with SMMUv3.3 architecture • Amendments and clarifications 2019/Jul/18 C.a• Amendments and clarifications 2018/Mar/16 C• Update with SMMUv3.2 architecture • Further amendments and clarifications 2017/Jun/15 B• Amendments and clarifications 2016/Oct/15 A• First release ii Non-Confidential Proprietary Notice This document is protected by copyright and other related rights and the practice or implementation of the information contained in this document may be protected by one or more patents or pending patent applications. No part of this document may be reproduced in any form by any means without the express prior written permission of Arm. No license, express or implied, by estoppel or otherwise to any intellectual property rights is granted by this document unless specifically stated. Your access to the information in this document is conditional upon your acceptance that you will not use or permit others to use the information for the purposes of determining whether implementations infringe any third party patents. THIS DOCUMENT IS PROVIDED “AS IS”. ARM PROVIDES NO REPRESENTATIONS AND NO WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, SATISFACTORY QUALITY, NON-INFRINGEMENT OR FITNESS FOR A PARTICULAR PURPOSE WITH RESPECT TO THE DOCUMENT. For the avoidance of doubt, Arm makes no representation with respect to, and has undertaken no analysis to identify or understand the scope and content of, patents, copyrights, trade secrets, or other rights.
    [Show full text]
  • Introduction to Uclinux
    Introduction to uClinux V M Introduction to uClinux Michael Opdenacker Free Electrons http://free-electrons.com Created with OpenOffice.org 2.x Thanks to Nicolas Rougier (Copyright 2003, http://webloria.loria.fr/~rougier/) for the Tux image Introduction to uClinux © Copyright 2004-2007, Free Electrons Creative Commons Attribution-ShareAlike 2.5 license http://free-electrons.com Nov 20, 2007 1 Rights to copy Attribution ± ShareAlike 2.5 © Copyright 2004-2007 You are free Free Electrons to copy, distribute, display, and perform the work [email protected] to make derivative works to make commercial use of the work Document sources, updates and translations: Under the following conditions http://free-electrons.com/articles/uclinux Attribution. You must give the original author credit. Corrections, suggestions, contributions and Share Alike. If you alter, transform, or build upon this work, you may distribute the resulting work only under a license translations are welcome! identical to this one. For any reuse or distribution, you must make clear to others the license terms of this work. Any of these conditions can be waived if you get permission from the copyright holder. Your fair use and other rights are in no way affected by the above. License text: http://creativecommons.org/licenses/by-sa/2.5/legalcode Introduction to uClinux © Copyright 2004-2007, Free Electrons Creative Commons Attribution-ShareAlike 2.5 license http://free-electrons.com Nov 20, 2007 2 Best viewed with... This document is best viewed with a recent PDF reader or with OpenOffice.org itself! Take advantage of internal or external hyperlinks. So, don't hesitate to click on them! Find pages quickly thanks to automatic search.
    [Show full text]
  • I.T.S.O. Powerpc an Inside View
    SG24-4299-00 PowerPC An Inside View IBM SG24-4299-00 PowerPC An Inside View Take Note! Before using this information and the product it supports, be sure to read the general information under “Special Notices” on page xiii. First Edition (September 1995) This edition applies to the IBM PC PowerPC hardware and software products currently announced at the date of publication. Order publications through your IBM representative or the IBM branch office serving your locality. Publications are not stocked at the address given below. An ITSO Technical Bulletin Evaluation Form for reader′s feedback appears facing Chapter 1. If the form has been removed, comments may be addressed to: IBM Corporation, International Technical Support Organization Dept. JLPC Building 014 Internal Zip 5220 1000 NW 51st Street Boca Raton, Florida 33431-1328 When you send information to IBM, you grant IBM a non-exclusive right to use or distribute the information in any way it believes appropriate without incurring any obligation to you. Copyright International Business Machines Corporation 1995. All rights reserved. Note to U.S. Government Users — Documentation related to restricted rights — Use, duplication or disclosure is subject to restrictions set forth in GSA ADP Schedule Contract with IBM Corp. Abstract This document provides technical details on the PowerPC technology. It focuses on the features and advantages of the PowerPC Architecture and includes an historical overview of the development of the reduced instruction set computer (RISC) technology. It also describes in detail the IBM Power Series product family based on PowerPC technology, including IBM Personal Computer Power Series 830 and 850 and IBM ThinkPad Power Series 820 and 850.
    [Show full text]
  • Understanding the Linux Kernel, 3Rd Edition by Daniel P
    1 Understanding the Linux Kernel, 3rd Edition By Daniel P. Bovet, Marco Cesati ............................................... Publisher: O'Reilly Pub Date: November 2005 ISBN: 0-596-00565-2 Pages: 942 Table of Contents | Index In order to thoroughly understand what makes Linux tick and why it works so well on a wide variety of systems, you need to delve deep into the heart of the kernel. The kernel handles all interactions between the CPU and the external world, and determines which programs will share processor time, in what order. It manages limited memory so well that hundreds of processes can share the system efficiently, and expertly organizes data transfers so that the CPU isn't kept waiting any longer than necessary for the relatively slow disks. The third edition of Understanding the Linux Kernel takes you on a guided tour of the most significant data structures, algorithms, and programming tricks used in the kernel. Probing beyond superficial features, the authors offer valuable insights to people who want to know how things really work inside their machine. Important Intel-specific features are discussed. Relevant segments of code are dissected line by line. But the book covers more than just the functioning of the code; it explains the theoretical underpinnings of why Linux does things the way it does. This edition of the book covers Version 2.6, which has seen significant changes to nearly every kernel subsystem, particularly in the areas of memory management and block devices. The book focuses on the following topics: • Memory management, including file buffering, process swapping, and Direct memory Access (DMA) • The Virtual Filesystem layer and the Second and Third Extended Filesystems • Process creation and scheduling • Signals, interrupts, and the essential interfaces to device drivers • Timing • Synchronization within the kernel • Interprocess Communication (IPC) • Program execution Understanding the Linux Kernel will acquaint you with all the inner workings of Linux, but it's more than just an academic exercise.
    [Show full text]
  • 18-447: Computer Architecture Lecture 18: Virtual Memory III
    18-447: Computer Architecture Lecture 18: Virtual Memory III Yoongu Kim Carnegie Mellon University Spring 2013, 3/1 Upcoming Schedule • Today: Lab 3 Due • Today: Lecture/Recitation • Monday (3/4): Lecture – Q&A Session • Wednesday (3/6): Midterm 1 – 12:30 – 2:20 – Closed book – One letter-sized cheat sheet • Can be double-sided • Can be either typed or written Readings • Required – P&H, Chapter 5.4 – Hamacher et al., Chapter 8.8 • Recommended – Denning, P. J. Virtual Memory. ACM Computing Surveys. 1970 – Jacob, B., & Mudge, T. Virtual Memory in Contemporary Microprocessors. IEEE Micro. 1998. • References – Intel Manuals for 8086/80286/80386/IA32/Intel64 – MIPS Manual Review of Last Lecture • Two approaches to virtual memory 1. Segmentation • Not as popular today 2. Paging • What is usually meant today by “virtual memory” • Virtual memory requires HW+SW support – HW component is called the MMU • Memory management unit – How to translate: virtual ↔ physical addresses? Review of Last Lecture (cont’d) 1. Segmentation – Divide the address space into segments • Physical Address = BASE + Virtual Address – Case studies: Intel 8086, 80286, x86, x86-64 – Advantages • Modularity/Isolation/Protection • Translation is simple – Disadvantages • Complicated management • Fragmentation • Only a few segments are addressable at the same time Review of Last Lecture (cont’d) 2. Paging – Virtual address space: Large, contiguous, imaginary – Page: A fixed-sized chunk of the address space – Mapping: Virtual pages → physical pages – Page table: The data structure that stores the mappings • Problem #1: Too large – Solution: Hierarchical page tables • Problem #2: Large latency – Solution: Translation Lookaside Buffer (TLB) – Case study: Intel 80386 – Today, we’ll talk more about paging ..
    [Show full text]
  • Virtual Memory and Linux
    Virtual Memory and Linux Matt Porter Embedded Linux Conference Europe October 13, 2016 About the original author, Alan Ott ● Unfortunately, he is unable to be here at ELCE 2016. ● Veteran embedded systems and Linux developer ● Linux Architect at SoftIron – 64-bit ARM servers and data center appliances – Hardware company, strong on software – Overdrive 3000, more products in process Physical Memory Single Address Space ● Simple systems have a single address space ● Memory and peripherals share – Memory is mapped to one part – Peripherals are mapped to another ● All processes and OS share the same memory space – No memory protection! – Processes can stomp one another – User space can stomp kernel mem! Single Address Space ● CPUs with single address space ● 8086-80206 ● ARM Cortex-M ● 8- and 16-bit PIC ● AVR ● SH-1, SH-2 ● Most 8- and 16-bit systems x86 Physical Memory Map ● Lots of Legacy ● RAM is split (DOS Area and Extended) ● Hardware mapped between RAM areas. ● High and Extended accessed differently Limitations ● Portable C programs expect flat memory ● Multiple memory access methods limit portability ● Management is tricky ● Need to know or detect total RAM ● Need to keep processes separated ● No protection ● Rogue programs can corrupt the entire system Virtual Memory What is Virtual Memory? ● Virtual Memory is a system that uses an address mapping ● Maps virtual address space to physical address space – Maps virtual addresses to physical RAM – Maps virtual addresses to hardware devices ● PCI devices ● GPU RAM ● On-SoC IP blocks What is Virtual Memory? ● Advantages ● Each processes can have a different memory mapping – One process's RAM is inaccessible (and invisible) to other processes.
    [Show full text]
  • Memory Management In
    Memory Management Prof. James L. Frankel Harvard University Version of 7:34 PM 2-Oct-2018 Copyright © 2018, 2017, 2015 James L. Frankel. All rights reserved. Memory Management • Ideal memory • Large • Fast • Non-volatile (keeps state without power) • Memory hierarchy • Extremely limited number of registers in CPU • Small amount of fast, expensive memory – caches • Lots of medium speed, medium price main memory • Terabytes of slow, cheap disk storage • Memory manager handles the memory hierarchy Basic Memory Management Three simple ways of organizing memory for monoprogramming without swapping or paging (this is, an operating system with one user process) Multiprogramming with Fixed Partitions • Fixed memory partitions • separate input queues for each partition • single input queue Probabilistic Model of Multiprocessing • Each process is in CPU wait for fraction f of the time • There are n processes with one processor • If the processes are independent of each other, then the probability that all processes are in CPU wait is fn • So, the probability that the CPU is busy is 1 – fn • However, the processes are not independent • They are all competing for one processor • More than one process may be using any one I/O device • Better model would be constructed using queuing theory Modeling Multiprogramming Degree of multiprogramming CPU utilization as a function of number of processes in memory Analysis of Multiprogramming System Performance • Arrival and work requirements of 4 jobs • CPU utilization for 1 – 4 jobs with 80% I/O wait • Sequence of events as jobs arrive and finish • note numbers show amout of CPU time jobs get in each interval Relocation and Protection • At time program is written, uncertain where program will be loaded in memory • Therefore, address locations of variables and code cannot be absolute – enforce relocation • Must ensure that a program does not access other processes’ memory – enforce protection • Static vs.
    [Show full text]
  • Powerpc MMU Simulation
    Computer Science PowerPC MMU Simulation Torbjörn Andersson, Per Magnusson Bachelor’s Project 2001:18 PowerPC MMU Simulation Torbjörn Andersson, Per Magnusson © 2001 Torbjörn Andersson and Per Magnussson, Karlstad University, Sweden This report is submitted in partial fulfilment of the requirements for the Bachelor’s degree in Computer Science. All material in this report which is not our own work has been identified and no material is included for which a degree has previously been conferred. Torbjörn Andersson Per Magnusson Approved, June 6th 2001 Advisor: Choong-ho Yi, Karlstad University Examiner: Stefan Lindskog, Karlstad University iii iv Abstract An instruction-set simulator is a program that simulates a target computer by interpreting the effect of instructions on the computer, one instruction at a time. This study is based on an existing instruction-set simulator, which simulates a general PowerPC (PPC) processor with support for all general instructions in the PPC family. The subject for this thesis work is to enhance the existing general simulator with support for the memory management unit (MMU), with its related instruction-set, and the instruction-set controlling the cache functionality. This implies an extension of the collection of attributes implemented on the simulator with, for example, MMU tables and more specific registers for the target processor. Introducing MMU functionality into a very fast simulator kernel with the aim not to affect the performance too much has been shown to be a non-trivial task. The MMU introduced complexity in the execution that demanded fast and simple solutions. One of the techniques that was used to increase the performance was to cache results from previous address translations and in that way avoid unnecessary recalculations.
    [Show full text]
  • AVR32113: Configuration and Use of the Memory Management Unit
    AVR32113: Configuration and Use of the Memory Management Unit 32-bit Features Microcontrollers • Translation lookaside buffers (TLB) • Protected memory spaces • Variable page size • Uses exceptions for fast and easy management of TLB entries Application Note 1 Introduction Utilizing a memory management unit (MMU) in an application gives the benefit of virtual memory, where different memory pages can point to different physical memory. Virtual memory allows multiple processes to run with address protection and flexible memory mapping. All memory pages are configured individually with respect to size, access privileges and mapping. The AVR®32 MMU hardware has the assignment of converting the virtual addresses requested by the CPU to physical addresses. The MMU also raises exceptions if invalid addresses are accessed or if the running process doesn’t have access to the memory page. The MMU is also used to protect processes from each other, typically by operating systems. A process trying to access the memory segment of another process will be denied by the MMU in the AVR32 device and the CPU is informed by exceptions. To speed up the process of converting from virtual to physical, the AVR32 MMU uses translation buffers, TLB. Depending on the device, it can have separate TLB for instructions and data or a unified TLB for both instructions and data. The AVR32 MMU is fully configurable from software, giving it great amount of flexibility. There are special registers to ease the implementation of the memory management, making it easy to implement and with high performance. Figure 1-1. MMU translating virtual addresses to physical addresses 7 kB - 8 kB 6 kB - 7 kB 5 kB - 6 kB 4 kB - 5 kB 3 kB - 4 kB 3 kB - 4 kB 2 kB - 3 kB MMU 2 kB - 3 kB 1 kB - 2 kB 1 kB - 2 kB TLB entries 0 kB - 1 kB 0 kB - 1 kB Virtual memory Physical memory Rev.
    [Show full text]