DOCSLIB.ORG

A Brief Introduction to Opencl • Reference - Programming Massively Parallel Processors: a Hands-On Approach, David Kirk and Wen-Mei W

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
A Brief Introduction to Opencl • Reference - Programming Massively Parallel Processors: a Hands-On Approach, David Kirk and Wen-Mei W A Brief Introduction to OpenCL • Reference - Programming Massively Parallel Processors: A Hands-on Approach, David Kirk and Wen-mei W. Hwu, Chapter 11 • What is OpenCL? – It is a standardized, cross-platform, parallel-computing API – It is designed to be portable & work with heterogeneous systems – Unlike earlier models, such as OpenMP, OpenCL is designed to address complex memory hierarchies and SIMD computing – Having a more general standard means that it is also more complex; not all devices may support all features and it may be necessary to write adaptable code – In this brief introduction we will look at the data parallelism model and briefly see its application to the molecular visualization problem Data Parallelism Model • There is a direct corres- pondence with CUDA • Host programs are used to launch kernels on OpenCL devices • The index space maps data to the work items • Work items are groups, as in Blocks with CUDA • Work items in the same group can be synchronized • The next slide shows a 2D NDRange (or index space), it is very similar to the CUDA model (except the Work group indices are in the expected order!) Parallel Execution Model Getting global and local values • Thead IDs and Sizes – The API calls and equivalent CUDA code is shown below for dimension 0 (the x dimension) – If the parameter is 1, it corresponds to the y dimension, and 2 for the z dimension Device Architecture • The CPU is a traditional computer that exectures the host program • Here is an OpenCL device – It contains one or more compute units (CU) – Each CU contains one or more processing elements (PE) – There are a variety of memory types Memory Characteristics • Global memory – dynamically allocated by host, has read/write access by both host and devices • Constant memory – dynamically allocated by host (unlike CUDA), read/write by host and read-only by device; a query returns the maximum size supported by the device • Local memory – most closely corresponds to CUDA shared memory, can be dynamically allocated by the host and statically allocated by the device; cannot be accessed by the host (same as CUDA) but can be accessed by all workers in the work group • Private memory – corresponds to CUDA local memory Kernel Functions • Similarities with CUDA – __kernel corresponds to __global in CUDA – A vector add kernel is shown below; two input vectors a and b and one output vector result – All three vectors reside in global memory, the two inputs are const – This is a 1D problem so get_global_id(0) is used to get the thread index – The addition is performed as expected Device Management & Kernel Launch • Now for the “ugly” side of OpenCL – CUDA, which deals with a uniform device from one manufacturer, has hidden the details of launching apps – This is not possible in OpenCL which is designed for many widely varied devices from many manufacturers • An OpenCL context – Use clCreateContext() – Use clGetDeviceIDs() to find all devices – Create a command queue for each device – A sequence of function call are made to insert the kernel code with its execution parameters A “Simple” Example - 1 • Line by Line – Set error code to success – Call create context from type • Include all devices (param 2) • The last argument sets the error code – Line 3 declares parmsz, the size of the memory buffer – Line 4 is the first call to clGetContextInfo • clctx from line 2 is the first param • Param 4 is NULL since the size is not known • There will be another call in line 6 where the missing information is supplied A “Simple” Example - 2 • Line by Line – Line 5 uses malloc to assign to cldevs the address of the buffer – Call clGetContextInfo again in line 6 • The third param is set to parmsz • The fourth param is set to cldevs • The error code is returned – Line 7 creates a command queue for the first device • cldevs is treated as an array and the 2nd param is cldevs[0] • This generates a command queue for the first device in the list returned by clGetContextInfo Electrostatic Potential Map in OpenCL • Step 1: design the organization of NDRange – Threads are now work items; blocks are work groups – Each work item calculates up to eight grid points – Each work group has 64 to 256 work items Mapping DCS NDRange to OpenCL Device • The structure is the same, only the nomenclature is changed Changes in Data Access Indexing • The change are relatively minor – __global__ becomes __kernel – The access to the .x and .y items and arithmetic are replaced by method calls specifying dimension 0 and 1 The Inner Loop of the DCS kernel • The OpenCL code is shown – The logic is basically the same – _rsqrt() has been changed to native_rsqrt Building an OpenCL kernel – Line 1 – declares entire DCS kernel as a string – Line 3 – delivers source code string to the OpenCL run time system – Line 4 – sets up the compiler flags – Line 5 – invokes the runtime compiler to build program – Line 6 – handle to kernel that can be submitted to command queue Host Code for the kernel Launch - 1 Host Code for the kernel Launch - 2 – Lines 1 & 2 : allocate memory for energy grid and atoms – Lines 3 – 6 : sets up arguments to be passed to the kernel – Line 8 : submits the DCS kernel for launch – Lines 9-10 : check for errors, if any – Line 11 : transfers result data in energy array back to host memory – Lines 12-13 : releases memory .
Load more

Recommended publications
  • Map, Reduce and Mapreduce, the Skeleton Way$
    View metadata, citation and similar papers at core.ac.uk brought to you by CORE provided by Elsevier - Publisher Connector Procedia Computer Science ProcediaProcedia Computer Computer Science Science 00 1 (2010)(2012) 1–9 2095–2103 www.elsevier.com/locate/procedia International Conference on Computational Science, ICCS 2010 Map, Reduce and MapReduce, the skeleton way$ D. Buonoa, M. Daneluttoa, S. Lamettia aDept. of Computer Science, Univ. of Pisa, Italy Abstract Composition of Map and Reduce algorithmic skeletons have been widely studied at the end of the last century and it has demonstrated effective on a wide class of problems. We recall the theoretical results motivating the intro- duction of these skeletons, then we discuss an experiment implementing three algorithmic skeletons, a map,areduce and an optimized composition of a map followed by a reduce skeleton (map+reduce). The map+reduce skeleton implemented computes the same kind of problems computed by Google MapReduce, but the data flow through the skeleton is streamed rather than relying on already distributed (and possibly quite large) data items. We discuss the implementation of the three skeletons on top of ProActive/GCM in the MareMare prototype and we present some experimental obtained on a COTS cluster. ⃝c 2012 Published by Elsevier Ltd. Open access under CC BY-NC-ND license. Keywords: Algorithmic skeletons, map, reduce, list theory, homomorphisms 1. Introduction Algorithmic skeletons have been around since Murray Cole’s PhD thesis [1]. An algorithmic skeleton is a paramet- ric, reusable, efficient and composable programming construct that exploits a well know, efficient parallelism exploita- tion pattern. A skeleton programmer may build parallel applications simply picking up a (composition of) skeleton from the skeleton library available, providing the required parameters and running some kind of compiler+run time library tool specific of the target architecture at hand [2].
    [Show full text]
  • From Sequential to Parallel Programming with Patterns
    From sequential to parallel programming with patterns Inverted CERN School of Computing 2018 Plácido Fernández [email protected] 07 Mar 2018 Table of Contents Introduction Sequential vs Parallel patterns Patterns Data parallel vs streaming patterns Control patterns (sequential and parallel Streaming parallel patterns Composing parallel patterns Using the patterns Real world use case GrPPI with NUMA Conclusions Acknowledgements and references 07 Mar 2018 3 Table of Contents Introduction Sequential vs Parallel patterns Patterns Data parallel vs streaming patterns Control patterns (sequential and parallel Streaming parallel patterns Composing parallel patterns Using the patterns Real world use case GrPPI with NUMA Conclusions Acknowledgements and references 07 Mar 2018 4 Source: Herb Sutter in Dr. Dobb’s Journal Parallel hardware history I Before ~2005, processor manufacturers increased clock speed. I Then we hit the power and memory wall, which limits the frequency at which processors can run (without melting). I Manufacturers response was to continue improving their chips performance by adding more parallelism. To fully exploit modern processors capabilities, programmers need to put effort into the source code. 07 Mar 2018 6 Parallel Hardware Processors are naturally parallel: Programmers have plenty of options: I Caches I Multi-threading I Different processing units (floating I SIMD / Vectorization (Single point, arithmetic logic...) Instruction Multiple Data) I Integrated GPU I Heterogeneous hardware 07 Mar 2018 7 Source: top500.org Source: Intel Source: CERN Parallel hardware Xeon Xeon 5100 Xeon 5500 Sandy Bridge Haswell Broadwell Skylake Year 2005 2006 2009 2012 2015 2016 2017 Cores 1 2 4 8 18 24 28 Threads 2 2 8 16 36 48 56 SIMD Width 128 128 128 256 256 256 512 Figure: Intel Xeon processors evolution 0Source: ark.intel.com 07 Mar 2018 11 Parallel considerations When designing parallel algorithms where are interested in speedup.
    [Show full text]
  • Opencl: a Hands-On Introduction
    OpenCL: A Hands-on Introduction Tim Mattson Alice Koniges Intel Corp. Berkeley Lab/NERSC Simon McIntosh-Smith University of Bristol Acknowledgements: In addition to Tim, Alice and Simon … Tom Deakin (Bristol) and Ben Gaster (Qualcomm) contributed to this content. Agenda Lectures Exercises An Introduction to OpenCL Logging in and running the Vadd program Understanding Host programs Chaining Vadd kernels together Kernel programs The D = A + B + C problem Writing Kernel Programs Matrix Multiplication Lunch Working with the OpenCL memory model Several ways to Optimize matrix multiplication High Performance OpenCL Matrix multiplication optimization contest The OpenCL Zoo Run your OpenCL programs on a variety of systems. Closing Comments Course materials In addition to these slides, C++ API header files, a set of exercises, and solutions, we provide: OpenCL C 1.2 Reference Card OpenCL C++ 1.2 Reference Card These cards will help you keep track of the API as you do the exercises: https://www.khronos.org/files/ opencl-1-2-quick-reference-card.pdf The v1.2 spec is also very readable and recommended to have on-hand: https://www.khronos.org/registry/ cl/specs/opencl-1.2.pdf AN INTRODUCTION TO OPENCL Industry Standards for Programming Heterogeneous Platforms GPUs CPUs Emerging Increasingly general Multiple cores driving Intersection purpose data-parallel performance increases computing Graphics Multi- Heterogeneous APIs and processor Computing Shading programming – Languages e.g. OpenMP OpenCL – Open Computing Language Open, royalty-free standard for portable, parallel programming of heterogeneous parallel computing CPUs, GPUs, and other processors The origins of OpenCL ARM AMD Merged, needed Nokia commonality IBM ATI across products Sony Wrote a rough draft Qualcomm GPU vendor – straw man API Imagination wants to steal TI NVIDIA market share from CPU + many more Khronos Compute CPU vendor – group formed wants to steal Intel market share from GPU Was tired of recoding for many core, GPUs.
    [Show full text]
  • Mapreduce Basics
    Chapter 2 MapReduce Basics The only feasible approach to tackling large-data problems today is to divide and conquer, a fundamental concept in computer science that is introduced very early in typical undergraduate curricula. The basic idea is to partition a large problem into smaller sub-problems. To the extent that the sub-problems are independent [5], they can be tackled in parallel by different workers| threads in a processor core, cores in a multi-core processor, multiple processors in a machine, or many machines in a cluster. Intermediate results from each individual worker are then combined to yield the final output.1 The general principles behind divide-and-conquer algorithms are broadly applicable to a wide range of problems in many different application domains. However, the details of their implementations are varied and complex. For example, the following are just some of the issues that need to be addressed: • How do we break up a large problem into smaller tasks? More specifi- cally, how do we decompose the problem so that the smaller tasks can be executed in parallel? • How do we assign tasks to workers distributed across a potentially large number of machines (while keeping in mind that some workers are better suited to running some tasks than others, e.g., due to available resources, locality constraints, etc.)? • How do we ensure that the workers get the data they need? • How do we coordinate synchronization among the different workers? • How do we share partial results from one worker that is needed by an- other? • How do we accomplish all of the above in the face of software errors and hardware faults? 1We note that promising technologies such as quantum or biological computing could potentially induce a paradigm shift, but they are far from being sufficiently mature to solve real world problems.
    [Show full text]
  • CUDA C++ Programming Guide
    CUDA C++ Programming Guide Design Guide PG-02829-001_v11.4 | September 2021 Changes from Version 11.3 ‣ Added Graph Memory Nodes. ‣ Formalized Asynchronous SIMT Programming Model. CUDA C++ Programming Guide PG-02829-001_v11.4 | ii Table of Contents Chapter 1. Introduction........................................................................................................ 1 1.1. The Benefits of Using GPUs.....................................................................................................1 1.2. CUDA®: A General-Purpose Parallel Computing Platform and Programming Model....... 2 1.3. A Scalable Programming Model.............................................................................................. 3 1.4. Document Structure................................................................................................................. 5 Chapter 2. Programming Model.......................................................................................... 7 2.1. Kernels.......................................................................................................................................7 2.2. Thread Hierarchy...................................................................................................................... 8 2.3. Memory Hierarchy...................................................................................................................10 2.4. Heterogeneous Programming................................................................................................11 2.5. Asynchronous
    [Show full text]
  • Programming Massively Parallel Processors
    APPENDIX An introduction to OpenCL A CHAPTER OUTLINE A.1 Background .......................................................................................................461 A.2 Data Parallelism Model ......................................................................................462 A.3 Device Architecture ............................................................................................464 A.4 Kernel Functions ................................................................................................466 A.5 Device Management and Kernel Launch ..............................................................466 A.6 Electrostatic Potential Map in OpenCL .................................................................469 A.7 Summary ...........................................................................................................473 A.8 Exercises ...........................................................................................................474 References ...............................................................................................................474 In this appendix, we will give a brief overview of OpenCL for CUDA programers. The fundamental programing model of OpenCL is so similar to CUDA that there is a one-to-one correspondence for most features. With your understanding of CUDA, you will be able to start writing OpenCL programs with the material presented in this appendix. In our opinion, the best way to learn OpenCL is actually to learn CUDA first and then map the OpenCL features
    [Show full text]
  • A Case Study of Openmp Applied to Map/Reduce-Style Computations
    A Case Study of OpenMP applied to Map/Reduce-style Computations Arif, M., & Vandierendonck, H. (2015). A Case Study of OpenMP applied to Map/Reduce-style Computations. In OpenMP: Heterogenous Execution and Data Movements (Vol. 9342, pp. 162-174). (Lecture Notes in Computer Science). https://doi.org/10.1007/978-3-319-24595-9_12 Published in: OpenMP: Heterogenous Execution and Data Movements Document Version: Peer reviewed version Queen's University Belfast - Research Portal: Link to publication record in Queen's University Belfast Research Portal Publisher rights Copyright Springer 2015. The final publication is available at Springer via http://dx.doi.org/10.1007/978-3-319-24595-9_12. General rights Copyright for the publications made accessible via the Queen's University Belfast Research Portal is retained by the author(s) and / or other copyright owners and it is a condition of accessing these publications that users recognise and abide by the legal requirements associated with these rights. Take down policy The Research Portal is Queen's institutional repository that provides access to Queen's research output. Every effort has been made to ensure that content in the Research Portal does not infringe any person's rights, or applicable UK laws. If you discover content in the Research Portal that you believe breaches copyright or violates any law, please contact [email protected]. Download date:01. Oct. 2021 A Case Study of OpenMP applied to Map/Reduce-Style Computations Mahwish Arif Hans Vandierendonck School of Electronics, Electrical Engineering and Computer Science, Queen's University Belfast, UK Keywords: OpenMP, map/reduce, reduction As data analytics are growing in importance they are also quickly becoming one of the dominant application domains that require parallel processing.
    [Show full text]
  • A Review of CUDA, Mapreduce, and Pthreads Parallel Computing Models
    A Review of CUDA, MapReduce, and Pthreads Parallel Computing Models Kato Mivule1, Benjamin Harvey2, Crystal Cobb3, and Hoda El Sayed4 1 Computer Science Department, Bowie State University, Bowie, MD, USA [email protected] [email protected] [email protected] [email protected] Abstract – The advent of high performance computing models to assist high performance computing users (HPC) and graphics processing units (GPU), present an with a faster understanding of parallel programming enormous computation resource for Large data concepts and thus better implementation of big data transactions (big data) that require parallel processing for parallel programming projects. Although a number of robust and prompt data analysis. While a number of HPC models could have been chosen for this overview, we frameworks have been proposed, parallel programming focused on CUDA, MapReduce, and Pthreads models present a number of challenges – for instance, how to fully utilize features in the different programming models because of the underlying features in the three to implement and manage parallelism via multi-threading models that could be used to for multi-threading. The in both CPUs and GPUs. In this paper, we take an rest of this paper is organized as follows: In Section overview of three parallel programming models, CUDA, 2, a review of the latest literature on parallel MapReduce, and Pthreads. The goal is to explore literature computing models and determinism is done. In on the subject and provide a high level view of the features Section 3, an overview of CUDA is given, while in presented in the programming models to assist high Section a review of MapReduce features is performance users with a concise understanding of parallel presented.
    [Show full text]
  • Parallel Design Patterns
    Parallel design patterns M. Danelutto Introduction Parallel design Parallel design patterns patterns Finding concurrency design space Marco Danelutto Algorithm Structure design space Dept. of Computer Science, University of Pisa, Italy Supporting structures design space May 2011, Pisa Implementation mechanisms design space Conclusions Contents Parallel design patterns M. Danelutto 1 Introduction Introduction Parallel design 2 Parallel design patterns patterns Finding concurrency 3 Finding concurrency design space design space Algorithm 4 Algorithm Structure design space Structure design space Supporting 5 Supporting structures design space structures design space Implementation 6 Implementation mechanisms design space mechanisms design space Conclusions 7 Conclusions T s(n) = seq (speedup) Tpar (n) T d T (n) = i = seq (efficiency) Tpar (n) n × Tpar (n) 1 s(n) = 1−f (Amdhal law) f + n Parallel computing Parallel design patterns M. Danelutto The problem Introduction Solve a problem using nw processing resources Parallel design Obtaining a (close to) nw speedup with respect to time patterns spent sequentially Finding concurrency design space Algorithm Structure design space Supporting structures design space Implementation mechanisms design space Conclusions Parallel computing Parallel design patterns M. Danelutto The problem Introduction Solve a problem using nw processing resources Parallel design Obtaining a (close to) nw speedup with respect to time patterns spent sequentially Finding concurrency design space Algorithm Tseq Structure s(n) = (speedup) design space Tpar (n) Supporting structures Ti d Tseq design space (n) = = (efficiency) Implementation Tpar (n) n × Tpar (n) mechanisms design space 1 Conclusions s(n) = 1−f (Amdhal law) f + n Parallelism exploitation program activities (threads, processes) program interactions (communications, sycnhronizations) ! overhead The problems Parallel design patterns M.
    [Show full text]
  • Memcuda: Map Device Memory to Host Memory on GPGPU Platform*
    memCUDA: Map Device Memory to Host Memory on GPGPU Platform* Hai Jin, Bo Li, Ran Zheng, Qin Zhang, and Wenbing Ao Services Computing Technology and System Lab Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology, Wuhan, 430074, China [email protected] Abstract. The Compute Unified Device Architecture (CUDA) programming environment from NVIDIA is a milestone towards making programming many-core GPUs more flexible to programmers. However, there are still many challenges for programmers when using CUDA. One is how to deal with GPU device memory, and data transfer between host memory and GPU device mem- ory explicitly. In this study, source-to-source compiling and runtime library technologies are used to implement an experimental programming system based on CUDA, called memCUDA, which can automatically map GPU device memory to host memory. With some pragma directive language, programmer can directly use host memory in CUDA kernel functions, during which the te- dious and error-prone data transfer and device memory management are shielded from programmer. The performance is also improved with some near-optimal technologies. Experiment results show that memCUDA programs can get similar effect with well-optimized CUDA programs with more compact source code. Keywords: GPU, CUDA, memory mapping, programming model. 1 Introduction In the past decade, the era of multi-core computer processor is coming due to power and performance limitations of VLSI design. As a new computing platform, GPGPUs become more and more attractive because they offer extensive resources even for non-visual, general-purpose computations: massive parallelism, high memory band- width, and general-purpose instruction sets.
    [Show full text]
  • Openmp Advanced Overview SIMD and Target Offload
    OpenMP Advanced Overview SIMD and Target Offload Doug Jacobsen, Intel Corporation John Pennycook, Intel Corporation Tim Mattson, Intel Corporation Alejandro Duran, Intel Corporation Intel, the Intel logo, Intel® Xeon Phi™, Intel® Xeon® Processor are trademarks of Intel Corporation in the U.S. and/or other countries. *Other names and brands may be claimed as the property of others. See Trademarks on intel.com for full list of Intel trademarks. Topics • We Will Cover: • Accelerated OpenMP* basics review • Vectorization and OpenMP* SIMD • OpenMP* Device Usage (target) • We will NOT Cover: • Detailed OpenMP* basics usage • OpenMP* Tasking • Affinity • NUMA effects • Reference material in backup: • Interface descriptions for all described constructs • Brief Introduction to OpenMP* 5.0 Changes 2 © 2018 Intel Corporation OpenMP* Review 3 © 2018 Intel Corporation OpenMP* Basics Review OpenMP*: . Application Program Interface (API) focused on the expression of parallelism within an application . Provides methods for creating multi-threaded, heterogeneous device, and vectorized applications . Contains standardized directives and library functions . Supports C, C++, and Fortran . Was established in 1997 4 © 2018 Intel Corporation OpenMP* Threads Threads are the original and most basic concept within OpenMP*. A master thread spawns a team of threads when it encounters a parallel region Threads can distribute work among themselves to accomplish the same task faster, or can work on independent tasks in parallel. 5 © 2018 Intel Corporation OpenMP* Directive Overview Directive Description #pragma omp parallel Create threads in a parallel region !$omp parallel #pragma omp for Distribute iterations of a loop !$omp do among threads #pragma omp for reduction(+:sum) Distribute iterations of a loop !$omp do reduction(+:sum) among threads, and reduce the thread private ‘sum’ after the loop is complete.
    [Show full text]
  • A Parallel Implementation of the Self Organising Map Using Opencl
    A Parallel Implementation of the Self Organising Map using OpenCL Gavin Davidson School of Computing Science Sir Alwyn Williams Building University of Glasgow G12 8QQ Level 4 Project — 27th March 2015 Abstract The self organising map is a machine learning algorithm used to produce low dimensional representations of high dimensional data. While the process is becoming more and more useful with the rise of big data, it is hindered by the sheer amount of time the algorithm takes to run serially. This project produces a parallel version of the classical algorithm using OpenCL that is suited for use on parallel processor architectures. The use of the Manhattan distance metric is also explored as a replacement for the traditional Euclidean distance in an attempt to decrease run times. The output from the parallel program is compared to that of a widely used package, SOM PAK, to ensure validity. The parallel implementation is tested on a variety of architectures, including graphics hardware, to determine which parameters run times. A 10x speed up is demonstrated when compared with SOM PAK. Education Use Consent I hereby give my permission for this project to be shown to other University of Glasgow students and to be distributed in an electronic format. Please note that you are under no obligation to sign this declaration, but doing so would help future students. Name: Signature: i Acknowledgements I would firstly like to thank my supervisor Dr Vanderbauwhede for proposing such an interesting project and also for providing sound advice whenever it was needed. I’d also like to thank Rachel for her constant patience while I continually talked about a subject she has no interest in and for her help in proof reading this report.
    [Show full text]