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ADV7181B Multiformat SDTV Video Decoder Data Multiformat SDTV Video Decoder ADV7181B FEATURES Multiformat video decoder supports NTSC-(M, J, 4.43), Differential phase: 0.6° typ PAL-(B/D/G/H/I/M/N), SECAM Programmable video controls: Integrates three 54 MHz, 9-bit ADCs Peak white/hue/brightness/saturation/contrast Clocked from a single 27 MHz crystal Integrated on-chip video timing generator Line-locked clock-compatible (LLC) Free-run mode (generates stable video ouput with no I/P) Adaptive Digital Line Length Tracking (ADLLT™), signal VBI decode support for close captioning, WSS, CGMS, EDTV, processing, and enhanced FIFO management give mini Gemstar® 1×/2× TBC functionality Power-down mode 5-line adaptive comb filters 2-wire serial MPU interface (I2C®-compatible) Proprietary architecture for locking to weak, noisy, and 3.3 V analog, 1.8 V digital core; 3.3 V IO supply unstable video sources such as VCRs and tuners Temperature grade:–40°C to +85°C Subcarrier frequency lock and status information output 80-lead LQFP Pb-free package Integrated AGC with adaptive peak white mode Macrovision® copy protection detection APPLICATIONS CTI (chroma transient improvement) DVD recorders DNR (digital noise reduction) PC Video Multiple programmable analog input formats: HDD-based PVRs/DVDRs CVBS (composite video) LCD TVs S-Video (Y/C) Set-top boxes YPrPb component (VESA, MII, SMPTE, and BetaCam) Security systems 6 analog video input channels Digital televisions Automatic NTSC/PAL/SECAM identification Portable video devices Digital output formats (8-bit or16-bit): Automotive entertainment ITU-R BT.656 YCrCb 4:2:2 output + HS, VS, and FIELD 0.5 V to 1.6 V analog signal input range AVR receiver Differential gain: 0.6% typ GENERAL DESCRIPTION The ADV7181B integrated video decoder automatically detects video signal peak-to-peak range of 0.5 V to 1.6 V. Alternatively, and converts a standard analog baseband television signal- these can be bypassed for manual settings. compatible with worldwide standards NTSC, PAL, and SECAM The fixed 54 MHz clocking of the ADCs and datapath for all into 4:2:2 component video data-compatible with 16-/8-bit modes allows very precise, accurate sampling and digital CCIR601/CCIR656. filtering. The line-locked clock output allows the output data The advanced and highly flexible digital output interface rate, timing signals, and output clock signals to be synchronous, enables performance video decoding and conversion in line- asynchronous, or line locked even with ±5% line length locked clock-based systems. This makes the device ideally variation. The output control signals allow glueless interface suited for a broad range of applications with diverse analog connections in almost any application. The ADV7181B modes 2 video characteristics, including tape based sources, broadcast are set up over a 2-wire, serial, bidirectional port (I C- sources, security/surveillance cameras, and professional compatible). systems. The ADV7181B is fabricated in a 3.3 V CMOS process. Its The 6 analog input channels accept standard Composite, monolithic CMOS construction ensures greater functionality S-Video, YPrPb video signals in an extensive number of with lower power dissipation. combinations. AGC and clamp restore circuitry allow an input The ADV7181B is packaged in a small 80-lead LQFP Pb-free package. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. or otherwise under any patent or patent rights of Analog Devices. Trademarks and Tel: 781.329.4700 www.analog.com registered trademarks are the property of their respective owners. Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. ADV7181B TABLE OF CONTENTS Introduction ...................................................................................... 3 Luma Filter .................................................................................. 25 Analog Front End......................................................................... 3 Chroma Filter.............................................................................. 28 Standard Definition Processor ................................................... 3 Gain Operation........................................................................... 29 Functional Block Diagram .............................................................. 4 Chroma Transient Improvement (CTI) .................................. 32 Specifications..................................................................................... 5 Digital Noise Reduction (DNR)............................................... 33 Electrical Characteristics............................................................. 5 Comb Filters................................................................................ 34 Video Specifications..................................................................... 6 AV Code Insertion and Controls ............................................. 36 Timing Specifications .................................................................. 7 Synchronization Output Signals............................................... 38 Analog Specifications................................................................... 7 Sync Processing .......................................................................... 45 Thermal Specifications ................................................................ 8 VBI Data Decode ....................................................................... 46 Timing Diagrams.......................................................................... 8 Pixel Port Configuration ............................................................... 58 Absolute Maximum Ratings............................................................ 9 MPU Port Description................................................................... 59 ESD Caution.................................................................................. 9 Register Accesses ........................................................................ 60 Pin Configuration and Function Descriptions........................... 10 Register Programming............................................................... 60 Analog Front End ........................................................................... 12 I2C Sequencer.............................................................................. 60 Analog Input Muxing ................................................................ 12 I2C Register Maps ........................................................................... 61 Global Control Registers ............................................................... 14 I2C Register Map Details ........................................................... 66 Power-Save Modes...................................................................... 14 I2C Programming Examples.......................................................... 88 Reset Control .............................................................................. 14 Mode 1 CVBS Input (Composite Video on AIN6)................ 88 Global Pin Control ..................................................................... 15 Mode 2 S-Video Input (Y on AIN1 and C on AIN4) ............ 88 Global Status Registers................................................................... 17 Mode 3 525i/625i YPrPb Input (Y on AIN1, Pr on AIN3, and Pb on AIN5)................................................................................ 89 Identification............................................................................... 17 Mode 4 CVBS Tuner Input CVBS PAL on AIN6................... 89 Status 1 ......................................................................................... 17 PCB Layout Recommendations.................................................... 90 Autodetection Result.................................................................. 17 Analog Interface Inputs............................................................. 90 Status 2 ......................................................................................... 17 Power Supply Decoupling ......................................................... 90 Status 3 ......................................................................................... 18 PLL ............................................................................................... 90 Standard Definition Processor (SDP).......................................... 19 Digital Outputs (Both Data and Clocks)................................. 90 SD Luma Path ............................................................................. 19 Digital Inputs .............................................................................. 91 SD Chroma Path......................................................................... 19 Antialiasing Filters ..................................................................... 91 Sync Processing........................................................................... 20 Typical Circuit Connection........................................................... 92 VBI Data Recovery..................................................................... 20 Outline Dimensions......................................................................
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