sustainability
Article Multi-Port High Voltage Gain Modular Power Converter for Offshore Wind Farms
Sen Song 1, Yihua Hu 1 ID , Kai Ni 1,* ID , Joseph Yan 1, Guipeng Chen 2, Huiqing Wen 3 and Xianming Ye 4 1 Department of Electrical Engineering and Electronics, The University of Liverpool, Liverpool L69 3BX, UK; [email protected] (S.S.); [email protected] (Y.H.); [email protected] (J.Y.) 2 College of Electrical Engineering, Zhejiang University, Hangzhou 310027, China; [email protected] 3 Department of Electrical Engineering and Electronics, Xi’an Jiaotong-Liverpool University, Suzhou 215123, China; [email protected] 4 Department of Electrical, Electronic and Computer Engineering, University of Pretoria, Pretoria 0084, South Africa; [email protected] * Correspondence: [email protected]; Tel.: +44-751-920-3720
Received: 30 May 2018; Accepted: 25 June 2018; Published: 26 June 2018
Abstract: In high voltage direct current (HVDC) power transmission of offshore wind power systems, DC/DC converters are applied to transfer power from wind generators to HVDC terminals, and they play a crucial role in providing a high voltage gain, high efficiency, and high fault tolerance. This paper introduces an innovative multi-port DC/DC converter with multiple modules connected in a scalable matrix configuration, presenting an ultra-high voltage step-up ratio and low voltage/current rating of components simultaneously. Additionally, thanks to the adoption of active clamping current-fed push–pull (CFPP) converters as sub-modules (SMs), soft-switching is obtained for all power switches, and the currents of series-connected CFPP converters are auto-balanced, which significantly reduce switching losses and control complexity. Furthermore, owing to the expandable matrix structure, the output voltage and power of a modular converter can be controlled by those of a single SM, or by adjusting the column and row numbers of the matrix. High control flexibility improves fault tolerance. Moreover, due to the flexible control, the proposed converter can transfer power directly from multiple ports to HVDC terminals without bus cable. In this paper, the design of the proposed converter is introduced, and its functions are illustrated by simulation results.
Keywords: high voltage direct current (HVDC); power transmission; DC/DC converter; high voltage gain; modular; multi-port
1. Introduction The global number of offshore wind farms has increased in recent years [1,2]. In Europe, 560 new offshore wind turbines were built in 17 wind farms in 2017 with a total generation capacity of 3148 MW, which is about 20% of the total offshore generation capacity [3]. The power generated offshore is typically transmitted over an average distance of 41 km (in 2017) through submarine cables before reaching a connection point with the existing onshore grid [3]. For example, Hornsea wind farm is located around 40 km from the onshore station. Compared with high voltage alternating current (HVAC) transmission, high voltage direct current (HVDC) transmission is the preferred method to transfer power over a long distance (>40 km) in terms of the factors of economy and power efficiency [4,5]. When delivering the same amount of power, the purchase price for the bipolar HVDC cable is lower than that of two parallel 3-core HVAC ones [6]. Additionally, HVDC has a higher transmission efficiency than HVAC since no inductance-reactive power exists within DC transmission cables.
Sustainability 2018, 10, 2176; doi:10.3390/su10072176 www.mdpi.com/journal/sustainability Sustainability 2018, 10, x FOR PEER REVIEW 2 of 15
Sustainabilitytransmission2018 , efficiency10, 2176 than HVAC since no inductance-reactive power exists within2 of DC 15 transmission cables. Figure 1 presents three HVDC configurations. The hybrid HVDC system illustrated in Figure 1a uses Figurea medium1 presents voltage three (MV) HVDC—high configurations. voltage (HV) AC/DC The hybrid converter HVDC to systemobtain high illustrated voltage in DC Figure power.1a usesHowever, a medium line-frequency voltage (MV)—high (50/60 Hz) voltage AC/AC (HV) transformers AC/DC converterfor low-voltage to obtain (LV) high—MV voltage conversion DC power. still However,occupy a significant line-frequency portion (50/60 of the Hz) substation AC/AC transformers space. In this for topology, low-voltage the transformer (LV)—MV conversion is replaced still by occupya converter a significant as shown portion in Figure of the 1b,substation which significantly space. In thisreduces topology, the system the transformer size and weight is replaced [7]. These by a convertertwo configurati as shownons in use Figure two1-b,stage which conversion significantly to reduces meet the the voltage system sizelevel and of weight HVDC [ transmission.7]. These two configurationsHowever, Reference use two-stage [8] points conversion out that the to meetconfiguration the voltage of leveltwo DC/DC of HVDC conversion transmission. stages However, has the Referencehighest power [8] points loss, which out that is thearound configuration four times of that two of DC/DC a one conversion conversion stage stages confi hasguration the highest presented power loss,in Figure which 1c is taking around into four consider times thatation of the a one winding conversion and stagecore losses configuration of transformers presented and in the Figure given1c takingdatasheets into of consideration the semiconductors. the winding The andconverter core losses applied of transformersin Figure 1c not and only the provides given datasheets a high voltage of the semiconductors.gain but also transfers The converterpower directly applied from in multiple Figure1c generators not only provides to HVDC a terminals high voltage without gain bus but cable. also transfersThe converter power design directly is from a technical multiple challenge generators for to HVDC boosting terminals LV directly without to bus HV cable. due to The the converter conflict designbetween is a the technical required challenge high voltage for boosting level,LV e.g. directly, ±800 to kV HV [9] due and to the the conflictrestricted between voltage the ratings required of highsemiconductor voltage level, components, e.g., ±800 kV e.g. [9, ]22 and kV the for restricted SiC thyristors, voltage ratings and 15 of kV semiconductor for SiC transistors components, [10]. e.g.,Fortunately, 22 kV for with SiC thyristors,the development and 15 kVof semiconductors for SiC transistors and [10 converter]. Fortunately, topologies, with the possible development solutions of semiconductorsare provided [11 and–13] converter. topologies, possible solutions are provided [11–13].
LV AC LV-MV MV-HV LV-MV MV DC MV-HV Wind Turbine Generators Wind Turbine Generators Bus AC/AC AC/DC DC/DC Bus DC/DC
GB AC/DC = GB AC/DC/AC = . . . = . . . = HVDC
. = HVDC . .
transimission transmission
GB AC/DC/AC GB AC/DC = =
(a) (b) LV-HV Wind Turbine Generators DC/DC
GB AC/DC
. = .
. HVDC
= transimission
GB AC/DC
(c)
Figure 1. High voltage direct current (HVDC) configurations for wind power transmission: (a) DC- Figure 1. High voltage direct current (HVDC) configurations for wind power transmission: (baseda) DC-based connection connection with two with-stage two-stage hybrid hybridconversion; conversion; (b) DC- (basedb) DC-based connection connection with two with-stage two-stage DC/DC DC/DCconversion; conversion; (c) DC-based (c) DC-based connection connection with the withproposed the proposed modular modular converter. converter.
To address the challenges, DC converters with high voltage gains [14–17], modular multilevel To address the challenges, DC converters with high voltage gains [14–17], modular multilevel converters (MMCs) [18–22] and multi-module converters [23–25] are studied extensively. Although converters (MMCs) [18–22] and multi-module converters [23–25] are studied extensively. dual-active bridge (DAB) converters [14,15] and resonant converters [16,17] can obtain high voltage Although dual-active bridge (DAB) converters [14,15] and resonant converters [16,17] can obtain step-up ratios, the voltage stress on their semiconductor components is high, which can be reduced high voltage step-up ratios, the voltage stress on their semiconductor components is high, which can by applying MMCs. By adding sub-modules (SMs), a high output voltage is achieved without be reduced by applying MMCs. By adding sub-modules (SMs), a high output voltage is achieved increasing the voltage stress. However, the MMC topologies based on half-bridge (HB) or full-bridge without increasing the voltage stress. However, the MMC topologies based on half-bridge (HB) or (FB) [18,19] and resonant MMC [20] cannot provide electrical isolation. The isolated MMCs in full-bridge (FB) [18,19] and resonant MMC [20] cannot provide electrical isolation. The isolated MMCs References [21,22] are presented with DC/AC/DC configuration, where medium-frequency high in References [21,22] are presented with DC/AC/DC configuration, where medium-frequency high turns-ratio transformers are employed, resulting in a vast volume. Although resonant MMCs [26] Sustainability 2018, 10, x FOR PEER REVIEW 3 of 15 turns-ratio transformers are employed, resulting in a vast volume. Although resonant MMCs [26] achieveSustainability galvanic2018 isolation, 10, 2176 and a small volume of transformers at the same time, its conversion3 of 15 ratio only satisfies MV applications. Alternatively, transformers can be decentralized into multi-module converters, enabling the installation of high-frequency transformers, which reduces the sizes of transformersachieve galvanic and reactive isolation components. and a smallvolume However, of transformers by adopting at the active same-clamping time, its conversion flyback– ratioforward only satisfies MV applications. Alternatively, transformers can be decentralized into multi-module converters as SMs, the currents of different SMs are unbalanced because of the non-ideal factors such converters, enabling the installation of high-frequency transformers, which reduces the sizes of as unequable leakage inductances of transformers, and only half of the power switches can achieve transformers and reactive components. However, by adopting active-clamping flyback–forward zero voltageconverters switching as SMs, the (ZVS), currents resulting of different in high SMs switching are unbalanced losses because [23]. of the non-ideal factors such Inas this unequable paper, leakage based on inductances the multi of-modular transformers, converter and only in Reference half of the [23], power active switches-clamping can achieve current- fed pushzero– voltagepull (CFPP) switching converters (ZVS), resulting are adopted in high to switching replace lossesthe flyback [23]. –forward SMs. The currents of modules inIn thisseries paper,-connection based on are the multi-modularauto-balanced, converter and all in power Reference switches [23], active-clamping can achieve soft current-fed-switching. Therefore,push–pull control (CFPP) complexity converters and are adoptedswitching to replaceloss are the reduced. flyback–forward Furthermore, SMs. The the currents matrix ofconfiguration modules bringsin about series-connection high control are auto-balanced, flexibility, which and all improves power switches the fault can tolerance achieve soft-switching. capability. Additionally, Therefore, thankscontrol to the complexity independent and switching operation loss of areeach reduced. port, the Furthermore, converter thecan matrix collect configuration power from brings multiple sourcesabout without high control bus cable. flexibility, which improves the fault tolerance capability. Additionally, thanks to the independent operation of each port, the converter can collect power from multiple sources without The paper is organized as follows: The basic cell and two interleaved working modes are bus cable. analyzed in Section 1; the scalable topology design is discussed in Section 3; Section 4 depicts the fault The paper is organized as follows: The basic cell and two interleaved working modes are analyzed tolerancein Section strategies1; the scalableof the topology topology; design simulation is discussed results in are Section presented3; Section in4 depictsSection the 5 to fault demonstrate tolerance the effectivenestrategiesss and of the efficiency topology; of simulation the converter results, and are presented finally, concl in Sectionusions5 to are demonstrate drawn in the Secti effectivenesson 4. and efficiency of the converter, and finally, conclusions are drawn in Section4. 2. Analysis of the Basic Cell and Working Strategies of Matrix Configuration 2. Analysis of the Basic Cell and Working Strategies of Matrix Configuration 2.1. Operation of the Basic Cell 2.1. Operation of the Basic Cell The The basic basic cell cell topology topology based on on CFPP CFPP converter converter shown shown in Figure in2 hasFigure similar 2 operationhas similar principles operation principles and characteristics as the converter presented in Reference [27]. S1–S2 are the two main and characteristics as the converter presented in Reference [27]. S1–S2 are the two main switches. switches.Sc1–S cS2c1are–Sc2 the are two the active two clamping active clamping switches. switches.Cc is the clampCc is the capacitor. clampL capacitor.1 is the input L1 transistor.is the input transistor.The tri-winding The tri-windin transformerg transformer has a turns has ratio a turns of N pratio1:Np2 :ofN sN=p1 1:1::Npn2:andNs = leakage1:1:n and inductance leakage Linductancek at the Lk at secondarythe secondary side. Furthermore,side. Furthermore, the secondary the secondary circuit consists circuit of fourconsists rectifier of four diodes rectifierD1–D4, diodes one output D1–D4, one outputcapacitor capacitorCout and C aout load and resistor a loadR resistor. R.
L1
Np1 Np2
D1 D3 Vin Sc1 Sc2 Ns Lk is + vs - C Cc out R S 1 S2 D2 D4
FigureFigure 2. Topology 2. Topology of the of thebasic basic cell cell based based on on active active-clamping-clamping fedfed push–pull push–pull (CFPP) (CFPP converter.) converter.
The key operating waveforms of CFPP cell are depicted in Figure 3. Vgs1–Vgs2 are the control The key operating waveforms of CFPP cell are depicted in Figure3. Vgs1–Vgs2 are the control 1 2 ◦ gsc1 gsc2 signalssignals for the for two the twomain main switches switches S –SS1–,S which2, which have have the the phase phase shift shift angle ofof 180180°.. V Vgsc1––VVgsc2 are the controlthe signals control signals for the for two the clamp two clamp switches switches Sc1S-Sc1c-2S. cThe2. The control control signals signals of of thethe main main switches switches and and clampingclamping switches switches are are complementary. complementary. vvdsds11––vvdsds2 2andand vdsc11––vvdscdsc2 2areare the the drain-to-sourcedrain-to-source voltages voltages of the of the main mainswitches switches and andclamping clamping switches switches resp respectively.ectively. iL1iL is1 isthe the current current of of input input inductor inductor LL11.. vss and iiss are the secondaryare the secondary voltage voltage and current and current of the of thetransformer transformer respectively. respectively. The followingfollowing assumptions assumptions are are mademade to simplify to simplify the theanalysis. analysis. Sustainability 2018, 10, 2176 4 of 15 Sustainability 2018, 10, x FOR PEER REVIEW 4 of 15
Vgs1 Vgsc1 t
Vgsc2 Vgs2 t
vdsc1 vds1 t
vds2 vdsc2 t v s t
i s t
iL1 t t t t t t t t t t t t 0 1 2 3 4 5 6 7 8 9 10
FigureFigure 3.3. Operating waveformswaveforms ofof thethe basicbasic cell.cell.
• All switches and diodes are identical. • All switches and diodes are identical. • The capacitance of clamp capacitor is large enough so that its voltage ripple can be ignored. Due • The capacitance of clamp capacitor is large enough so that its voltage ripple can be ignored. to the symmetrical operation, a brief introduction of the operation during t0–t5 when D ≤ 0.5 is ≤ Duepresented to the symmetricalin this part. operation, a brief introduction of the operation during t0–t5 when D 0.5 is presented in this part. Mode 1 (t0–t1): In this mode, the main switch S1 and the clamping switch Sc2 are on. The power is transferredMode 1 (t 0to– tthe1): Inoutput. this mode, The diodes the main D2 switchand D3S are1 and forward the clamping biased, switchand theSc secondary2 are on. The current power is isdecreases transferred. to the output. The diodes D2 and D3 are forward biased, and the secondary current is decreases.Mode 2 (t1–t2): At t1, the main switch S1 is turned off. The leakage inductances Lk resonate with the parasiticMode 2 capacitances (t1–t2): At t1, ofthe S1 main and S switchc1. Then,S1 theis turned voltage off. of S TheC1 drops leakage to zero inductances at t2 to achieveLk resonate ZVS turn with- theon. parasiticAt the same capacitances time, capacitance of S1 and CSS1 cis1. charged. Then, the voltage of SC1 drops to zero at t2 to achieve ZVS turn-on.Mode At 3 the (t2 same–t3): At time, t2, the capacitance clamping C switchS1 is charged. SC1 is turned on with zero voltage. Because both the clampingMode switches 3 (t2–t3): SC At1 andt2, theSC2 are clamping on, the switchprimarySC sides1 is turned of the transformer on with zero are voltage. short-circuit Becauseed. Then both thethe clampingpower is transferred switches S Cto1 andthe inputSC2 are inductor on, the L primary1, and the sides secondary of the current transformer is rises are rapidly short-circuited.. ThenMode the power 4 (t3– ist4 transferred): At t3, the to secondary the input current inductor reachesL1, and zero. the secondary All four diodescurrent areis rises reverse rapidly. biased. Additionally,Mode 4 ( tthe3–t 4secondary): At t3, the voltage secondary recovers current to zero reaches within zero. a short All time. four diodes are reverse biased. Additionally,Mode 5 ( thet4–t secondary5): At t4, the voltage clamping recovers switch to S zeroC2 is withinturned aoff. short The time. leakage inductances Lk resonate withMode parasitic 5 (t 4capacitances–t5): At t4, the of clampingS2 and SC2 switch. The voltageSC2 is turnedacross S off.2 drops The leakageto zero at inductances t5 so that ZVSLk resonate turn-on withof S2 parasiticis obtained. capacitances of S2 and SC2. The voltage across S2 drops to zero at t5 so that ZVS turn-on of S2 Theis obtained. operation in intervals (t0–t5) and (t5–t10) is symmetrical. The power is transferred to the outputThe load operation R when inone intervals main switch (t0–t5 and) and one (t5 clamping–t10) is symmetrical. switch are on, The and power then the is transferredpower flows to from the outputthe input load to Rinductorwhen oneL1 when main both switch clamping and one switches clamping are switch on. All are switches on, and can then obtain the powerZVS turn flows-on fromand the the energ inputy tostored inductor in LkL 1iswhen recycled both by clamping the parasitic switches capacitances are on. Allof clamping switches switches, can obtain which ZVS turn-oncontributes and to the a higher energy conversion stored in L efficiency.k is recycled by the parasitic capacitances of clamping switches, whichThe contributes voltage of to clamp a higher capacitor conversion VCc can efficiency. be obtained according to the flux balance of L1: The voltage of clamp capacitor VCc can be obtained according to the flux balance of L1: Vin VCc = (1) 1V− D V = in (1) Cc 1 − D Additionally, with the turns ratio as 1:1:n, the output voltage of basic cell Vo,BC can be determined:
Additionally, with the turns ratio as 1:1:n, the output voltage of basic cell Vo,BC can be determined: nnVin VVo, BC ==Cc (2) n 2 2n (1−VD ) V = V = in (2) o,BC 2 Cc 2 (1 − D) The voltage stress of all four power switches Vds can be obtained by: V VV==in (3) ds Cc 1− D Sustainability 2018, 10, 2176 5 of 15
The voltage stress of all four power switches Vds can be obtained by: Sustainability 2018, 10, x FOR PEER REVIEW 5 of 15 V V = V = in (3) ds Cc 1 − D 2.2. Working Strategies of Matrix Configuration 2.2. Working Strategies of Matrix Configuration A fundamental 2 × 2 modular topology is presented in Figure 4. The primary circuits of power A fundamental 2 × 2 modular topology is presented in Figure4. The primary circuits of power cells are parallel connected so that they have an equal secondary voltage value with the same duty cells are parallel connected so that they have an equal secondary voltage value with the same duty cycle of maincycle switches. of main switches. The secondary The secondary side side of of each each cell is is connected connected with with four rectifierfour rectifi diodeser for diodes for power regulation.power regulation.
P_Cell_11
L1
D00 D01 D02 S_Cell_11
Np1 Np2 Ns
P P
P S_Cell_12
_ _
Vin _
Cell Cell Cell
D10 D11 D12
_ _
Sc1 Sc2 _
22 12 21 Cout S_Cell_21 S_Cell_22 R
D20 D21 D22 Cc S1 S2
Figure 4.Figure 2 × 2 topology 4. 2 × 2 topology of the of isolated the isolated high high voltage voltage gain gain DC/DC DC/DC converter converter with basic with cells. basic cells.
As illustratedAs illustrated in Figure in Figure 5a,b,5 adjacenta,b, adjacent cells cells have have oppositeopposite polarities polarities in column in column interleaved interleaved modes. modes. For example,For example,the polarity the polarity of cell of 11 cell is 11 opposite is opposite to to those those of of cell cell 21 21 and and 12. In12. this In case, this cells case, in thecells same in the same column are connected in series, and the adjacent columns are in parallel connection. The voltage column are connected in series, and the adjacent columns are in parallel connection. The voltage ratings of diodes in the first and last rows, D00–D02 and D20–D22, are equal to the voltage of power 00 02 20 22 ratings of diodescells vs. Whilein the the first voltage and ratingslast rows, of other D diodes–D andD10– DD12–haveD , twiceare equal the value to the of v svoltagesince they of are power cells vs. While theconnected voltage with ratings two cells. of other The current diodes stresses D10–D of12diodes have twice in the firstthe andvalue last of columns, vs sinceD 00they–D20 areand connected D –D have the same value as the secondary current of one column. Diodes D –D connect with with two cells.02 The22 current stresses of diodes in the first and last columns, 01D00–21D20 and D02–D22 have two columns so that they have double the current stress of the others. Additionally, the sum of the 01 21 the same valueaverage as diode the secondary currents in all current columns of is equalone column. to the output Diodes current. D Therefore,–D connect in column with interleaved two columns so that they havemodes, double the voltage the andcurrent current stress ratings of of the diodes others. in an Additionally, expanded topology the as sum shown of inthe Figure average6 diode currents incomposed all columns of s rows is equal and p columns to the canoutput be obtained: current. Therefore, in column interleaved modes, the voltage and current ratings of diodes in an expanded topology as shown in Figure 6 composed of s 1 = = n = s Vo,s×p Vo,BC 2(1−D) Vin i 0, s rows and p columns canV be(D obtained:) = (4) ij 2 = × = n = ··· ( − ) s Vo,s×p 2 Vo,BC (1−D) Vin i 1, 2, , s 1 1 n Vo,, s( p=1 V o BC =1 V in i = 0, s 2 Io,BC = 2p Io,s×p j = 0, p I(DsD) = 2(1− ) (5) VD()= ij 1 ij Io,BC = Io,s×p j = 1, 2, ···, (p − 1) (4) 2 p n Vo,, s p=2 Vp o BC = V in i = 1,2, ,( s − 1) sD(1− ) ∑ I(Dij) = Io,sp (6) j=0
where Io,BC is the average output11 current of a single basic cell; Vo,s×p and Io,s×p are the output voltage × Io,, BC== I o s p j 0, p and current of s p topology.22 In this case,p all semiconductor components have low voltage and current ratings. ID()ij = (5) 1 Io,, BC= I o s p j= 1,2, ,( p − 1) p
p IDI()ij= o, sp (6) j=0 where Io,BC is the average output current of a single basic cell; Vo,s×p and Io,s×p are the output voltage and current of s × p topology. In this case, all semiconductor components have low voltage and current ratings.
D00 D01 D02 D00 D01 D02 - + + - + - - + S_Cell_11 S_Cell_12 S_Cell_11 S_Cell_12
D10 D11 D12 D10 D11 D12
+ - - + Cout - + + - Cout S_Cell_21 S_Cell_22 R S_Cell_21 S_Cell_22 R
D20 D21 D22 D20 D21 D22
(a) (b) Sustainability 2018, 10, x FOR PEER REVIEW 5 of 15
2.2. Working Strategies of Matrix Configuration A fundamental 2 × 2 modular topology is presented in Figure 4. The primary circuits of power cells are parallel connected so that they have an equal secondary voltage value with the same duty cycle of main switches. The secondary side of each cell is connected with four rectifier diodes for power regulation.
P_Cell_11
L1
D00 D01 D02 S_Cell_11
Np1 Np2 Ns
P P
P S_Cell_12
_ _
Vin _
Cell Cell Cell
D10 D11 D12
_ _
Sc1 Sc2 _
22 12 21 Cout S_Cell_21 S_Cell_22 R
D20 D21 D22 Cc S1 S2
Figure 4. 2 × 2 topology of the isolated high voltage gain DC/DC converter with basic cells.
As illustrated in Figure 5a,b, adjacent cells have opposite polarities in column interleaved modes. For example, the polarity of cell 11 is opposite to those of cell 21 and 12. In this case, cells in the same column are connected in series, and the adjacent columns are in parallel connection. The voltage ratings of diodes in the first and last rows, D00–D02 and D20–D22, are equal to the voltage of power cells vs. While the voltage ratings of other diodes D10–D12 have twice the value of vs since they are connected with two cells. The current stresses of diodes in the first and last columns, D00–D20 and D02–D22 have the same value as the secondary current of one column. Diodes D01–D21 connect with two columns so that they have double the current stress of the others. Additionally, the sum of the average diode currents in all columns is equal to the output current. Therefore, in column interleaved modes, the voltage and current ratings of diodes in an expanded topology as shown in Figure 6 composed of s rows and p columns can be obtained: 1 n Vo,, s p= V o BC = V in i = 0, s sD2(1− ) VD()ij = (4) 2 n Vo,, s p=2 V o BC = V in i = 1,2, ,( s − 1) sD(1− )
11 Io,, BC== I o s p j 0, p 22p ID()ij = (5) 1 Io,, BC= I o s p j= 1,2, ,( p − 1) p
p IDI()ij= o, sp (6) j=0 wSustainabilityhere Io,BC is2018 the, 10 average, 2176 output current of a single basic cell; Vo,s×p and Io,s×p are the output voltage6 and of 15 current of s × p topology. In this case, all semiconductor components have low voltage and current ratings.
D00 D01 D02 D00 D01 D02 - + + - + - - + S_Cell_11 S_Cell_12 S_Cell_11 S_Cell_12
D10 D11 D12 D10 D11 D12
+ - - + Cout - + + - Cout S_Cell_21 S_Cell_22 R S_Cell_21 S_Cell_22 R
D20 D21 D22 D20 D21 D22
Sustainability 2018, 10, x FOR PEER REVIEW 6 of 15 Sustainability 2018, 10, x FOR PEER (REVIEWa) (b) 6 of 15
D00 D01 D02 D00 D01 D02 D D D D D D 00 - + 01 - + 02 00 + - 01 + - 02 S_Cell- _ 1 1+ S_Cell- _ 12 + S_Cell+ _ 1 1 - S_Cell+ _ 12 - S_Cell_11 S_Cell_12 S_Cell_11 S_Cell_12 D10 D11 D12 D10 D11 D12 D10 D11 D12 D10 D11 D12 + - + - Cout - + - + Cout S_Cell+ _ 21 - S_Cell+ _ 2 2- CoutR S_Cell- _ 21 + S_Cell- _ 2 2+ CoutR S_Cell_21 S_Cell_22 R S_Cell_21 S_Cell_22 R D20 D21 D22 D20 D21 D22 D20 D21 D22 D20 D21 D22 (c) (d) (c) (d) Figure 5. 2 × ×2 topology with different interleaved strategies: (a) Column interleaved mode 1; (b) FigureFigure 5.5. 2 × 22 topolog topologyy with with different different interleaved interleaved strategies: strategies: (a)( aColumn) Column interleaved interleaved mode mode 1; ( 1;b) Column interleaved mode 2; (c) Series interleaved mode 1; (d) Series interleaved mode 2. (bColumn) Column interleaved interleaved mode mode 2; ( 2;c) (Seriesc) Series interleaved interleaved mode mode 1; ( 1;d) ( dSeries) Series interleaved interleaved mode mode 2. 2.
WTG 1
WTG 1
P P P P P P
P P P
______
_ _ _
C C C C C C
C C C
P P P P P P
P P P
ell ell ell ell ell ell
ell ell ell
______
_ _ _
C C C C C C
1 1 1 1 1 1
C C C
1 1
·· ·· ·· 1 ··
------
- - -
11 22 2 1 1 2
s s sp
ell ell ell ell ell ell
ell ell ell
1 2
p 2 p 1
1 1 1 1 1 1
1 1
·· ·· ·· 1 ··
------
- - -
11 22 2 1 1 2
s s sp
1 2
p p 1 WTG 2 2
WTG 2
P P P P P P
P P P
______
_ _ _
C C C C C C
C C C
P P P P P P
P P P
ell ell ell ell ell ell
ell ell ell
______
_ _ _
C C C C C C
2 2 2 2 2 2
C C C
2 2
·· ·· ·· 2 ··
------
- - -
11 22 2 1 1 2
s s sp
ell ell ell ell ell ell
ell ell ell
1 2
p 2 p 1
2 2 2 2 2 2
2 2
·· ·· ·· 2 ··
------
- - -
11 22 2 1 1 2
s s sp
1 2
p p 1 WTG 3 2
WTG 3
P P P P P P
P P P
______
_ _ _
C C C C C C
C C C
P P P P P P
P P P
ell ell ell ell ell ell
ell ell ell
______
_ _ _
C C C C C C
3 3 3 3 3 3
C C C
3 3
·· ·· ·· 3 ··
------
- - -
11 22 2 1 1 2
s s sp
ell ell ell ell ell ell
ell ell ell
1 2
p 2 p 1
3 3 3 3 3 3
3 3
·· ·· ·· 3 ··
------
- - -
11 22 2 1 1 2
s s sp
1 2
p 2 p 1
(a) (a)
Group 1 Group 2 Group 3
D1-00 D1-01 GroupD1-02 1 D1-0p D2-00 D2-01 GroupD2-02 2 D2-0p D3-00 D3-01 GroupD3-02 3 D3-0p Iout
D1-00 D1-01 D1-02 D1-0p D2-00 D2-01 D2-02 D2-0p D3-00 D3-01 D3-02 D3-0p Iout S_Cell1-11 S_Cell1-12 S_Cell1-1p S_Cell2-11 S_Cell2-12 S_Cell2-1p S_Cell3-11 S_Cell3-12 S_Cell3-1p
D1-10S_CellD11-11-11 S_CellD11-12-12 S_CellD11-1-1pp D2-10S_CellD22-11-11 S_CellD22-12-12 S_CellD22-1-1pp D3-10S_CellD33-11-11 S_CellD33-12-12 S_CellD33-1-1pp
D1-10 D1-11 D1-12 D1-1p D2-10 D2-11 D2-12 D2-1p D3-10 D3-11 D3-12 D3-1p S_Cell1-21 S_Cell1-22 S_Cell1-2p S_Cell2-21 S_Cell2-22 S_Cell2-2p S_Cell3-21 S_Cell3-22 S_Cell3-2p
D1-20S_CellD11-21-21 S_CellD11-22-22 S_CellD11-2-2pp D2-20S_CellD22-21-21 S_CellD22-22-22 S_CellD22-2-2pp D3-20S_CellD33-21-21 S_CellD33-22-22 S_CellD33-2-2pp Vout D1-20 D1-21 D1-22 D1-2p D2-20 D2-21 D2-22 D2-2p D3-20 D3-21 D3-22 D3-2p Cout Vout Cout
S_Cell1-s1 S_Cell1-s2 S_Cell1-sp S_Cell2-s1 S_Cell2-s2 S_Cell2-sp S_Cell3-s1 S_Cell3-s2 S_Cell3-sp
D1-s0S_CellD11-s-1s1 S_CellD11-s-2s2 S_CellD11-sp-sp D2-s0S_CellD22-s-1s1 S_CellD22-s-2s2 S_CellD22-sp-sp D3-s0S_CellD33-s-1s1 S_CellD33-s-2s2 S_CellD33-sp-sp D1-s0 D1-s1 D1-s2 D1-sp D2-s0 D2-s1 D2-s2 D2-sp D3-s0 D3-s1 D3-s2 D3-sp (b) (b) Figure 6. Topology of the proposed converter with three input-ports: (a) primary circuits with three Figure 6. Topology of the proposed converter with three input-ports: (a) primary circuits with three powerFigure sources; 6. Topology (b) secondary of the proposed circuits converter collecting with power three and input-ports: delivering it (a to) primary load. circuits with three power sources; (b) secondary circuits collecting power and delivering it to load. power sources; (b) secondary circuits collecting power and delivering it to load. From Figure 5c,d, in series interleaved modes, all cells are series-connected. The cells in adjacent From Figure 5c,d, in series interleaved modes, all cells are series-connected. The cells in adjacent rows have the opposite polarities while the cells in the same row have the same polarity. Similar to rows have the opposite polarities while the cells in the same row have the same polarity. Similar to Equation (4), diodes D10 and D12 have twice the voltage rating higher than that of diodes in the first Equation (4), diodes D10 and D12 have twice the voltage rating higher than that of diodes in the first and last rows because they connect with two rows. The currents of all operating diodes have the same and last rows because they connect with two rows. The currents of all operating diodes have the same value since they are in series-connection. Hence, the voltage and current ratings of diodes in series value since they are in series-connection. Hence, the voltage and current ratings of diodes in series interleaved modes can be calculated as: interleaved modes can be calculated as: 1 pn 1Vo,, s p= p V o BC =pn V in i = 0, s sDVo,, s p= p V o BC =2(1− ) V in i = 0, s VD()ij = sD2(1− ) (7) VD()= 2 pn ij V=2 p V = V i = 1,2, ,( s − 1) (7) 2 o,, s p o BCpn in sDVo,, s p=2 p V o BC =(1− ) V in i = 1,2, ,( s − 1) sD(1− ) Sustainability 2018, 10, 2176 7 of 15
From Figure5c,d, in series interleaved modes, all cells are series-connected. The cells in adjacent rows have the opposite polarities while the cells in the same row have the same polarity. Similar to Equation (4), diodes D10 and D12 have twice the voltage rating higher than that of diodes in the first and last rows because they connect with two rows. The currents of all operating diodes have the same value since they are in series-connection. Hence, the voltage and current ratings of diodes in series interleaved modes can be calculated as: 1 = × = p×n = s Vo,s×p p Vo,BC 2(1−D) Vin i 0, s V(Dij) = (7) 2 = × = p×n = ··· ( − ) s Vo,s×p 2p Vo,BC (1−D) Vin i 1, 2, , s 1
1 1 I(D ) = I = I × j = 0, p (8) ij 2 o,BC 2 o,s p According to Equation (8), for series interleaved modes, the current rating of diodes is increased with the increase of output power. Besides which, the diodes D01–D21 are blocked, which benefits the fault tolerance operation to be described in Section4.
3. Analysis of the Proposed Converter with Multi-Input Ports
3.1. Scalable Topology Thanks to modularity, multi-module converters can be easily expanded by increasing its row number and column number to attain a high voltage gain and the desired high power level. In the normal scenario, the proposed converter operates with column interleaved modes to keep a low voltage/current rating of components. Three wind-turbine-generators, WTGs 1–3, are connected to the proposed converter as illustrated in Figure6a. Figure6b shows the secondary circuits that are divided into three independent, Groups 1–3, by diodes D1-0p–D1-sp, D2-00–D1-s0 and D2-0p–D2-sp, D3-00–D3-s0 on the basis of input ports. The output power of each group consisting of the s × p expanded topology can be controlled individually, and the bus cable is eliminated. With the same input voltage and power of each port, the voltages and currents of all basic cells are identical. The cells in the same column are in series-connection. Hence, every column has the same terminal voltage which is the sum of the voltages of cells in the same column. For a converter with multi-ports, output voltage Vout equals to the identical terminal voltage of columns and the output current Iout is the sum of secondary currents of all columns. Therefore, the row number s determines the output voltage, and the group number x with column number p determines the output power.
( s×n Vout = Vo,s×p = s × Vo,BC = ( − ) Vin 2 1 D (9) Iout = x × Io,s×p = x × p × Io,BC
3.2. Current Balance with Column Interleaved Mode The control complexity is reduced by the auto-balanced currents of cells in the same column. According to the currents through diodes D10–D13 and D20–D23, as shown in Figure7, the relationships among all cells can be obtained as:
+ = + Io,BC11+ Io,BC12+ Io,BC21+ Io,BC22+ I + = I + o,BC31 o,BC21 (10) I = I o,BC23+ o,BC13+ Io,BC32+ + Io,BC33+ = Io,BC22+ + Io,BC23+ Sustainability 2018, 10, 2176 8 of 15
= Io,BC11− Io,BC21− I − + I − = I − + I − o,BC31 o,BC32 o,BC21 o,BC22 (11) I + I = I + I o,BC12− o,BC13− o,BC22− o,BC23− Io,BC33− = Io,BC23− where Io,BC+ is the average current of secondary circuit in the interval (t0–t5) and Io,BC− is that in the interval (t5–t10). According to the symmetrical operation of the basic cell between the two intervals, it can be derived that Io,BC+ = Io,BC−. Therefore, Equation (12) is obtained with Io,BC = Io,BC+ + Io,BC−. I = I = I o,BC11 o,BC21 o,BC31 I = I = I (12) Sustainability 2018, 10, x FOR PEER REVIEW o,BC12 o,BC22 o,BC32 8 of 15 Sustainability 2018, 10, x FOR PEER REVIEW 8 of 15 Io,BC13 = Io,BC23 = Io,BC33 According to Equation (12), the average currents for cells in the same column are auto-balanced. AccordingAccording to EquationEquation (12), the average currents for cells in the the same same column column are are auto auto-balanced.-balanced. Therefore, as shown in Figure 8, only the control of output voltage and current sharing in different Therefore, as shown in Figure8 8,, onlyonly thethe controlcontrol ofof output output voltagevoltage andand currentcurrent sharingsharing inin differentdifferent columns is employed to achieve the required output voltage and power in the s × p topology, where columns is is employed employed to to achieve achieve the the required required output output voltage voltage and andpower power in the in s the× p tops ×ology,p topology, where vo,ref is the desired output voltage and iL,i1–iL,ip are the currents collected from columns 1–p. wherevo,ref is thevo,ref desiredis the desiredoutput outputvoltage voltageand iL,i1 and–iL,ip iareL,i1 –theiL,ip currentsare the currentscollected collected from columns from columns1–p. 1–p.
D00 D01 D02 D03 D00 D01 D02 D03 D00 D01 D02 D03 D00 D01 D02 D03 + - - + + - - + + - - + + - - + + - - + + - - + S_Cell11 S_Cell12 S_Cell13 S_Cell11 S_Cell12 S_Cell13 S_Cell11 S_Cell12 S_Cell13 S_Cell11 S_Cell12 S_Cell13 D10 D11 D12 D13 D10 D11 D12 D13 D D D D D D D D 10 - + 11 + - 12 - + 13 10 + - 11 - + 12 + - 13 - + + - - + + - - + + - S_Cell21 S_Cell22 S_Cell23 Vout S_Cell21 S_Cell22 S_Cell23 Vout S_Cell21 S_Cell22 S_Cell23 Cout Vout S_Cell21 S_Cell22 S_Cell23 Cout Vout D20 D21 D22 D23 Cout D20 D21 D22 D23 Cout D20 D21 D22 D23 D20 D21 D22 D23 + - - + + - - + + - - + + - - + + - - + + - - + S_Cell31 S_Cell32 S_Cell33 S_Cell31 S_Cell32 S_Cell33 S_Cell31 S_Cell32 S_Cell33 S_Cell31 S_Cell32 S_Cell33 D30 D31 D32 D33 D30 D31 D32 D33 D D D D D D D D 30 31 32 33 30 31 32 33 (a) (b) (a) (b) Figure 7. Auto-balanced currents of cells in the same column with column interleaved working Figure 7. 7. Auto-balancedAuto-balanced currents currents of cellsof cells in the in same the same column column with column with column interleaved interleaved working working strategy: strategy: (a) Column interleaved working mode 1; (b) Column interleaved working mode 2. (strategy:a) Column (a) interleavedColumn interleaved working modeworking 1; ( bmode) Column 1; (b) interleaved Column interleaved working modeworking 2. mode 2.
Column Column + + PI 1 s PI 1 - sI - IL,i1 i=1 L,i1 i=1 + + Vo,ref + PI + PI 2 Vo,ref PI s PI 2 - - sI - IL,i2 - i=1 L,i2 Vout i=1 Vout + + PI p s PI p - sI - IL,ip i=1 L,ip
i=1 Figure 8. Control scheme of the s × p topology. FigureFigure 8.8. Control schemescheme ofof thethe ss ×× pp topotopology.logy. 4. Fault Tolerance 4. Fault Tolerance 4.1. Fault Tolerance for WTGs with Different Output Power 4.1. Fault Tolerance forfor WTGsWTGs withwith DifferentDifferent OutputOutput PowerPower When disturbances occur, proper control strategies of WTGs and converters should be applied When disturbances occur,occur, properproper control control strategies strategies of of WTGs WTGs and and converters converters should should be be applied applied to to ensure system protection and high power efficiency [28,29]. For the proposed converter, the output ensureto ensure system system protection protection and and high high power power efficiency efficiency [ 28[28,,2929].]. For For the the proposedproposed converter,converter, thethe output power of one group is determined not only by the column number of the secondary circuits but also, power of one groupgroup is determined not only by the column number of the secondary circuits bu butt also also,, by the duty-cycles of main switches. According to Equation (8), the output power of one group is by the duty-cycles of main switches. According to Equation (8), the output power of one group is obtained as: obtained as: Pgroup=() p − m V out I o, BC (13) Pgroup=() p − m V out I o, BC (13) where m is the number of idle column in the corresponding group. where m is the number of idle column in the corresponding group. The variation of a duty-cycle will cause the change of currents through the cells in one column The variation of a duty-cycle will cause the change of currents through the cells in one column as: as:
ton 2 t Isub= I o, BC =2 on i out i max D (14) Isub= I o, BC =T 0 i out i max D (14) s 0 Ts Hence the output power is: Hence the output power is: Pgroup= p V out I sub = p D V out imax (15) Pgroup= p V out I sub = p D V out imax (15) where imax is the maximum output current of power cells. where imax is the maximum output current of power cells. Sustainability 2018, 10, 2176 9 of 15 by the duty-cycles of main switches. According to Equation (8), the output power of one group is obtained as: Pgroup = (p − m) × Vout × Io,BC (13) where m is the number of idle column in the corresponding group. The variation of a duty-cycle will cause the change of currents through the cells in one column as:
2 Z ton Isub = Io,BC = · iout ≈ imax · D (14) Ts 0
Hence the output power is:
Pgroup = p · Vout · Isub = p · D · Vout · imax (15) where imax is the maximum output current of power cells.
4.2. Fault Tolerance for Semiconductor Components
SustainabilitySemiconductor 2018, 10, x FOR components PEER REVIEW are vulnerable components in a converter [30]. For offshore HVDC9 of 15 stations, faulty components take a long time for maintenance, resulting in high cost and loss [31]. 4.2. FaultFigure Tolerance9 shows for the Semiconductor fault tolerance Components operation derived by installing redundant power cells. To maintain normal operation, the column in a red dotted box containing the damaged Cell 11 Semiconductor components are vulnerable components in a converter [30]. For offshore HVDC is replaced by one redundant column that is in the other red dotted box. For the faulty diodes D –D , stations, faulty components take a long time for maintenance, resulting in high cost and loss [31]00 . s0 they require only one redundant column since they connect with one column. However, for other Figure 9 shows the fault tolerance operation derived by installing redundant power cells. To diodes, two redundant columns are demanded. For example, when diode D fails, the columns 1–2 in maintain normal operation, the column in a red dotted box containing11 the damaged Cell 11 is the blue dotted box are idle, and the redundant columns p1–p2 are applied. replaced by one redundant column that is in the other red dotted box. For the faulty diodes D00–Ds0, they require only one redundant column since they connect with one column. However, for other Vo,s×p 1 V = = V (16) diodes, two redundant columns are demanded.o,FBC 2 For× s example,2 o,BC when diode D11 fails, the columns 1–2 in the blue dotted box are idle, and the redundant columns p1–p2 are applied.
Failed cell Failed diode
D00 D01 D02 D03 D0p D0p1 D0p2 Cell_11 Cell_12 Cell_13 Cell_1p1 Cell_1p2
D10 D11 D12 D13 D1p D1p1 D1p2 Cell_21 Cell_22 Cell_23 Cell_2p1 Cell_2p2
D20 D21 D22 D23 D2p D2p1 D2p2 Cell_31 Cell_32 Cell_33 Cell_3p1 Cell_3p2
D30 D31 D32 D33 D3p D3p1 D3p2
Vout Cout
Cell_s1 Cell_s2 Cell_s3 Cell_sp1 Cell_sp2
Ds0 Ds1 Ds2 Ds3 Dsp Dsp1 Dsp2
Idle Cells Redundant Cells Figure 9. FaultFault tolerance tolerance with with redundancy redundancy..
The proposed topology can also obtain faultVo, s tolerant p 1 operation of diodes and power switches VVo,, FBC== o BC (16) without redundancy. In Figure 10a,b, when diode22 s D11 is short-circuited, the cells in rows 1–2 are inactive to block the faulty components, while the fault tolerance group still operates with the column interleavedThe proposed strategy. topology Additionally, can also to obtain maintain fault normal tolerant operation, operation the of output diodes voltages and power of the switches faulty withoutgroup are redundancy. controlled according In Figure to 10 Equationsa,b, when (2) diode and (9) D11 to is ensure short the-circuited, output voltagethe cells is in the rows same 1 as–2 thatare inactive to block the faulty components, while the fault tolerance group still operates with the column in the normal case. When diode D11 is open-circuited as illustrated in Figure 10c,d, the fault tolerant interleaved strategy. Additionally, to maintain normal operation, the output voltages of the faulty operation group consisting of two columns works under the series interleaved modes to block D11. groupCompared are controlled with the normalaccording operation to Equation group,s (2) the and number (9) to ofensure cells the inseries output connection voltage is inthe the same faulty as that in the normal case. When diode D11 is open-circuited as illustrated in Figure 10c,d, the fault tolerant operation group consisting of two columns works under the series interleaved modes to block D11. Compared with the normal operation group, the number of cells in series connection in the faulty group is doubled. The voltages of cells in the fault group are adjusted as illustrated in Equation (15) to ensure they have the same terminal voltage. Moreover, the fault tolerant operation of damaged cells without redundancy is similar to that when diodes are short-circuited. For instance, when cell 11 fails, cells 11-1p and 21-2p are idle so that the faulty one is blocked.
D00 D01 D02 D0p D00 D01 D02 D0p Cell_11 Cell_12 Cell_1p Cell_11 Cell_12 Cell_1p
D10 D11 D12 D1p D10 D11 D12 D1p Cell_21 Cell_22 Cell_2p Cell_21 Cell_22 Cell_2p
D20 D21 D22 D2p D20 D21 D22 D2p Cell_31 Cell_32 Cell_3p Cell_31 Cell_32 Cell_3p
D30 D31 D32 D3p D30 D31 D32 D3p
Vout Vout
Cout Cout
Cell_s1 Cell_s2 Cell_sp Cell_s1 Cell_s2 Cell_sp
Ds0 Ds1 Ds2 Dsp Ds0 Ds1 Ds2 Dsp Fault tolerance operation group Fault tolerance operation group (a) (b) Sustainability 2018, 10, x FOR PEER REVIEW 9 of 15
4.2. Fault Tolerance for Semiconductor Components Semiconductor components are vulnerable components in a converter [30]. For offshore HVDC stations, faulty components take a long time for maintenance, resulting in high cost and loss [31]. Figure 9 shows the fault tolerance operation derived by installing redundant power cells. To maintain normal operation, the column in a red dotted box containing the damaged Cell 11 is replaced by one redundant column that is in the other red dotted box. For the faulty diodes D00–Ds0, they require only one redundant column since they connect with one column. However, for other diodes, two redundant columns are demanded. For example, when diode D11 fails, the columns 1–2 in the blue dotted box are idle, and the redundant columns p1–p2 are applied.
Failed cell Failed diode
D00 D01 D02 D03 D0p D0p1 D0p2 Cell_11 Cell_12 Cell_13 Cell_1p1 Cell_1p2
D10 D11 D12 D13 D1p D1p1 D1p2 Cell_21 Cell_22 Cell_23 Cell_2p1 Cell_2p2
D20 D21 D22 D23 D2p D2p1 D2p2 Cell_31 Cell_32 Cell_33 Cell_3p1 Cell_3p2
D30 D31 D32 D33 D3p D3p1 D3p2
Vout Cout
Cell_s1 Cell_s2 Cell_s3 Cell_sp1 Cell_sp2
Ds0 Ds1 Ds2 Ds3 Dsp Dsp1 Dsp2
Idle Cells Redundant Cells Figure 9. Fault tolerance with redundancy.
Vo, s p 1 VV== (16) o,, FBC22 s o BC The proposed topology can also obtain fault tolerant operation of diodes and power switches without redundancy. In Figure 10a,b, when diode D11 is short-circuited, the cells in rows 1–2 are inactive to block the faulty components, while the fault tolerance group still operates with the column interleaved strategy. Additionally, to maintain normal operation, the output voltages of the faulty group are controlled according to Equations (2) and (9) to ensure the output voltage is the same as that in the normal case. When diode D11 is open-circuited as illustrated in Figure 10c,d, the fault tolerantSustainability operation2018, 10, 2176group consisting of two columns works under the series interleaved modes10 of to 15 block D11. Compared with the normal operation group, the number of cells in series connection in the faulty group is doubled. The voltages of cells in the fault group are adjusted as illustrated in Equation (15)group to ensure is doubled. they Thehave voltages the same of terminal cells in the voltage. fault group are adjusted as illustrated in Equation (15) to ensureMoreover, they have the the fault same toleran terminalt operation voltage. of damaged cells without redundancy is similar to that whenMoreover, diodes are the short fault-circuited. tolerant For operation instance, of when damaged cell 11 cells fails, without cells 11 redundancy-1p and 21-2p is are similar idle so to that that thewhen faulty diodes one areis blocked. short-circuited. For instance, when cell 11 fails, cells 11-1p and 21-2p are idle so that the faulty one is blocked.
D00 D01 D02 D0p D00 D01 D02 D0p Cell_11 Cell_12 Cell_1p Cell_11 Cell_12 Cell_1p
D10 D11 D12 D1p D10 D11 D12 D1p Cell_21 Cell_22 Cell_2p Cell_21 Cell_22 Cell_2p
D20 D21 D22 D2p D20 D21 D22 D2p Cell_31 Cell_32 Cell_3p Cell_31 Cell_32 Cell_3p
D30 D31 D32 D3p D30 D31 D32 D3p
Vout Vout
Cout Cout
Cell_s1 Cell_s2 Cell_sp Cell_s1 Cell_s2 Cell_sp
Ds0 Ds1 Ds2 Dsp Ds0 Ds1 Ds2 Dsp Fault tolerance operation group Fault tolerance operation group Sustainability 2018, 10, x FOR PEER(a) REVIEW (b) 10 of 15
D00 D01 D02 D0p D00 D01 D02 D0p Cell_11 Cell_12 Cell_1p Cell_11 Cell_12 Cell_1p
D10 D11 D12 D1p D10 D11 D12 D1p Cell_21 Cell_22 Cell_2p Cell_21 Cell_22 Cell_2p
D20 D21 D22 D2p D20 D21 D22 D2p Cell_31 Cell_32 Cell_3p Cell_31 Cell_32 Cell_3p
D30 D31 D32 D3p D30 D31 D32 D3p
Vout Vout
Cout Cout
Cell_s1 Cell_s2 Cell_sp Cell_s1 Cell_s2 Cell_sp1
Ds0 Ds1 Ds2 Dsp Ds0 Ds1 Ds2 Dsp Fault tolerance operation group Normal operation group Fault tolerance operation group Normal operation group (c) (d)
Figure 10. Fault tolerance without redundancy: (a) Working mode 1 under diode short-circuit; (b) Figure 10. Fault tolerance without redundancy: (a) Working mode 1 under diode short-circuit; Working mode 2 under diode short-circuit; (c) Working mode 1 under diode open-circuit; (d) (b) Working mode 2 under diode short-circuit; (c) Working mode 1 under diode open-circuit; Working mode 2 under diode open-circuit. (d) Working mode 2 under diode open-circuit.
5. Simulation Results and Discussion 5. Simulation Results and Discussion To illustrate the functionality of the proposed power converter, a simulation model consisting To illustrate the functionality of the proposed power converter, a simulation model consisting of 3 groups × 4 rows × 5 columns with 2 redundant columns is built by software PSIM, which is of 3 groups × 4 rows × 5 columns with 2 redundant columns is built by software PSIM, which is similar to the model shown in Figure 6. The cells in columns 1-3 are active, while those in columns 4- similar to the model shown in Figure6. The cells in columns 1–3 are active, while those in columns 5 are inactive. 4–5 are inactive. For Figure 12, every group has different numbers of rows. Only one row operates in Group 1; in Table1 presents the initial values for the simulation. It is noted that to verify the auto-balanced Group 2, there are two rows; Group 3 has four rows. The duty-cycle D of cells in each group is current characteristic, the leakage inductances of cells in column 1 are set as 70, 75, 80, 85 µH. regulated to obtain the same terminal voltage, and the voltages of cells are shown in Figure 12 as: Vs_cell 1–11 = 2 × Vs_cell 2–11 = 4 × Vs_cell 3–11 Table= Vout. 1. Initial values of simulation. The peak current values of different columns are almost equal so that the duty-cycle power transmission controlSystem presented Parameters in Equation Values (15) is verified. Components Values Figure 13 shows the voltages of diodes in Group 1–2. The voltage of diodes in Group 3 has the Input Voltage 650 V Turns ratio 1:1:n 1:1:2 same waveformsOutput as those Voltage presented in Figure 6400 V 10. It can Leakage be found inductance that the voltage 80 valueµH is increased as the numberSwitching of idle rows Frequency increases. 5 kHz Input inductance 5 mH µ As illustratedOutput in Figure Power 14, before turning 40 kW on switches Clamp S1 or capacitor SC1, the drain-to-source 20 F current flows through the parasitic diode of the switch to achieve ZVS operation. Similarly, the switches S2 and SC2 can alsoThe obtain steady-state soft-switching. waveforms Therefore, of the converter the switching with theloss same is significantly input power reduced. from WTGs are shown in FigureTable 11 1. presents All groups the work initial under values the for column the simulation. interleaved It is strategy, noted that and to the verify voltages the auto of the-balanced adjacent current characteristic, the leakage inductances of cells in column 1 are set as 70, 75, 80, 85 μH.
Table 1. Initial values of simulation.
System Parameters Values Components Values Input Voltage 650 V Turns ratio 1:1:n 1:1:2 Output Voltage 6400 V Leakage inductance 80 μH Switching Frequency 5 kHz Input inductance 5 mH Output Power 40 kW Clamp capacitor 20 μF
The steady-state waveforms of the converter with the same input power from WTGs are shown in Figure 11. All groups work under the column interleaved strategy, and the voltages of the adjacent cells in the same column have opposite polarities. Meanwhile, the currents of cells with diverse leakage inductances in column 1 are almost equal. The voltage stress of power switches is ¼ of the output voltage, and all diodes have the voltage and current stresses as low as ¼ or ½ of the output voltage and current, respectively. For Figure 12, every group has different numbers of rows. Only one row operates in Group 1; in Group 2, there are two rows; Group 3 has four rows. The duty-cycle D of cells in each group is regulated to obtain the same terminal voltage, and the voltages of cells are shown in Figure 12 as: Vs_cell 1–11 = 2 × Vs_cell 2–11 = 4 × Vs_cell 3–11 = Vout. Sustainability 2018, 10, 2176 11 of 15 cells in the same column have opposite polarities. Meanwhile, the currents of cells with diverse leakage inductances in column 1 are almost equal. The voltage stress of power switches is 1/4 of the output voltage, and all diodes have the voltage and current stresses as low as 1/4 or 1/2 of the output voltage and current, respectively. Sustainability 2018, 10, x FOR PEER REVIEW 11 of 15 SustainabilityFor Figure 2018, 10 12, x, FOR every PEER group REVIEW has different numbers of rows. Only one row operates in Group11 of 15 1; in Group 2, there are two rows; Group 3 has four rows. The duty-cycle D of cells in each group is The peak current values of different columns are almost equal so that the duty-cycle power regulatedThe p toeak obtain current the values same terminal of different voltage, columns and are the almost voltages equal of cells so thatare shown the duty in- Figurecycle power 12 as: transmission control presented in Equation (15) is verified. transmissionVs_cell 1–11 = 2 control× Vs_cell presented2–11 = 4 × inV Eqs_celluation3–11 = (15) Vout is. verified. Figure 13 shows the voltages of diodes in Group 1–2. The voltage of diodes in Group 3 has the FigureThe peak 13 shows current the values voltages of different of diodes columns in Group are 1– almost2. The voltage equal so of thatdiodes the in duty-cycle Group 3 has power the same waveforms as those presented in Figure 10. It can be found that the voltage value is increased sametransmission waveforms control as those presented presented in Equation in Figure (15) 10. is It verified. can be found that the voltage value is increased as the number of idle rows increases. as theFigure number 13 ofshows idle rows the voltages increases. of diodes in Group 1–2. The voltage of diodes in Group 3 has the As illustrated in Figure 14, before turning on switches S1 or SC1, the drain-to-source current flows sameAs waveforms illustrated as in those Figure presented 14, before in turning Figure 10 on. Itswitches can be foundS1 or S thatC1, the the drain voltage-to-source value iscurrent increased flows as through the parasitic diode of the switch to achieve ZVS operation. Similarly, the switches S2 and SC2 throughthe number the ofparasitic idle rows diode increases. of the switch to achieve ZVS operation. Similarly, the switches S2 and SC2 can also obtain soft-switching. Therefore, the switching loss is significantly reduced. can also obtain soft-switching. Therefore, the switching loss is significantly reduced. Vout (V) vD10, 30 (V) vD20 (V) Vout (V) 4K vD10, 30 (V) vD20 (V) 6.8K 4K 6.8K 2K 2K 6.4K 0 6.4K 0 6K vD00, 40 (V) 6K vD00, 40 (V) v (v) v (v) 2000 vs_cell 11,31 (v) vs_cell 21 (v) 2000 2K s_cell 11,31 s_cell 21 1000 2K 1000 1K 0 1K 0 0 i (A) i (A) 0 iD00 (A) iD03 (A) -1K 2 D00 D03 2 --21KK -2K 1 i (A) i (A) 1 is_cell 11,31 (A) is_cell 21 (A) 0 2 s_cell 11,31 s_cell 21 0 2 iD01 (A) iD02 (A) 4 iD01 (A) iD02 (A) 0 4 0 2 2 -2 0 -2 0.2288 0.229 0.2292 00.2288 0.229 0.2292 0.2288 Time0.229 (s) 0.2292 0.2288 Time0.229 (s) 0.2292 Time (s) Time (s) (a) (b) (a) (b) Figure 11. Steady-state waveforms for cells and diode: (a) voltage/current of basic cells; (b) Figure 11. SteadySteady-state-state waveform waveformss for for cells cells and and diode: diode: (a) ( voltage/currenta) voltage/current of basic of basic cells; cells; (b) voltage/current of diodes. voltage/current(b) voltage/current of diodes. of diodes.
Vout (V) V (V) 6.8K out 6.8K 6.4K 66.4KK 6K vS_Cell 1-11 (V) 10K vS_Cell 1-11 (V) 105KK 50K -5K0 -10-5KK -10K vS_Cell 2-11 (V) 4K vS_Cell 2-11 (V) 24KK 20K -2K0 --42KK -4K vS_Cell 3-11 (V) 2K vS_Cell 3-11 (V) 12KK 10K -1K0 --21KK -2K iS_Cell 1-11 (A) iS_Cell 2-11 (A) iS_Cell 3-11 (A) 4 iS_Cell 1-11 (A) iS_Cell 2-11 (A) iS_Cell 3-11 (A) 24 02 -20 --42 -4 0.3925 0.3926 0.3927 0.3928 0.3925 0.3926 Time (s) 0.3927 0.3928 Time (s)
Figure 12. Waveforms of cells when Groups 1–3 have different output power. FigureFigure 12. 12. WaveformsWaveforms of of cells cells when when Groups Groups 1 1–3–3 have different output power power.. Sustainability 2018, 10, 2176 12 of 15 Sustainability 2018, 10, x FOR PEER REVIEW 12 of 15
v (V) 8K D1-00 Sustainability 2018, 10, x FOR PEER REVIEW 12 of 15 4K 0v (V) 8K D1-00 vD1-10,20,30,40 (V) 4K1500 1000 0 500 0 vD1-10,20,30,40 (V) 0.3925 0.3926 Time (s) 0.3927 0.3928 1500 1000 (a)
500 vD2-00 (V) 30000 2000 1000 0.3925 0.3926 Time (s) 0.3927 0.3928 0 vD2-10 (V) 8K (a) 4KvD2-00 (V) 3000 0 2000 vD2-20,30,40 (V) 10001500 01000 500vD2-10 (V) 8K 0 4K 0.3925 0.3926 Time (s) 0.3927 0.3928 0 (b) vD2-20,30,40 (V) 1500 Figure 13. Voltages1000 of diodes in each Group when Groups 1–3 have different output power: (a) Figure 13. Voltages of500 diodes in each Group when Groups 1–3 have different output power: (a) Voltages Voltages of diodes 0in Group 1; (b) Voltages of diodes in Group 2. of diodes in Group 1; (b) Voltages of diodes in Group 2. 0.3925 0.3926 Time (s) 0.3927 0.3928 Vg1 (V) Vgc1 (V) ZVS 0 (b) As illustrated in Figure 14, before turning on switches S1 or SC1, the drain-to-source current flows throughFigure the 13. parasitic Voltages diode of diodes of the in switch each Groupto achieve when ZVS Groups operation. 1–3 have Similarly, different the output switches power:S2 and (a) SC2 can alsoVoltages obtain of diodes soft-switching. in Group 1; Therefore,0 (b) Voltages the of switching diodes in Group loss is 2. significantly reduced. Vg2 (V) Vgc2 (V) 2K 1K Vg1 (V) Vgc1 (V) ZVS 0 0
ids1 (A) idsc1 (A) 0 2 0 Vg2 (V) Vgc2 (V) 2K-2 0.2288 0.229 0.2292 1K Time (s) 0 Figure 14. Zero voltage switching (ZVS) of main switches and clamping switches. ids1 (A) idsc1 (A) 2 Figure 15a shows the fault tolerance operation with redundancy. At 0.07 s, fault cells 1–2 are idle, and the redundant columns0 4–5 start to work to guarantee normal operation. Figure 15b,c -2 presents the fault tolerance without0.2288 redundancy, 0where.229 only column0.2292s 1–3 are active. In Figure 15b, when the diode D11 is short-circuited, the cells in Timerows (1s)–2 are blocked. The voltages of cells in row 3–4 are doubled to achieve the same terminal voltage. The diode D11 is open in Figure 15c. The faulty group consistingFigure 14.of columnsZZeroero voltage 1–2 worksswitching in the ( (ZVS)ZVS series) of maininterleaved switches mode and by clamping changing switches switches. the polarities. of cells. Moreover, the voltages of cells in the faulty group are reduced to half of that in the normal operation group to obtain the same output voltage. Figure 1515aa showsshows thethe fault fault tolerance tolerance operation operation with with redundancy. redundancy. At At 0.07 0.07 s, fault s, fault cells cells 1–2 are1–2 idle,are idle,and the and redundant the redundant columns columns 4–5 start 4– to5 workstart to guarantee work to guarantee normal operation. normal Figure operation. 15b,c Figure presents 15b,c the presentsfault tolerance the fault without tolerance redundancy, without whereredundancy, only columns where 1–3only are column active.s In1– Figure3 are active. 15b, when In Figur thee diode 15b, when the diode D11 is short-circuited, the cells in rows 1–2 are blocked. The voltages of cells in row D11 is short-circuited, the cells in rows 1–2 are blocked. The voltages of cells in row 3–4 are doubled to 3–4 are doubled to achieve the same terminal voltage. The diode D11 is open in Figure 15c. The faulty achieve the same terminal voltage. The diode D11 is open in Figure 15c. The faulty group consisting groupof columns consisting 1–2 works of columns in the 1 series–2 works interleaved in the series mode interleaved by changing mode the by polarities changing of cells.the polarities Moreover, of cells.the voltages Moreover, of cells the involtages the faulty of cells group in arethe reducedfaulty group to half are of reduced that in the to normalhalf of operationthat in the group normal to operationobtain the group same outputto obtain voltage. the same output voltage. Sustainability 2018, 10, 2176 13 of 15 Sustainability 2018, 10, x FOR PEER REVIEW 13 of 15
Vout (V) V (V) 8K out 8K 4K 0K 4K VS_cell_idle (V) 0 2K VS_cell row 1~2 (V) 0K 2K -2K VS_cell_redundancy (V) 0 2K 0K -2K VS_cell fault_opration (V) -2K 4K VS_cell_normal (V) 2K 0 0K -4K -2K 0.06 0.07 0.08 0.1 0.06 0.07 0.08 0.1 Time (s) Time (s)
(a) (b) SustainabilitySustainability 2018 2018, 10, 10, x, FORx FOR PEER PEER REVIEW REVIEW 1313 of of15 15 Vout (V) 10000 6000 VoutV out(V ()V) 20001000010000 60006000iD11 (A) 200082000 4 0 iD11iD (11A ()A) 8VS8_Cell 11 (V) 2000 4 4 0 0 0 -2000 VSV_CellS_Cell 11 (11V ()V) 20002000VS_Cell 12 (V) 2000 0 0 -20000-2000 -2000 VSV_CellS_Cell 12 (12V ()V) 20002000VS_Cell 13 (V) 2000 0 0 -20000-2000 -2000 VSV_CellS_Cell 13 (13V ()V) 0.06 0.07 0.08 0.1 20002000 Time (s) 0 0 -2000-2000 0.060.06(c)0 .070.07 0.080.08 0.10.1 TimeTime (s )(s) Figure 15. Fault tolerance operation: (a) With redundancy; (b) Without redundancy for D11 short- Figure 15. Fault tolerance operation: (a) With redundancy;(c() c) (b) Without redundancy for D11 short-circuit; circuit; (c) Without redundancy for D11 open-circuit. (c) Without redundancy for D11 open-circuit. FigureFigure 15. 15. Fault Fault tolerance tolerance op operation:eration: (a )( aWith) With redundancy; redundancy; (b ()b Without) Without redundancy redundancy for for D 11D 11short short- - Wherecircuit;circuit; N (c is)( cWithout )the Without number redundancy redundancy of SMs foror for power D 11D open11 open cells;-circuit.-circuit. n is the turns ratio of transformers. Table 2 shows a performanceWhere N is comparison the number among of SMs several or power literatures cells; n. Due is the to turnshard switching, ratio of transformers. References [21, Table23] 2ha showsve a performancehigherWhere Where switching N comparisonN is isthe losses. the number number Multi among of- moduleof SM SMs several ors or power converters power literatures. cells; cells; can n nis achieve isthe Due the turns turns to a hard higherratio ratio switching,of voltageof transformers transformers step References-up. Table . ratioTable 2 [ by 21shows2 shows,23] haveincreasinga performancea higherperformance the switching power comparison comparison cells losses. number among Multi-module among and several several the volta literatures converters literaturesge gain. ofDue can. Duepower achieveto to hard hardcells. switching, a switching,For higher MMCs, voltage References References fault step-up tolerance [21, [21, ratio23] 23]is ha byhaveve increasingachievedhigherhigher switching the byswitching power redundancy. losses. cellslosses. number Multi However, Multi-module- andmodule the the convertersproposed voltageconverters gain convertercan can of achieve power achieve has cells.a anahigher higher improvedFor MMCs,voltage voltage fault faultstep step tolerance- toleranceup-up ratio ratio by is by achievedcapabilityincreasingincreasing by which redundancy. the the power can power maintain cells However,cells number numbernormal the and operation and proposed the the volta volta without convertergege gain gain redundancy. of hasof power power an improved cells. Therefore, cells. For For faultMMCs, toMMCs, achieve tolerance fault fault the tolerance capability sametolerance is is whichperformance,achievedachieved can maintain by by a redundancy.mu redundancy. normallti-module operation However,converter However, without with the the CFPP redundancy.proposed proposed cells requiresconverter Therefore,converter fewer has tohas com achievean anponents. improved improved the same fault performance,fault tolerance tolerance a multi-modulecapabilitycapability which which converter can can maintain maintain with CFPP normal normal cells operation operation requires without fewer without components. redundancy. redundancy. Therefore, Therefore, to to achieve achieve the the same same Table 2. Performance comparison. performance,performance, a mua multilti-module-module converter converter with with CFPP CFPP cells cells requires requires fewer fewer com components.ponents. MMCsTable 2. Performance comparison.Multi-Module Converters
HB/FB [21,32] ResonantTableTable 2. MMC 2.Performance Performance [20] comparisonFlyback comparison–Forw. .ard [23] CFPP Converter Soft-switching MMCs✓ Multi-Module Converters✓ MMCsMMCs 1MultiMulti-Module-Module Converters Converters1 Conversion ratio HB/FB Nn, [21 ,32] Resonant N MMC [20] Flyback–ForwardNn,, [23] Nn CFPP,, Converter HB/FBHB/FB [21,32] [21,32] ResonantResonant MMC MMC [20] [20] FlybackFlyback1−–DForw–Forwardard [23] [23] CFPPCFPP1− D Converter Converter Soft-switching SoftTransformerSoft-switching-switching Large Small Small Conversion ratio ∝ N, n ∝ N ∝ N, 1 , n ∝ N, 1 , n Fault tolerance Low Low Medium 11−1D High 1−1D1 TransformerConversionConversion ratio ratio ∝ Large∝Nn,Nn, ∝∝NN ∝∝Nn,,NnSmall,, ∝∝Nn Small,,Nn,, − − − − Fault tolerance Low Low Medium1 1DD High1 1DD 6. ConclusionTransformerTransformers LargeLarge SmallSmall SmallSmall FaultFault tolerance tolerance LowLow LowLow MediumMedium HighHigh 6. ConclusionsA multi-port high voltage gain modular DC/DC power converter applied in offshore wind farms is proposed in this paper. Thanks to the modularity, the high output voltage and power is achieved 6. 6.AConclusion Conclusion multi-ports highs voltage gain modular DC/DC power converter applied in offshore wind farms is proposedAA multi multi in- thisport-port paper. high high voltage Thanksvoltage gain togain the modular modular modularity, DC/DC DC/DC the power power high converter output converter voltage applied applied and in in offshore power offshore is wind achievedwind farms farms is isproposed proposed in in this this paper. paper. Thanks Thanks to to the the modularity, modularity, the the high high output output voltage voltage and and power power is isachieved achieved byby adding adding power power cells. cells. With With the the independent independent operation operation of of each each port port and and high high control control flexibility, flexibility, the the converterconverter can can collect collect power power from from multi multi-sources-sources without without bus bus cable. cable. Additionally, Additionally, the the CFPP CFPP cells cells reducereduce the the switching switching losses losses and and control control complexity. complexity. TheThe performances performances of of MMC MMC with with galvanic galvanic isolation, isolation, resonant resonant MMC, MMC, multi multi-module-module converter converter withwith flyback flyback–forwarding–forwarding cells cells and and CFPP CFPP cells cells are are compared. compared. The The proposed proposed model model appears appears to to be be more more efficientefficient and and reliable, reliable, including including fewer fewer switching switching losses, losses, higher higher conversion conversion ratio, ratio, fewer fewer components, components, smallersmaller volume volume, and, and high higherer reliability. reliability. TheThe simulation simulation re resultssults verify verify the the advantages advantages of of the the proposed proposed converter converter are are the the soft soft-switching-switching of of allall power power switches, switches, flexible flexible control, control, and and impr improvedoved fault fault tolerance tolerance operation. operation.
AuthorAuthor Contributions: Contributions: Conceptualization, Conceptualization, Y .H.Y.H. and and G.C. G.C.; ;Formal Formal analysis, analysis, S.S. S.S. and and Y.H. Y.H.; ; InvestigatInvestigation,ion, S.S. S.S.; Methodology,; Methodology, S.S. S.S., Y.H., Y.H. and and G.C. G.C.; Software,; Software, S.S. S.S. and and G.C. G.C.; Supervision,; Supervision, Y.H. Y.H.; ; Validation,Validation, S.S. S.S.; Writing; Writing——originaloriginal draft, draft, S.S. S.S.; Writing; Writing——reviewreview and and editing, editing, K.N. K.N., J.Y., J.Y., H.W., H.W. and and X.Y X.Y. . Sustainability 2018, 10, 2176 14 of 15 by adding power cells. With the independent operation of each port and high control flexibility, the converter can collect power from multi-sources without bus cable. Additionally, the CFPP cells reduce the switching losses and control complexity. The performances of MMC with galvanic isolation, resonant MMC, multi-module converter with flyback–forwarding cells and CFPP cells are compared. The proposed model appears to be more efficient and reliable, including fewer switching losses, higher conversion ratio, fewer components, smaller volume, and higher reliability. The simulation results verify the advantages of the proposed converter are the soft-switching of all power switches, flexible control, and improved fault tolerance operation.
Author Contributions: Conceptualization, Y.H. and G.C.; Formal analysis, S.S. and Y.H.; Investigation, S.S.; Methodology, S.S., Y.H. and G.C.; Software, S.S. and G.C.; Supervision, Y.H.; Validation, S.S.; Writing—original draft, S.S.; Writing—review and editing, K.N., J.Y., H.W. and X.Y. Funding: This study is supported by the State Key Laboratory of Alternate Electrical Power System with Renewable Energy Sources under Grant LAPS17022. Conflicts of Interest: The authors declare no conflict of interest.
References
1. Zervos, A.; Kjaer, C. Pure Power. Wind Energy Scenarios up to 2030; The European Wind Energy Association (EWEA): Brussels, Belgium, 2006. 2. Council, G.W.E. Global Wind Report 2016. Available online: http://files.gwec.net/files/GWR2016.pdf?ref= Website (accessed on 25 June 2018). 3. Remy, T.; Mbistrova, A. Offshore Wind in Europe-Key trends and statistics 2017. Available online: https://windeurope.org/wp-content/uploads/files/about-wind/statistics/WindEurope-Annual- Offshore-Statistics-2017.pdf (accessed on 25 June 2018 ). 4. Oni, O.E.; Davidson, I.E.; Mbangula, K.N. A review of LCC-HVDC and VSC-HVDC technologies and applications. In Proceedings of the 2016 IEEE 16th International Conference on Environment and Electrical Engineering (EEEIC), Florence, Italy, 7–10 July 2016. 5. Oates, C. Modular multilevel converter design for VSC HVDC applications. IEEE J. Emerg. Sel. Top. Power Electron. 2015, 3, 505–515. [CrossRef] 6. Van Eeckhout, B.; Van Hertem, D.; Reza, M.; Srivastava, K.; Belmans, R. Economic comparison of VSC HVDC and HVAC as transmission system for a 300 MW offshore wind farm. Eur. Trans. Electr. Power 2009, 20, 661–671. [CrossRef] 7. Chen, W.; Huang, A.Q.; Li, C.; Wang, G.; Gu, W. Analysis and comparison of medium voltage high power DC/DC converters for offshore wind energy systems. IEEE Trans. Power Electron. 2013, 28, 2014–2023. [CrossRef] 8. Meyer, C.; Hoing, M.; Peterson, A.; De Doncker, R.W. Control and design of DC grids for offshore wind farms. IEEE Trans. Ind. Appl. 2007, 43, 1475–1482. [CrossRef] 9. Wang, X.; Cao, C.; Zhou, Z. Experiment on fractional frequency transmission system. IEEE Trans. Power Syst. 2006, 21, 372–377. 10. Vechalapu, K.; Bhattacharya, S.; Van Brunt, E.; Ryu, S.-H.; Grider, D.; Palmour, J.W. Comparative evaluation of 15-kv sic mosfet and 15-kv sic igbt for medium-voltage converter under the same dv/dt conditions. IEEE J. Emerg. Sel. Top. Power Electron. 2017, 5, 469–489. [CrossRef] 11. Nami, A.; Liang, J.; Dijkhuizen, F.; Demetriades, G.D. Modular Multilevel Converters for HVDC Applications: Review on Converter Cells and Functionalities. IEEE Trans. Power Electron. 2015, 30, 18–36. [CrossRef] 12. Ghat, M.B.; Shukla, A. A New H-Bridge Hybrid Modular Converter (HBHMC) for HVDC Application: Operating Modes, Control, and Voltage Balancing. IEEE Trans. Power Electron. 2018, 33, 6537–6554. [CrossRef] 13. Gowaid, I.; Adam, G.; Massoud, A.M.; Ahmed, S.; Williams, B. Hybrid and Modular Multilevel Converter Designs for Isolated HVDC–DC Converters. IEEE J. Emerg. Sel. Top. Power Electron. 2018, 6, 188–202. [CrossRef] Sustainability 2018, 10, 2176 15 of 15
14. Soltau, N.; Stagge, H.; De Doncker, R.W.; Apeldoorn, O. Development and demonstration of a medium-voltage high-power dc-dc converter for dc distribution systems. In Proceedings of the 2014 IEEE 5th International Symposium on Power Electronics for Distributed Generation Systems (PEDG), Galway, Ireland, 24–27 July 2014. 15. Engel, S.P.; Soltau, N.; Stagge, H.; De Doncker, R.W. Dynamic and balanced control of three-phase high-power dual-active bridge DC–DC converters in DC-grid applications. IEEE Trans. Power Electron. 2013, 28, 1880–1889. [CrossRef] 16. Chen, W.; Wu, X.; Yao, L.; Jiang, W.; Hu, R. A step-up resonant converter for grid-connected renewable energy sources. IEEE Trans. Power Electron. 2015, 30, 3017–3029. [CrossRef] 17. Meyer, C.; De Doncker, R.W. Design of a three-phase series resonant converter for offshore DC grids. In Proceedings of the 42nd IAS Annual Meeting. Conference Record of the 2007 IEEE on Industry Applications Conference, New Orleans, LA, USA, 23–27 September 2007. 18. Kish, G.J.; Ranjram, M.; Lehn, P.W. A modular multilevel DC/DC converter with fault blocking capability for HVDC interconnects. IEEE Trans. Power Electron. 2015, 30, 148–162. [CrossRef] 19. Martinez-Rodrigo, F.; Ramirez, D.; Rey-Boue, A.B.; de Pablo, S.; Herrero-de Lucas, L.C. Modular Multilevel Converters: Control and Applications. Energies 2017, 10, 1709. [CrossRef] 20. Zhang, X.; Xiang, X.; Green, T.C.; Yang, X. Operation and Performance of Resonant Modular Multilevel Converter with Flexible Step Ratio. IEEE Trans. Ind. Electron. 2017, 64, 6276–6286. [CrossRef] 21. Kenzelmann, S.; Rufer, A.; Dujic, D.; Canales, F.; De Novaes, Y.R. Isolated DC/DC structure based on modular multilevel converter. IEEE Trans. Power Electron. 2015, 30, 89–98. [CrossRef] 22. Gowaid, I.; Adam, G.; Massoud, A.M.; Ahmed, S.; Holliday, D.; Williams, B. Quasi two-level operation of modular multilevel converter for use in a high-power DC transformer with DC fault isolation capability. IEEE Trans. Power Electron. 2015, 30, 108–123. [CrossRef] 23. Hu, Y.; Zeng, R.; Cao, W.; Zhang, J.; Finney, S.J. Design of a Modular, High Step-Up Ratio DC–DC Converter for HVDC Applications Integrating Offshore Wind Power. IEEE Trans. Ind. Electron. 2016, 63, 2190–2202. [CrossRef] 24. Chen, G.; Deng, Y.; He, X.; Hu, Y.; Jiang, L. Analysis of high voltage gain DC-DC converter with active-clamping current-fed push-pull cells for HVDC-connected offshore wind power. In Proceedings of the 42nd Annual Conference of the IEEE Industrial Electronics Society (IECON 2016), Florence, Italy, 23–26 October 2016. 25. Mohammadpour, A.; Parsa, L.; Todorovic, M.H.; Lai, R.; Datta, R.; Garces, L. Series-input parallel-output modular-phase dc–dc converter with soft-switching and high-frequency isolation. IEEE Trans. Power Electron. 2016, 31, 111–119. [CrossRef] 26. Xiang, X.; Zhang, X.; Chaffey, G.P.; Green, T.C. An Isolated Resonant Mode Modular Converter with Flexible Modulation and Variety of Configurations for MVDC Application. IEEE Trans. Power Deliv. 2017, 33, 508–519. [CrossRef] 27. Nome, F.J.; Barbi, I. A ZVS clamping mode-current-fed push-pull DC-DC converter. In Proceedings of the IEEE International Symposium on Industrial Electronics (ISIE’98), Pretoria, South Africa, 7–10 July 1998. 28. Duong, M.Q.; Leva, S.; Mussetta, M.; Le, K.H. A Comparative Study on Controllers for Improving Transient Stability of DFIG Wind Turbines during Large Disturbances. Energies 2018, 11, 480. [CrossRef] 29. Wang, H.; Wang, Y.; Duan, G.; Hu, W.; Wang, W.; Chen, Z. An Improved Droop Control Method for Multi-Terminal VSC-HVDC Converter Stations. Energies 2017, 10, 843. [CrossRef] 30. Yang, Z.; Chai, Y. A survey of fault diagnosis for onshore grid-connected converter in wind energy conversion systems. Renew. Sustain. Energy Rev. 2016, 66, 345–359. [CrossRef] 31. Zhang, W.; Xu, D.; Enjeti, P.N.; Li, H.; Hawke, J.T.; Krishnamoorthy, H.S. Survey on fault-tolerant techniques for power electronic converters. IEEE Trans. Power Electron. 2014, 29, 6319–6331. [CrossRef] 32. Zhang, X.; Green, T.C. The modular multilevel converter for high step-up ratio DC–DC conversion. IEEE Trans. Ind. Electron. 2015, 62, 4925–4936. [CrossRef]
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