DOCSLIB.ORG

Assembly Using X-Wire™ Insulated Bonding Wire Technology

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Assembly Using X-Wire™ Insulated Bonding Wire Technology Assembly Using X-Wire™ Insulated Bonding Wire Technology Robert Lyn, William (Bud) Crockett, Microbonds, Inc. Markham, ON, Canada Presented at SEMICON Singapore 2007 Assembly Using X-Wire™ Insulated Bounding Wire Technology Page 1 ABSTRACT and systems architects have had to make to accommodate the shortcomings in the As the semiconductor industry continues to move interconnection (packaging) technology available. towards higher pin count, finer pitch, multi-row and multi- stack devices, wire bonding becomes an CHIP LEVEL INTERCONNECTION increasing challenge for today’s advanced packaging processes. Insulated bonding wire An important first step in electronics packaging technology, known as X-Wire™, has been identified interconnections are the chip-level, (also called on the 2006 ITRS Roadmap for Semiconductors first-level) interconnects. This interconnect will [1], as a viable, cost-effective solution to enable dictate to a high degree how much performance complex package designs, enhance package can be achieved from a chip. Performance is performance, and improve the yield of high-density critical; however, an IC product manager cannot packaging. consider performance in isolation to other economic factors. Important considerations in a full In order to successfully implement insulated wire benefit/cost tradeoff analysis can be grouped into bonding, low cost integration into the existing the following categories: (1) Cost, (2) Performance, packaging assembly infrastructure is of utmost (3) Size/Density, and (4) Time-to-Market. importance. In particular, it is a requirement that Packaging technologies are typically evaluated on the insulated bonding wires demonstrate this basis. wirebonding and package assembly performance which meets industry standard wire bond package Although many types of first-level interconnection test specifications when used on existing technologies exist to connect chip-to-chip, and wirebonding and packaging assembly platforms. chip-to-substrate, two primary methods continue to This paper will discuss various methods, dominate the industry: (1) Wire bonding & (2) Flip techniques and processes developed to date that Chip (a form of Wafer Level Packaging), with allow insulated wire packages to be assembled with wirebonding holding greater than 90 percent of the high yield and reliability using current production market. Over time, niche technologies such TAB equipment. Proper capillary selection and wire (tape-automated-bonding) and more recently, bonder setup, as well as correct use of bond through- silicon-via (TSV), have emerged to provide parameters, loop parameters, plasma parameters alternate solutions to specific interconnection and other advanced wirebond and packaging challenges. techniques will be highlighted. INSULATED WIRE BONDING BACKGROUND – SYSTEM PACKAGING SELECTION The semiconductor industry has been seeking a viable insulated wire bonding solution for almost as IC packaging is often described as the linkage long as wirebonding technology has been available between the silicon and the system. In layman’s [2,3]. The benefits of insulated wire bonding have terms, electronics packaging can be described as been well known and clear for many years: the process of connecting chips together to create an electronic system. The ultimate technical goal is With respect to a full benefit/cost tradeoff analysis, to deliver the highest performance chip function to insulated bonding wire provides: the end-user at the lowest cost; however, limitations in packaging and chip manufacturing 1) Cost: technology create a ‘drag’ in the system which a. The ability to use the lowest cost reduce the final performance to the user. These manufacturing infrastructure, which limitations are the compromises that chip designers is wirebonding. www.NordsonMARCH.com Assembly Using X-Wire™ Insulated Bounding Wire Technology Page 2 2) Performance: wirebonding at the forefront of the lowest a. The ability to allow more cost/highest performance I/O battleground. interconnections per unit area at the chip level, enabling low cost ‘die WAFER LEVEL PACKAGING & FLIP CHIP shrink’ chips and reducing pad- TECHNOLOGY limitations. b. The ability to connect chips directly Wafer Level Packaging Technology is an emerging together for highest bandwidth interconnection technology for the IC packaging connection, eliminating layers of industry, generally referring to a technique in which chip, substrate and board level bumps applied directly to a wafer, after which the wiring and allowing flexible routing. wafer is diced into individual ICs. Wafer level c. The ability to bring signal and packaging is used in applications requiring small ground wires very close together to form factor, high density and/or low-inductance. minimize inductance. Flip chip can be cost/benefit effective for wiring out 3) Size: very high I/O chips (> 1000) and high frequency a. The ability to place chips tightly applications with similarly low inductance. In together, known as ‘brick-walling’, relation to wirebonding, the commodity not requiring a wire-bond fan-out or infrastructure for wafer level packaging and flip chip keep-out area. remains in the early stages, as indicated by its b. The ability to connect stack dies relatively higher cost; particularly at low-to-medium directly and flexibility in a wide volumes. variety of configurations. 4) Time-to Market: Flip chip does offer some technical advantages a. The ability to use existing chips over bare wire bonding for very high I/O, high immediately without additional chip speed devices, but at high cost compared to the or wafer processing. existing wire-bonding infrastructure currently in b. The flexibility to be applied on a wide place. Flip chip for high I/O single-chip packages range of applications also competes with advances in system-on-a-chip (SOC) technology, resulting in an overall chip I/O Because of its flexibility and cost effectiveness and eduction in very high pincount devices. Wire- because it leverages a significant amount of proven bonding offers the most flexible and cost-effective human capital, wire bonding is the dominant interconnection method, particularly where it technology in the semiconductor packaging embraces advanced materials and will be further industry, used in over 90 percent of all IC extended by advances in system-on-a-chip. packages. Prior to insulated wire bonding, previous limitations to wirebonding have been that the PACKAGING COST – THE FINAL ARBITER interconnections have been confined to the perimeter of the chip, and as chip I/Os have In the semiconductor packaging industry, where increased this has created a need to develop economic improvement is measured in fractions of technologies which have area array capability, i.e., pennies, cost ultimately rules. Costs relative to chip I/Os which are not restricted to the perimeter. packaging technology selection can be considered A secondary concern with wirebonding had been in two main categories: (1) Infrastructure adoption inductance of long and parallel wires; which can be costs, and (2) Per-Unit scaling costs. alleviated using crossed and closely packed insulated wires. Copper wirebonding, both insulated Incremental Infrastructure Adoption Costs: and non-insulated is also gaining prominence for With respect to adoption cost, it is clear that performance and cost advantages, helping to keep wirebonding is the preferred platform, because of www.NordsonMARCH.com Assembly Using X-Wire™ Insulated Bounding Wire Technology Page 3 the extensive installed base of equipment, The Yole methodology confirms bare wirebonding materials and human capital as well as interconnect as currently the lowest cost IC interconnect flexibility. It cannot be overstated that a key technology, relative to flip chip, while the real costs decision point for the product manager, CTO and for thru-silicon-via are yet to be determined. assembly house is to increase I/O capability at the lowest possible incremental cost. An example Focusing on the flip chip and wirebond scaling cost ranking of incremental adoption costs of selected graphs, from the above chart, it can be appreciated packaging technologies is typically considered to that the extension of wirebond technology with be: insulated wire achieves additional interconnect 1) Wirebonding (including insulated wire) capability increase at a fraction of the incremental 2) Wafer Level Packaging & Flip Chip adoption cost, once the traditional capability 3) Tape Automated Bonding (TAB) limitations of 2D & 3D parallelism are removed. 4) Thru-Silicon-Via (TSV) Hence, the justification for many industry attempts developing a commercially viable insulated bonding Per-Unit Scaling Costs: wire technology is clearly understood. A recently completed study by Yole [5], provides a type of methodology for comparing per-unit, scaling Therefore, considering the cost and benefit costs of the various packaging technologies. The together, overall packaging technology selection comprehensive 250 page report, on the subject of criteria may be summarized in Table 1: 3D packaging alternatives, examines technologies such as bare (i.e. not insulated) wirebonding, flip Wire Bond Flip Chip TSV chip and package-on-package (POP), in + Insulated comparison to a new approach called through Med- Cost Very Low Very High silicon via (TSV). The cost per interconnect on a High wafer basis, for first- level interconnect alternatives, Early is plotted on a chart. For reference purposes, a Infrastructure Mature None 9x9mm die is
Load more

Recommended publications
  • Copper Wire Bond Failure Mechanisms
    COPPER WIRE BOND FAILURE MECHANISMS Randy Schueller, Ph.D. DfR Solutions Minneapolis, MN ABSTRACT formation with copper wire. Wire bonding a die to a package has traditionally been performed using either aluminum or gold wire. Gold wire If copper were an easy drop-in replacement for gold the provides the ability to use a ball and stitch process. This industry would have made the change long ago. technique provides more control over loop height and bond Unfortunately copper has a few mechanical property placement. The drawback has been the increasing cost of the differences that make it more difficult to use as a wire bond gold wire. Lower cost Al wire has been used for wedge- material. Cu has a higher Young’s Modulus (13.6 vs. 8.8 2 wedge bonds but these are not as versatile for complex N/m ), thus it is harder than gold and, more significantly, package assembly. The use of copper wire for ball-stitch copper work hardens much more rapidly than gold. This bonding has been proposed and recently implemented in means that during the compression of the ball in the bonding high volume to solve the cost issues with gold. As one operation, the copper ball becomes much harder while the would expect, bonding with copper is not as forgiving as gold remains soft and deforms more easily. A thin layer of with gold mainly due to oxide growth and hardness oxide on the copper also makes bonding more challenging, differences. This paper will examine the common failure especially on the stitch side of the bond.
    [Show full text]
  • Thermosonic Wire Bonding
    Thermosonic Wire Bonding General Guidelines Application Note – AN1002 1. Introduction 1.1. Wire Bonding Methods Wire bonding is a solid state welding process, where two metallic materials are in intimate contact, and the rate of metallic interdiffusion is a function of temperature, force, ultrasonic power, and time. There are three wire bonding technologies: thermocompression bonding, thermosonic bonding, and ultrasonic bonding. Thermocompression bonding is performed using heat and force to deform the wire and make bonds. The main process parameters are temperature, bonding force, and time. The diffusion reactions progress exponentially with temperature. So, small increases in temperature can improve bond process significantly. In general, thermocompression bonding requires high temperature (normally above 300°C), high force, and long bonding time for adequate bonding. The high temperature and force can damage some sensitive dies. In addition, this process is very sensitive to bonding surface contaminants. Thermocompression is, therefore, seldom used now in optoelectronic and IC applications. Thermosonic bonding is performed using a heat, force, and ultrasonic power to bond a gold (Au) wire to either an Au or an aluminum (Al) surface on a substrate. Heat is applied by placing the package on a heated stage. Some bonders also have heated tool, which can improve the wire bonding performance. Force is applied by pressing the bonding tool into the wire to force it in contact with the substrate surface. Ultrasonic energy is applied by vibrating the bonding tool while it is in contact with the wire. Thermosonic process is typically used for Au wire/ribbon. Ultrasonic bonding is done at room temperature and performed by a combination of force and ultrasonic power.
    [Show full text]
  • Copper Wire Bonding
    Copper Wire Bonding Preeti S. Chauhan • Anupam Choubey ZhaoWei Zhong • Michael G. Pecht Copper Wire Bonding Preeti S. Chauhan Anupam Choubey Center for Advanced Life Cycle Industry Consultant Engineering (CALCE) Marlborough, MA, USA University of Maryland College Park, MD, USA Michael G. Pecht Center for Advanced Life Cycle ZhaoWei Zhong Engineering (CALCE) School of Mechanical University of Maryland & Aerospace Engineering College Park, MD, USA Nanyang Technological University Singapore ISBN 978-1-4614-5760-2 ISBN 978-1-4614-5761-9 (eBook) DOI 10.1007/978-1-4614-5761-9 Springer New York Heidelberg Dordrecht London Library of Congress Control Number: 2013939731 # Springer Science+Business Media New York 2014 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. Exempted from this legal reservation are brief excerpts in connection with reviews or scholarly analysis or material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work. Duplication of this publication or parts thereof is permitted only under the provisions of the Copyright Law of the Publisher’s location, in its current version, and permission for use must always be obtained from Springer. Permissions for use may be obtained through RightsLink at the Copyright Clearance Center.
    [Show full text]
  • For Copper Wire Bonds E
    Body of Knowledge (BOK) for Copper Wire Bonds E. Rutkowski1 and M. J. Sampson2 1. ARES Technical Services Corporation, 2. NASA Goddard Space Flight Center Executive Summary Copper wire bonds have replaced gold wire bonds in the majority of commercial semiconductor devices for the latest technology nodes. Although economics has been the driving mechanism to lower semiconductor packaging costs for a savings of about 20% by replacing gold wire bonds with copper, copper also has materials property advantages over gold. When compared to gold, copper has approximately: 25% lower electrical resistivity, 30% higher thermal conductivity, 75% higher tensile strength and 45% higher modulus of elasticity. Copper wire bonds on aluminum bond pads are also more mechanically robust over time and elevated temperature due to the slower intermetallic formation rate – approximately 1/100th that of the gold to aluminum intermetallic formation rate. However, there are significant tradeoffs with copper wire bonding - copper has twice the hardness of gold which results in a narrower bonding manufacturing process window and requires that the semiconductor companies design more mechanically rigid bonding pads to prevent cratering to both the bond pad and underlying chip structure. Furthermore, copper is significantly more prone to corrosion issues. The semiconductor packaging industry has responded to this corrosion concern by creating a palladium coated copper bonding wire, which is more corrosion resistant than pure copper bonding wire. Also, the selection of the device molding compound is critical because use of environmentally friendly green compounds can result in internal CTE (Coefficient of Thermal Expansion) mismatches with the copper wire bonds that can eventually lead to device failures during thermal cycling.
    [Show full text]
  • Chapter 9 Chip Bonding At
    9 CHIP BONDING AT THE FIRST LEVEL The I/O interface to the die primarily interconnects electrical power, ground and signals. It must provide for low impedance for the power distribution system, so as to keep switching noise within specification, and controlled impedance for the signal leads to allow adequate signal integrity. In addition it must accommodate all the I/O and power and ground leads required, and at the same time, minimize the cost for high volume assembly. The secondary role of chip bonding is to be mechanically robust, not interfere with thermal man- agement and be the geometrical transformer from the die features to the next level of packaging features. There are many options for the next level of interconnect, including: ¥ leadframe in a single chip package ¥ ceramic substrate in a single chip package ¥ laminate substrate in a single chip package ¥ ceramic substrate in a multichip module ¥ laminate substrate in a multichip module ¥ glass substrate, such as an LCD (liquid crystal display) ¥ laminate substrate, such as a circuit board ¥ ceramic substrate, such as a circuit board For all of these first level interfaces, the chip bonding options are the same. Illustrated in Figure 9-1, they are: ¥ wirebond ¥ TAB (tape automated bonding) ¥ flip chip; either with a solder interface, a polymer adhesive or a welded joint Because of the parallel efforts in widely separated applications involving similar, but slightly dif- ferent variations of chip attach techniques, seemingly confusing names have historically evolved to describe some of the attach technologies. COG (chip on glass) refers to assembly of bare die onto LCD panels.
    [Show full text]
  • Wire Bonding Considerations Design Tips for Performance and Reliability
    THE b a c k - e n d PROCESS Wire Bonding Considerations Design Tips for Performance and Reliability BY VIVEK DIXIT, PH.D., HEIDI DAVIS, PH.D., AND MEL CLARK, Maxtek Components Corp. ire bonding ranks among Wire-bond Connections popular and dominant Avoid chip-to-chip connec- W interconnect technolo- tions – Unless electrical per- gies due to its reputation for versatili- formance demands it, wire ty, performance, and reliability. Wire- bonding directly between bond types can be described either by ICs should be avoided. Cre- the mechanism for creating the wire ating the stitch bond trans- bond or the type of bond. Wire-bond mits mechanical energy to mechanisms offer three different the pad, which could lead to methods for imparting the requisite micro-cracking in, or under, energy to attach a wire to the bond the pad metallization. Mi- site: thermocompression, ultrasonic, cro-cracks represent a po- FIGURE 1. Top row (l-r) – Examples of typical ball, stitch, and thermosonic. Two types of bond and wedge bonds formed using 0.001-in. Au wire. tential reliability risk; there- methods exist: the ball-stitch and the Bottom row (l-r) – examples of typical failures, including fore, intermediate bond pads wedge bonds (Table 1). cratering, poor heel stick, and heel cracking. should be designed into the substrate. Ball-stitch Bonding Don’t cross wires – Bond wires should not cross over one In ball bonding, a capacitive discharge spark melts the tip another, other die, or bond pads (Figure 3). Under external of the wire and the surface tension of the molten gold forms mechanical stresses, the unsupported loop of the wire bond the ball.
    [Show full text]
  • Heterogeneous Integration Technologies Based on Wafer Bonding and Wire Bonding for Micro and Nanosystems
    Heterogeneous Integration Technologies Based on Wafer Bonding and Wire Bonding for Micro and Nanosystems XIAOJING WANG Doctoral Thesis Stockholm, Sweden, 2019 Front cover pictures: Left: SEM image of an array of vertically assembled microchips that are electrically packaged by wire bonding. Right: Optical image of wafer bonded ultra-thin silicon caps of different sizes for wafer-level vacuum sealing. KTH Royal Institute of Technology School of Electrical Engineering TRITA-EECS-AVL-2019:65 and Computer Science ISBN 978-91-7873-280-7 Department of Micro and Nanosystems Akademisk avhandling som med tillstånd av Kungliga Tekniska högskolan framlägges till offentlig granskning för avläggande av teknologie doktorsexamen i elektroteknik och datavetenskap fredagen den 4:e oktober klockan 10:00 i Sal F3, Lindstedtsvägen 64, Stockholm. Thesis for the degree of Doctor of Philosophy in Electrical Engineering and Computer Science at KTH Royal Institute of Technology, Stockholm, Sweden. © Xiaojing Wang, September 2019 Tryck: Universitetsservice US AB, 2019 iii Abstract Heterogeneous integration realizes assembly and packaging of separately manufactured micro-components and novel functional nanomaterials onto the same substrate. It has been a key technology for advancing the discrete micro- and nano-electromechanical systems (MEMS/NEMS) devices and micro-electronic components towards cost-effective and space-efficient multi-functional units. However, challenges still remain, especially on scalable solutions to achieve heterogeneous integration using standard materials, processes, and tools. This thesis presents several integration and packaging methods that utilize conventional wafer bonding and wire bonding tools, to address scalable and high- throughput heterogeneous integration challenges for emerging applications. The first part of this thesis reports three large-scale packaging and integration technologies enabled by wafer bonding.
    [Show full text]
  • Characterization and Requirements for Cu-Cu Bonds for Three-Dimensional Integrated Circuits by Rajappa Tadepalli
    Characterization and Requirements for Cu-Cu Bonds for Three-Dimensional Integrated Circuits by Rajappa Tadepalli B.Tech., Indian Institute of Technology - Madras, India (2000) S.M., Massachusetts Institute of Technology (2002) Submitted to the Department of Materials Science and Engineering in partial fulfillment of the requirements for the degree of Doctor of Philosophy at the MASSACHUSETTS INSTITUTE OF TECHNOLOGY February 2007 © Massachusetts Institute of Technology 2007. All rights reserved. Author ................................................................................................................ Department of Materials Science and Engineering 6 November 2006 Certified by ........................................................................................................ Carl V. Thompson Stavros Salapatas Professor of Materials Science and Engineering Thesis Supervisor Accepted by ....................................................................................................... Samuel M. Allen POSCO Professor of Physical Metallurgy Chair, Departmental Committee on Graduate Students 2 Characterization and Requirements for Cu-Cu Bonds for Three-Dimensional Integrated Circuits by Rajappa Tadepalli Submitted to the Department of Materials Science and Engineering on 6 November 2006, in partial fulfillment of the requirements for the degree of Doctor of Philosophy Abstract Three-dimensional integrated circuit (3D IC) technology enables heterogeneous integration of devices fabricated from different technologies, and
    [Show full text]
  • Pdf [70] BE Semiconductor Industries N.V
    This is an accepted version of a paper published in Journal of Micromechanics and Microengineering. This paper has been peer-reviewed but does not include the final publisher proof-corrections or journal pagination. Citation for the published paper: Fischer, A., Korvink, J., Wallrabe, U., Roxhed, N., Stemme, G. et al. (2013) "Unconventional applications of wire bonding create opportunities for microsystem integration" Journal of Micromechanics and Microengineering, 23(8): 083001 Access to the published version may require subscription. Permanent link to this version: http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-124074 http://kth.diva-portal.org UNCONVENTIONAL APPLICATIONS OF WIRE BONDING CREATE OPPORTUNITIES FOR MICROSYSTEM INTEGRATION A. C. Fischer1, J. G. Korvink23, N. Roxhed1, G. Stemme1, U. Wallrabe2 and F. Niklaus1 1 Department of Micro and Nanosystems, KTH Royal Institute of Technology, Stockholm, Sweden 2 Department of Microsystems Engineering - IMTEK, University of Freiburg, Germany 3 Freiburg Institute for Advanced Studies - FRIAS, University of Freiburg, Germany E-mail: [email protected] Abstract. Automatic wire bonding is a highly mature, cost-efficient and broadly available back-end process, intended to create electrical interconnections in semiconductor chip packaging. Modern production wire bonding tools can bond wires with speeds of up to 30 bonds per second with placement accuracies of better than 2 µm, and the ability to form each wire individually into a desired shape. These features render wire bonding a versatile tool also for integrating wires in applications other than electrical interconnections. Wire bonding has been adapted and used to implement a variety of innovative microstructures. This paper reviews unconventional uses and applications of wire bonding that have been reported in the literature.
    [Show full text]
  • Bonding to the Chip Face
    Bonding to the Chip Face ‘Wire bonding’ is used throughout the microelectronics industry for interconnecting dice, substrates and output pins. Fine wires, generally of aluminium or gold 18–50µm in diameter, are attached using pressure and ultrasonic energy to form metallurgical bonds. Devices bonded with gold wire generally need additional thermal energy, and the bonding process is referred to as ‘thermosonic’ rather than ‘ultrasonic’. Although many alternative joining methods have been devised, the development of automated, high speed, high throughput equipment has maintained the position of wire bonding as the principal interconnect process. There are two main bond geometries: • Wedge bonding, most commonly used with aluminium wire, which has a stitch bond at both ends • Ball bonding, generally used with gold wire, where a ball bond is formed at one end and a ‘fish tail’ bond at the other, the capillary cutting through the wire to produce a single ‘tail-less’ bond. Wedge bonds Stitch bonds are formed at both ends of the interconnect by a combination of pressure and vibration. An ultrasonic transducer and ‘horn’ are designed to translate electrical energy into tool movement along the horn axis. As this energy softens the wire, freshly exposed metal in the wire comes in contact with the freshly exposed metal on the pad and a metallurgical bond is formed. The bonding dwell time is typically 20ms for an automatic bonder. In Figure 1, which is an SEM photograph of a typical ultrasonic wedge bond, distortion of the wire is visible, but there is no evidence of a weld ‘fillet’. This contrasts with soldering operations.
    [Show full text]
  • Lecture 24 Wafer Bonding and Packaging
    Wafer-to-Wafer Bonding and Packaging Dr. Thara Srinivasan Lecture 25 EE C245 U. Srinivasan © Picture credit: Radant MEMS Lecture Outline • Reading • Senturia, S., Chapter 17, “Packaging.” • Schmidt, M. A. “Wafer-to-Wafer Bonding for Microstructure Formation,” pp. 1575-1585. • Tummala, R.R. “Fundamentals of Microsystems Packaging,” pp. 556-66. • Today’s Lecture • MEMS Packaging: Why a Whole Lecture? • Wafer Bonding Methods for MEMS • Bonding Tools and Characterization • Packaging: Die-Level, Wafer-Level… EE C245 2 U. Srinivasan © 1 MEMS and the Package • Packaging electronics • Provide electrical interconnects, protect electronics • Dice up wafer, assemble into ceramic/plastic package • Single package, many chips • Packaging MEMS • Provide electrical (and other, i.e., fluidic, optical) interconnects, protect micromechanical elements, interface with outside environment • Dicing cannot be done after release unless precautions taken • Environment inside package important • Package should not mechanically stress MEMS • Single chip, many packages • Packaging, test and calibration important to MEMS design EE C245 3 U. Srinivasan © Current MEMS Packages Die Level Wafer Level Wafer bonded package with glass frit seal and lateral feedthroughs (sealed MEMS is then placed into ceramic package) Cronos Relay Die level release and Motorola CMOS ceramic package Accelerometer region Bosch Gyroscope MEMS region BSAC/Sandia Partial Hexsil cap assembled Wafer bonded package EE C245 onto Sandia iMEMS chip with glass frit seal and using wafer-to-wafer transfer4 U. Srinivasan © lateral feedthroughs 2 Lecture Outline • MEMS Packaging • Wafer Bonding Methods for MEMS • Bonding tools and characterization • Packaging: die-level, wafer-level… EE C245 5 U. Srinivasan © Wafer Bonding in MEMS • Wafer-level packaging • MEMS device construction • Sealed structures, i.e., pressure sensors and fluidic channels • Multiwafer structures, i.e., µTAS, microturbines, optical devices, inkjet print heads Motorola pressure sensor EE C245 MIT microturbine 6 U.
    [Show full text]
  • A Corrosion Study of Ag–Al Intermetallic Compounds in Chlorine- Containing Epoxy Molding Compounds
    UC Irvine UC Irvine Previously Published Works Title A corrosion study of Ag-Al intermetallic compounds in chlorinecontaining epoxy molding compounds Permalink https://escholarship.org/uc/item/78b4m6sh Journal JOURNAL OF MATERIALS SCIENCE-MATERIALS IN ELECTRONICS, 28(20) ISSN 0957-4522 Authors Fu, Shao-Wei Lee, Chin C Publication Date 2017-10-01 DOI 10.1007/s10854-017-7467-4 Peer reviewed eScholarship.org Powered by the California Digital Library University of California J Mater Sci: Mater Electron DOI 10.1007/s10854-017-7467-4 A corrosion study of Ag–Al intermetallic compounds in chlorine- containing epoxy molding compounds Shao-Wei Fu1,2 · Chin C. Lee1,2 Received: 13 April 2017 / Accepted: 3 July 2017 © Springer Science+Business Media, LLC 2017 Abstract Typical epoxy molding compounds (EMC) EMC. New information obtained in this research can help contain chlorine ions that cause silver wire-bond fail- the search of new processes and techniques to counter or ures under highly accelerated temperature/humidity stress reduce the chlorine-induced corrosion of devices and pack- test (HAST). To understand the corrosion mechanisms, ages. The corrosion test method presented may possibly experiments were designed to emulate the HAST environ- become an acceptable test standard to consider. ment and conditions and performed. Specifically, Ag–Al joints, Ag, Al, Ag3Al, and Ag2Al samples were encap- sulated in chlorine-containing EMC, respectively, and 1 Introduction went through HAST. EMC with high chlorine content (1000 ppm) was chosen to accelerate the corrosion rate and Wire bonding technique has been extensively used to inter- shorten experiment time. The experimental results show connect chips and substrates of microelectronic packages that chlorine-induced corrosion occurs only on Ag 3Al and [1–3].
    [Show full text]