Overview of CPU Power Consumption and Management in Smartphones
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Overview of CPU Power Consumption and Management in Smartphones Prof. Sasu Tarkoma University of Helsinki, Aalto University, Helsinki Institute for Information Technology Contents • Modern smartphone SoC and CPUs – The CPU: power states – Power management basics • Smartphone solutions – Linux CPU Frequency subsystem – Power models • Intra-device task offloading – Sensor hub – Heterogeneous multiprocessing • Computation offloading Smartphones • Smartphones have become hubs for applications and connecting with the Internet • Cloud has emerged as a backend for mobile applications • Mobile data and WiFi are the dominant protocols for connecting with Internet resources • The next generation solutions are addressing limitations of the current smartphones – Coordination of resource usage – Offloading in its many forms – Heterogeneous environment and the emergence of IoT / M2M / wearables Observations • Smartphone and mobile device hardware and software evolve rapidly • Multiple wireless protocols • Heterogeneous computing over multiple cores – Dedicated subsystems (sensor hubs) – Increasing number of sensing subsystems – Always-on sensing • Battery technology has not kept pace with the development • Software is not, in many cases, optimized • Difficult to balance between local versus distributed processing • Difficult to control traffic across interfaces Mobile Evolution 1995 2000 2005 2010 2015 Processor Single Single Single Dual-core Quad-core and beyond, auxiliary processors, sensor hubs Cellular 2G 2.5-3G 3.5G Transition 4G generation toward 4G Standard GSM GPRS HSPA HSPA, LTE LTE, LTE-A Downlink (Mb/ 0.01 0.1 1 10 100 s) Display pixels 4 16 64 256 1024 (x1000) Communicatio - - WiFi, WiFi, WiFi, Bluetooth LE, ns modules Bluetooth Bluetooth RFID Battery 1 2 3 4 5 capacity (Wh) Software (MB) 0.1 1 10 100 1000 Example Smartphone SoC Modem Subsystem Multicore Subsystem Multimedia Subsystem LTE Adreno World KRAIT CPU KRAIT CPU GPU Modem Audio, GPS,Wi-Fi, Video HW, BT,FM Accelerator L1 Cache L1 Cache s DSP DSP DSP L2 Cache Multim. Proc. Dual channel memory Snapdragon Adaptive Power Technologies Android Smartphone Power Profile (mW) 800 700 600 500 400 300 200 100 0 28 Energy and Power Primer 2.3 Power Computation Energy can be saved on multiple levels in the hardware and software architecture. On circuit and transistor levels energy can be saved by changing the voltage and frequency of the circuit. The total power of CMOS logic circuits are determined by the clock rate, the supply voltage, and the capacitances of the transistors. The larger the capacitance, the more the transistors need to work to change the output charge. The higher the source voltage, the more the output has to change. The higher the clock frequency, the more power is wasted during switching. The 28 Energy and Power Primer capacitances are determined during chip design; however, the clock rate and voltage can be varied at runtime. By varying clock rate and supply voltage, it is possible to obtain linear and quadratic improvements, respectively. 2.3 PowerThe overall Computation power consumption is given by Energy can be saved on multipleP = levelsPswitch in the+ P hardwarestatic, and software architecture.(2.6) On circuit and transistor levels energy can be saved by changing the voltage and where P is the dynamic switching power and P is the static leakage frequencyswitch of the circuit. The total power of CMOS logicstatic circuits are determined power. The formula does not include the lost power due to short circuit due to by the clock rate, the supply voltage, and the capacitances of the transistors. a transistor switching that is a relatively small term in the dynamic switching The larger the capacitance, the more the transistors need to work to change the power [4]. output charge. The higherCPU the source Total voltage, Power the more the output has to change. The CPU consists of transistors that can switch states every clock cycle. Each The higher the clock frequency, the more power is wasted during switching. The switch of states between a complementary pair of transistors results in wasted capacitances are determined during chip design; however, the clock rate and power. Typically, most of the gates in the CPU switch states every clock cycle. voltage can• The be total varied power at runtime. of CMOS By varyinglogic circuits clock rateare anddetermined supply voltage, it is Thus the higher the clock rate, the higher the amount of wasted energy. In possible toby obtain the clock linear rate, and the quadratic supply improvements, voltage, and the respectively. addition tocapacitances the clock rate, of also the thetransistors voltage a↵ects the power consumption of the CPU.The overall power consumption is given by – Switching power and static power: The dynamic switching loss is the power used by switching of the state of the P = P + P , (2.6) transistors. This loss can be determinedswitch by usingstatic the formula • Dynamic switching loss is given by: where Pswitch is the dynamic switching power2 and Pstatic is the static leakage Pswitch = ↵ C V f, (2.7) power. The formula does not include the⇥ lost⇥ power⇥ due to short circuit due to By varying clock rate and supply voltage, it is possible a transistor• switching that is a relatively small term in the dynamic switching where ↵ denoteto obtain the linear switching and activity, quadraticC isimprovements the average capacitance of the tran- powersistors, [4].V is the supply voltage and f is the clock frequency [5]. The power consumptionThe CPU consists is proportional of transistors to the that product can switch of the states square every of the clock supply cycle. voltage Each switchand the of frequency. states between The power a complementary consumption pair decreases of transistors quadratically results with in thewasted re- power.duction Typically, of the voltage. most The of the formula gates in is not the exactCPU switch for modern states chips, every because clock cycle. also Thusmemory the circuits higher and the static clock leakage rate, the current higher need the to amount be taken of into wasted account. energy. In additionThe clock to the rate clock and rate, the supply also the voltage voltage are a parameters↵ects the power for the consumption energy optimiza- of the CPU.tion of the CPU [6, 7]. Major energy savings can be gained by adjusting the supplyThe dynamic voltage and switching the clock loss rate is the either power one used or both by switching of them atof the the state same of time. the transistors.Indeed, dynamic This loss voltage can scaling be determined is widely by used using to the improve formula power consumption of battery powered devices. Both low voltage and lowered clock frequencies are 2 used to minimize power consumptionPswitch = ↵ of componentsC V f, such as CPUs and DSPs.(2.7) ⇥ ⇥ ⇥ Operating frequency has an approximately linear relationship with the oper- where ↵ denote the switching activity, C is the average capacitance of the tran- sistors, V is the supply voltage and f is the clock frequency [5]. The power consumption is proportional to the product of the square of the supply voltage and the frequency. The power consumption decreases quadratically with the re- duction of the voltage. The formula is not exact for modern chips, because also memory circuits and static leakage current need to be taken into account. The clock rate and the supply voltage are parameters for the energy optimiza- tion of the CPU [6, 7]. Major energy savings can be gained by adjusting the supply voltage and the clock rate either one or both of them at the same time. Indeed, dynamic voltage scaling is widely used to improve power consumption of battery powered devices. Both low voltage and lowered clock frequencies are used to minimize power consumption of components such as CPUs and DSPs. Operating frequency has an approximately linear relationship with the oper- 2.3 Power2.3 Computation Power Computation29 29 Power#(W)#Power#(W)# Process#running#with#Process#running#with# frequency#f#frequency#f# Process#with#running#frequency#f/2# Process#with#running#frequency#f/2# Time# Time# Figure 2.2 Example of frequency, time and energy consumption Figure 2.2 Example of frequency, time and energy consumption ating voltage given by the following equation [4]: ating voltage given by the following equation [4]: V = β + β f , (2.8) CPU Power Savingnorm 1 2 ⇥ norm Vnorm = β1 + β2 fnorm, (2.8) where β = V /V and β =1⇥ β . V is the threshold voltage at which a 1 th max 2 − 1 th where β = Vtransistor/V and conductsβ =1 and beginsβ . V tois switch. the threshold voltage at which a 1 th max 2 − 1 th • Runningtransistor a task conducts atFigure a and slower 2.2 begins illustrates speed to switch. the relationships saves energy; of the operating frequency, process com- however,Figure it will 2.2 illustrates pletionlake time,longer the and relationships energyto execute consumption. of the operatingthe The task process frequency, thus is executed process on com- two di↵erent pletion time, andsystems energy at di consumption.↵erent voltage The and process frequency is executed levels. The on top two process di↵erent runs at high affectingsystems the at performance di↵frequencyerent voltage and is and completed frequency fast. levels. The lower The top process process runs runs at a at halved high processor •Dynamicfrequency voltage andfrequency is and completed frequency and supply fast. The voltage scaling lower and process takes favor much runs longer at a halved to complete. processor The lower fre- frequency andquency supply and voltage supply and voltage takes lead much to longersmaller to energy complete. consumption The lower [7]. fre-Suppose that parallelismquency andand supplythe having new voltage frequency multiple lead istof/ smaller2, voltage/frequency then energy from Equation consumption 2.7 we [7]. obtain Suppose the newthat switching scaledthe cores new frequency executingpower is f/2, tasks.