Intel® 7500 Chipset Datasheet Contents
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Intel® 7500 Chipset Datasheet March 2010 Reference Number: 322827-001 THIS SPECIFICATION IS PROVIDED “AS IS” WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE. Intel disclaims all liability, including liability for infringement of any proprietary rights, relating to use of information in this specification. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. 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Copyright © 2010, Intel Corporation. 2 Intel® 7500 Chipset Datasheet Contents 1Introduction............................................................................................................ 19 1.1 System Configuration Overview........................................................................... 19 1.2 Feature Summary ............................................................................................. 19 1.2.1 Features By Segment based on PCI Express Ports....................................... 20 1.2.2 Non-Legacy IOH..................................................................................... 21 1.2.3 Intel® QuickPath Interconnect Features .................................................... 21 1.2.4 PCI Express* Features ............................................................................ 21 1.2.5 Enterprise South Bridge Interface (ESI) Features........................................ 21 1.2.6 Controller Link (CL) ................................................................................ 22 1.2.7 Intel® I/OAT Gen3 ................................................................................. 22 1.2.8 Intel® Virtualization Technology for Directed I/O (Intel® VT-d), Second Revision................................................................ 22 1.2.9 Reliability, Availability, Serviceability (RAS) Features................................... 22 1.2.10 Power Management Support .................................................................... 23 1.2.11 Security ................................................................................................ 23 1.2.12 Other.................................................................................................... 23 1.3 Terminology ..................................................................................................... 23 1.4 Related Documents ........................................................................................... 26 2 Platform Topology ................................................................................................... 27 2.1 Introduction ..................................................................................................... 27 2.2 IOH Supported Topologies .................................................................................. 27 2.2.1 Platform Topologies ................................................................................ 27 2.3 I/O Sub-System ................................................................................................ 30 3Interfaces................................................................................................................ 33 3.1 Introduction ..................................................................................................... 33 3.2 Intel® QuickPath Interconnect ............................................................................ 33 3.2.1 Physical Layer........................................................................................ 33 3.2.2 Link Layer ............................................................................................. 35 3.2.3 Routing Layer ........................................................................................ 35 3.2.4 Protocol Layer........................................................................................ 35 3.3 PCI Express* Interface....................................................................................... 38 3.3.1 Gen1/Gen2 Support................................................................................ 38 3.3.2 PCI Express* Link Characteristics - Link Training, Bifurcation, and Lane Reversal Support ..................................................... 38 3.3.3 Degraded Mode...................................................................................... 39 3.3.4 Lane Reversal ........................................................................................ 40 3.3.5 Form-Factor Support .............................................................................. 40 3.3.6 IOH Performance Policies......................................................................... 40 3.3.7 Address Translation Caching (ATC) ........................................................... 42 3.3.8 PCI Express* RAS .................................................................................. 42 3.3.9 Power Management ................................................................................ 43 3.4 Enterprise South Bridge Interface (ESI) ............................................................... 43 3.4.1 Interface Speed and Bandwidth................................................................ 43 3.4.2 Supported Widths................................................................................... 43 3.4.3 Performance Policies on ESI..................................................................... 44 3.4.4 Error Handling ....................................................................................... 44 3.5 Reduced Media Independent Interface (RMII)........................................................ 44 3.6 Control Link (CLink) Interface ............................................................................. 44 3.7 System Management Bus (SMBus) ...................................................................... 44 3.7.1 SMBus Physical Layer ............................................................................. 45 3.7.2 SMBus Supported Transactions ................................................................ 45 3.7.3 Addressing ............................................................................................ 46 389924Intel® 7500 Chipset Datasheet 3 3.7.4 SMBus Initiated Southbound Configuration Cycles .......................................47 3.7.5 SMBus Error Handling..............................................................................48 3.7.6