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Imm Tps 12.Pdf Intel® Management Module Technical Product Specification Revision 1.1 October, 2006 Enterprise Platforms and Services Division - Marketing Revision History Intel® Management Module Revision History Date Revision Modifications Number March 2005 0.7 Initial release. April 2005 0.9 Preliminary draft release June 2005 1.0 Released version October 2006 1.1 Updated Section 5.6, SNMP Disclaimers Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. This document contains information on products in the design phase of development. Do not finalize a design with this information. Revised information will be published when the product is available. Verify with your local sales office that you have the latest datasheet before finalizing a design. The Intel® Management Module may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Intel, Pentium, Itanium, and Xeon are trademarks or registered trademarks of Intel Corporation. *Other brands and names may be claimed as the property of others. Copyright © Intel Corporation 2006. All rights reserved. ii Revision 1.1 Intel® Management Module Table of Contents Table of Contents 1. Introduction ........................................................................................................................ 15 1.1 Chapter Outline...................................................................................................... 15 1.2 Intel® Management Module Use Disclaimer ......................................................... 15 2. Intel® Management Module Overview............................................................................... 16 2.1 Management Module SKU Availability................................................................... 16 2.2 Intel® Management Module Hardware Feature Set ............................................... 16 3. Board Architecture.............................................................................................................19 3.1 Intel® Management Module Installation and Configuration.................................... 19 3.2 System Overview of Baseboard Management Controller (BMC)........................... 19 3.3 Connectors and Jumper Blocks............................................................................. 21 3.3.1 Intel® Management Module Connector .................................................................. 21 3.3.2 Generic Communications Module (GCM) Interface............................................... 24 3.3.3 Jumper Block Definition ......................................................................................... 25 3.4 Physical Dimensions.............................................................................................. 26 3.5 External Interfaces to Intel® Management Module BMC........................................ 27 3.5.1 Other Interface Support ......................................................................................... 27 3.6 5V Standby Operation ........................................................................................... 28 4. Professional Edition Firmware.......................................................................................... 29 4.1 Platform Determination .......................................................................................... 29 4.1.1 Platform Mismatch Detection................................................................................. 29 4.2 Power System........................................................................................................ 30 4.2.1 Power Supply Interface Signals............................................................................. 30 4.2.2 Power-up Sequence .............................................................................................. 31 4.2.3 Power-down Sequence.......................................................................................... 31 4.2.4 Power Control Sources.......................................................................................... 32 4.2.5 Manual Power Control ........................................................................................... 33 4.2.6 Power State Retention........................................................................................... 34 4.2.7 AC Power Loss ...................................................................................................... 34 4.3 Advanced Configuration and Power Interface (ACPI) ........................................... 34 4.3.1 ACPI Power Control............................................................................................... 34 4.3.2 ACPI State Synchronization .................................................................................. 35 4.3.3 ACPI S1 Sleep Support ......................................................................................... 35 Revision 1.1 iii Table of Contents Intel® Management Module 4.3.4 ACPI S4 Sleep Support ......................................................................................... 35 4.3.5 ACPI Power State Notify........................................................................................ 35 4.4 System Reset Control............................................................................................ 36 4.4.1 Reset Signal Output............................................................................................... 36 4.4.2 Reset Control Sources........................................................................................... 36 4.4.3 Front Panel System Reset..................................................................................... 36 4.4.4 Warm Boot............................................................................................................. 36 4.4.5 BMC Command to Cause System Reset............................................................... 37 4.4.6 Watchdog Timer Expiration ................................................................................... 37 4.4.7 FRB3 Failure.......................................................................................................... 37 4.5 BMC Reset Control................................................................................................ 37 4.5.1 BMC Exits Firmware Update Mode........................................................................ 37 4.6 System Initialization ............................................................................................... 37 4.6.1 Processor Temperature and Voltage Threshold Setting........................................ 37 4.6.2 Fault Resilient Booting (FRB) ................................................................................ 38 4.6.3 Boot Control Support ............................................................................................. 41 4.7 Integrated Front Panel User Interface ................................................................... 41 4.7.1 Chassis ID LED ..................................................................................................... 41 4.7.2 Front Panel / Chassis Inputs.................................................................................. 42 4.7.3 Chassis Intrusion ................................................................................................... 42 4.7.4 Diagnostic Interrupt (Front Panel NMI) .................................................................. 42 4.7.5 CMOS Clearing...................................................................................................... 43 4.7.6 Secure Mode Operation......................................................................................... 43 4.7.7 Set Fault Indication Command .............................................................................. 44 4.8 Private Management I2C Buses............................................................................. 44 4.9 Watchdog Timer .................................................................................................... 45 4.10 System Event Log (SEL) ....................................................................................... 45 4.10.1 Servicing Events .................................................................................................... 45 4.10.2 SEL Entry Deletion ................................................................................................ 45 4.10.3 SEL Erasure .........................................................................................................
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