Logic Circuits with Carbon Nanotube Transistors
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R EPORTS general, p-Si NWs grown with a higher dopant ratio 24. The OR and AND gates were assembled by using p-n 26. J. I. Pankov, T. D. Moustakas, Gallium Nitride (GaN) I ϭ (SiH4:B2H6 1000:1) have lower resistance and junctions (diode logic) and do not exhibit voltage gain; (Academic Press, San Diego, 1998), pp. 259Ð265. smaller on/off ratios of ϳ103; those synthesized with however, they would show gain if implemented by 27. N. J. Watkins, G. W. Wicks, Yongli Gao, Appl. Phys. a lower dopant ratio (6000:1) have higher resistance using cNW-FETs. For example, logic OR can be imple- Lett. 75, 2602 (1999). ϳ 4 5 and larger on/off ratios of 10 to 10 . In addition, mented with the NOR gate by reversing the 5-V bias 28. We thank H. Park for helpful discussion. C.M.L. ac- the carrier mobility typically varies from 30 to 200 and ground connections to the p-Si NW. The AND knowledges support of this work by the Office of cm2/V-s, depending on doping. function could also be implemented by using cNW-FETs Naval Research and the Defense Advanced Projects in parallel (versus series for OR). In addition, we note 22. S. M. Sze, Semiconductor Devices, Physics and Tech- Research Agency. nology ( Wiley, New York, 1985), pp. 208Ð210. that both p- and n-channel transistors are possible and 23. P. Horowitz, W. Hill, The Art of Electronics (Cam- would enable reduced power dissipation. bridge Univ. Press, Cambridge, 1989). 25. Y. Huang, X. Duan & C. M. Lieber, unpublished results. 12 September 2001; accepted 16 October 2001 ter of about 1 nm and that are situated on top of Logic Circuits with Carbon the Al gate wires. Their coordinates are regis- tered with respect to alignment markers. Finally, Nanotube Transistors contact electrodes and interconnect wires are fabricated with electron-beam lithography by Adrian Bachtold,* Peter Hadley, Takeshi Nakanishi, Cees Dekker† evaporating Au directly on the nanotube without an adhesion layer. We demonstrate logic circuits with field-effect transistors based on single Very strong doping of the nanotube channel carbon nanotubes. Our device layout features local gates that provide excellent can be achieved with this layout (Fig. 2A) (20). capacitive coupling between the gate and nanotube, enabling strong electro- Starting from a negative gate voltage Vg, the static doping of the nanotube from p-doping to n-doping and the study of the current I first decreases, then becomes immea- nonconventional long-range screening of charge along the one-dimensional surably small, and finally increases again. This nanotubes. The transistors show favorable device characteristics such as high indicates that Vg shifts the Fermi level succes- gain (Ͼ10), a large on-off ratio (Ͼ105), and room-temperature operation. sively from the valence band (accumulation re- Importantly, the local-gate layout allows for integration of multiple devices on gime) to the gap (depletion), and finally to the a single chip. Indeed, we demonstrate one-, two-, and three-transistor circuits conduction band (inversion) of the semicon- that exhibit a range of digital logic operations, such as an inverter, a logic NOR, ducting nanotube. The nearby Al gate thus a static random-access memory cell, and an ac ring oscillator. makes it possible to change the doping of the nanotube over the full range from the p-tothe The anticipated limits to the further miniatur- oxidized Si wafer (6, 7, 9), the tip of an atomic n-doped regime. ization of microelectronics have led to in- force microscope (10–12), a second nanotube Our nanotube transistors can be classified as tense research directed toward the develop- (13), an ionic solution (14), or a capping Al enhancement-mode p-type FETs (21), because a ment of molecular electronics (1). The use of film (15). The layouts of these devices do not strong modulation of the current through the single-wall carbon nanotubes has stimulated allow integration of multiply connected devices nanotube FET is possible when a small negative these efforts, because these molecules exhibit (16). For example, the most popular nanotube- gate voltage is applied. The current versus bias a range of suitable properties for nanoelec- transistor layout uses a backgate, which applies voltage Vsd characteristics (Fig. 3) are typical for tronics. Various basic single-nanotube com- the same gate voltage to all transistors on the FETs (22). From the data in Figs. 2 and 3, we ponents have recently been demonstrated, chip. In contrast, our gate consists of a micro- can extract a transconductance of our nanotube such as molecular wires, diodes, field-effect fabricated Al wire with a well-insulating native transistors of 0.3 S and a lower limit of the 5 transistors, and single-electron transistors (2– Al2O3 layer (17), which lies beneath a semi- on/off ratio of at least 10 . The maximum cur- 8). The next challenge in the development of conducting nanotube that is electrically contact- rent at which the nanotube transistor can operate molecular electronics is to go beyond single- ed to two Au electrodes (Fig. 1, A and B). In is on the order of 100 nA and the on-resistance ϭ ϭ molecule components and integrate such de- this configuration, the Al2O3 thickness of a few is 26 megaohms for Vsd –1.3 V and Vg –1.3 vices onto a chip to demonstrate digital logic nanometers is much shorter than the separation V. operations. Here, we report such logic cir- between the contact electrodes (ϳ100 nm), en- For any further development of operational cuits composed of single-nanotube field-ef- abling an excellent capacitive coupling between logic circuits, a gain (Ͼ1) at large bias voltage fect transistors. In addition to the realization the gate and the nanotube. Moreover, different is a crucial requirement, because the output of of logic circuits, our new device layout also local Al gates can easily be patterned such that one logic structure must be able to drive the enables substantial electrostatic doping for each one addresses a different nanotube transis- input of the next logic structure. The output modest gate voltages, which allows us to tor. This layout thus allows the integration of typically has to provide a voltage swing of study the nonconventional screening of multiple nanotube field-effect transistors about 1 V. Figure 3 indicates that in our tran- charge along the one-dimensional nanotubes. (FETs) on the same chip (Fig. 1C). sistors, a change in the output by more than 1 V Our nanotube transistors have a local gate Our nanotube circuits are realized in a three- occurs when the input voltage is changed by 0.1 that is insulated from the nanotube by a gate step process. First, Al gates are patterned using V. This indicates a large-signal gain Ͼ10. A oxide layer of only a few nanometers thickness. electron beam lithography (18) on an oxidized large gain combined with a large output In previous circuits, the gate consisted of an Si wafer. The insulating layer consists of the swing can be obtained because the gate is so native oxide that grows by exposing the sample close to the nanotube. Our technique allows to air. The precise thickness of this layer is for a much larger gain than has been achieved Department of Applied Physics, Delft University of Tech- difficult to determine, but is on the order of a with thick gate oxides or planar gates used in nology, Lorentzweg 1, 2628 CJ Delft, Netherlands. few nanometers (19). Second, single-wall car- previous nanotube FETs (6, 7, 9, 23). *Present address: Laboratoire de Physique de la Ma- bon nanotubes produced by laser ablation are A major point of our report is that small « tie`re Condense«e, Ecole Normale Superieure, 24 Rue dispersed on the wafer from a dichloroethane circuits combining our nanotube transistors can Lhomond, 75005 Paris, France. †To whom correspondence should be addressed. E- suspension. With an atomic force microscope, be used for a variety of logic elements. Here, we mail: [email protected] those nanotubes are selected that have a diame- describe our demonstration of an inverter, a www.sciencemag.org SCIENCE VOL 294 9 NOVEMBER 2001 1317 R EPORTS -7 A 100nm Al 10 -1.0 V 0 -8 10 -1.1 V SiO2 Au -1.2 V -9 -20 ) 10 (nA) nanotube A I ( I -10 10 -40 -11 Vg = -1.3 V 10 A -60 -12 -1 -0.5 0 10 -44-20 2 B Vsd (V) V Vg (V) sd Al2O3 I Fig. 3. Device characteristics of the nanotube nanotube 4 V transistor. Typical I-V curves measured at Au Al g sd room temperature for various values of Vg.In SiO2 2 the linear regime at small source-drain volt- ) ages, the current is proportional to Vsd.Inthe C Au µ saturation regime at higher source-drain Al 1 m atom / e voltages (that is, when V becomes more 0 sd -2 negative than Vg Ð Vt), the current through 10 ( the transistor changes more gradually. For a e g constant Vsd in the saturation regime, I(Vg) -2 has an approximately parabolic dependence har 2 C ϳ I (Vg Ð Vt) , as is typical for MOSFETs. The B data are for a different transistor than in Fig. -4 2. Lines are guides to the eye. Large gain Fig. 1. Device layout. (A) Height image of a 0 20 40 60 (Ͼ10) is obtained. single-nanotube transistor, acquired with an Distance from the interface (nm) atomic force microscope. (B) Schematic side Fig. 2. Strong doping and weak screening of view of the device.