USOO946O782B2

(12) United States Patent (10) Patent No.: US 9,460,782 B2 Seol et al. (45) Date of Patent: Oct. 4, 2016

(54) METHOD OF OPERATING MEMORY (56) References Cited CONTROLLER AND DEVICES INCLUDING MEMORY CONTROLLER U.S. PATENT DOCUMENTS 8,050,086 B2 11/2011 Shalvi et al. (71) Applicant: SAMSUNGELECTRONICS CO., 8,085,605 B2 12/2011 Yang et al. LTD., Suwon-si, Gyeonggi-do (KR) 2005.0089121 A1* 4/2005 Tsai ...... HO3M13/41 375,341 (72) Inventors: Chang Kyu Seol, Osan-si (KR); Jun 2011 0145487 A1 6/2011 Haratsch et al. Jin Kong, Yongin-si (KR); Hong Rak 2011 (0289.376 A1 1 1/2011 Maccarrone et al. 2012,0005409 A1 1/2012 Yang Son, Anyang-Si (KR) 2012/0066436 A1 3/2012 Yang (73) Assignee: Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do (KR) FOREIGN PATENT DOCUMENTS JP 2011504276 A 2, 2011 (*) Notice: Subject to any disclaimer, the term of this KR 2011.0128852. A 11/2011 patent is extended or adjusted under 35 KR 2012O061214 A 6, 2012 U.S.C. 154(b) by 274 days. * cited by examiner (21) Appl. No.: 14/205,496 Primary Examiner — Idriss N Alrobaye (22) Filed: Mar. 12, 2014 Assistant Examiner — Dayton Lewis-Taylor (65) Prior Publication (74) Attorney, Agent, or Firm — Volentine & Whitt, US 2014/0281293 A1 Sep. 18, 2014 PLLC

(30) Foreign Application Priority Data (57) ABSTRACT Mar. 15, 2013 (KR) ...... 10-2013-0O28O21 A method of operating a memory controller includes receiv ing a first data sequence and generating a coset representa (51) Int. Cl. tive sequence that can be divided into m- strings, where G06F 2/02 (2006.01) “m' is a natural number of at least 2; performing a first XOR GIC II/56 (2006.01) operation on each of the m-bit strings in the coset represen GITC 7/10 (2006.01) tative sequence and binary ; calculating all possible GI IC 16/34 (2006.01) branch metrics according to a result of the first XOR (52) U.S. Cl. operation; determining a Survivor path sequence based on CPC ...... GIIC II/5642 (2013.01); GIIC 7/1006 the all possible branch metrics; and performing a second (2013.01); GIIC II/5628 (2013.01); G1 IC XOR operation on the coset representative sequence and the 16/3418 (2013.01); G1 IC 2211/5632 (2013.01) Survivor path sequence and generating an output sequence. (58) Field of Classification Search None See application file for complete search history. 12 Claims, 19 Drawing Sheets

100

BL1BL2 BLy Memory Controller Memory Device U.S. Patent Oct. 4, 2016 Sheet 1 of 19 US 9,460,782 B2

FIG. 1

EnCOder

BL1 BL2 BLy Memory Controller Memory Device U.S. Patent Oct. 4, 2016 Sheet 2 of 19 US 9,460,782 B2

FIG 2

State

Normal (conventional)

E P1 P2 P3 Voltage margin LSB 1 O (obtained by state shaping) MSB 1 () O (9) U.S. Patent Oct. 4, 2016 Sheet 3 of 19 US 9,460,782 B2

FIG 3

State shaping (reduce bit 1 at MSB/LSB page, reduced bit 0 at CSB page

------Normal (conventional)

Threshold Voltage

Voltage margin (obtained by State shaping) U.S. Patent Oct. 4, 2016 Sheet 4 of 19 US 9,460,782 B2

FIG 4

40 55 Inverse DS1 Syndrome Former

Viterb SEL DeCOder U.S. Patent Oct. 4, 2016 Sheet 5 Of 19 US 9,460,782 B2

FIG 5

RS ... I mbit mbit mbit m bit U.S. Patent Oct. 4, 2016 Sheet 6 of 19 US 9,460,782 B2

FIG. 6

40

O- - - y4) ^ x(3)--GD-CD/S y3

======x2) y2) (m-1) bit - 40–2 m bit

X1 ------y1

- 40-3

XO ------yO -

r- 40-4 U.S. Patent Oct. 4, 2016 Sheet 7 Of 19 US 9,460,782 B2

FIG 7

40 r

------y40 CD-CD y30

1 x2 -(D-CD-I-y(2)

----E.------1x1) -(D-CDI-y(1)

======OXO CD-CD yO 0 U.S. Patent Oct. 4, 2016 Sheet 8 of 19 US 9,460,782 B2

FIG. 8

1x3)

1 x2

OX1

1 x0 U.S. Patent Oct. 4, 2016 Sheet 9 Of 19 US 9,460,782 B2

FIG 9

1x3)

0x2)

1x1)

OXO U.S. Patent Oct. 4, 2016 Sheet 10 of 19 US 9,460,782 B2

A=OOOOO

B=11111

C=10101

D=01010 U.S. Patent Oct. 4, 2016 Sheet 11 of 19 US 9,460,782 B2 U.S. Patent Oct. 4, 2016 Sheet 12 of 19 US 9,460,782 B2

FIG. 12

70 61 Syndrome Former ose Selector

PN U.S. Patent Oct. 4, 2016 Sheet 13 Of 19 US 9,460,782 B2

FIG 13

U.S. Patent Oct. 4, 2016 Sheet 14 of 19 US 9,460,782 B2

FIG 14.

70'

U.S. Patent Oct. 4, 2016 Sheet 15 Of 19 US 9,460,782 B2

FIG 15

U.S. Patent Oct. 4, 2016 Sheet 16 of 19 US 9,460,782 B2

FIG 16

GENERATE COSET REPRESENTATIVE SEQUENCE S10

CALCULATE ALL POSSIBLE BRANCH METRICS -S2O

DETERMINE SURVIVOR PATH SEQUENCE S30

OUTPUT OUTPUT SEQUENCE S40

MAP SECOND DATA SEQUENCE AND OUTPUT SEQUENCE TO PROGRAMMED STATES S50

PERFORM PROGRAM OPERATION ACCORDING TO THE MAPPED PROGRAMMED STATES S60 U.S. Patent Oct. 4, 2016 Sheet 17 Of 19 US 9,460,782 B2

FIG. 17

1700

1701 1720

Display

RADIO TRANSCEIVER 1710

Processor

1730 Memory 1760 Controller Input Device KO U.S. Patent Oct. 4, 2016 Sheet 18 of 19 US 9,460,782 B2

FIG. 18

1820 1810

HOST 1821 1823 1811 HOSt Card ProCeSSOr Interface Interface U.S. Patent Oct. 4, 2016 Sheet 19 Of 19 US 9,460,782 B2

~~~~096|| US 9,460,782 B2 1. 2 METHOD OF OPERATING MEMORY The all possible branch metrics may be each calculated as CONTROLLER AND DEVICES INCLUDING the Sum of parameters. The parameters may be defined MEMORY CONTROLLER according to a selection bit. When the selection bit is “1” and the result of the first CROSS-REFERENCE TO RELATED XOR operation is bit “0”, one of the parameters correspond APPLICATIONS ing to the bit “0” may be “0”. When the selection bit is “1” and the result of the first XOR operation is bit “1”, one of This application claims priority under 35 U.S.C. S 119(a) the parameters corresponding to the bit “1” may be “1”. from Korean Patent Application No. 10-2013-0028021 filed The calculating the all possible branch metrics may on Mar. 15, 2013, the subject matter of which is hereby 10 include calculating the all possible branch metrics using a incorporated by reference. first programmed State sequence, which is determined based on the result of the first XOR operation and a second data BACKGROUND sequence to be stored in a first word line together with the output sequence, and a second programmed State sequence Embodiments of the inventive concept relate to memory 15 systems and memory controllers. Embodiments of the determined based on page data bits that have been stored in inventive concept relate to methods of operating a memory a second word line. controller that control the definition or shaping of a data When a programmed State corresponding to a k-th bit line pattern. in the first programmed State sequence is an erased state and A non- device, such as a NAND flash a programmed State corresponding to the k-th bit line in the memory device, includes a great number of memory cells. second programmed State sequence is a highest programmed With increased integration density made possible by emerg state, a parameter corresponding to the k-th bit line among ing fabrication technologies, the separation distance the parameters may be “1” and the other parameters may be between adjacent (and nearby) memory cells has decreased “0”. The parameters may have different values according to markedly. The increasingly close proximity of individual 25 the first programmed State sequence and the second pro memory cells, together with other systemic and functional grammed State sequence. considerations, cause certain problems related to the reli Alternatively, the calculating the all possible branch met ability of stored data. rics may include calculating the all possible branch metrics One important functional consideration related to data using programmed States determined based on the result of reliability in emerging non-volatile memory devices is the 30 the first XOR operation and a second data sequence to be pattern with which data is stored across an array of proxi stored in a first word line together with the output sequence. mate memory cells. Poorly defined (or undesirable) data At this time, a value of a parameter corresponding to a programming patterns can lead to data degradation, whereas k-th bit line among the parameters may be determined based more appropriately defined data programming patterns on a programmed State corresponding to the k-th bit line result in better data reliability. For instance, during program 35 among the programmed States and a programmed State ming of a “target ' selected during a program corresponding to (k-1)-th bit line among the programmed ming operation, data previously stored in adjacent or proxi State. mate memory cells may be unintentionally disturbed (i.e., According to other embodiments of the inventive concept, erroneously changed) due to certain coupling effects (e.g., there is provided a memory controller including an inverse electric field coupling or F-poly coupling). That is, coupling 40 syndrome former configured to receive a first data sequence effects may change (e.g., widened) the threshold Voltage and generate a coset representative sequence that can be distribution of proximate memory cells and adversely affect divided into m-bit strings, where “m' is a natural number of the reliability of the non-volatile memory device. Therefore, at least 2; a Viterbi detector configured to perform a first methods of enhancing the reliability of the non-volatile XOR operation on each of the m-bit strings in the coset memory device are desired. 45 representative sequence and binary bits and to determine a survivor path sequence according to a result of the first XOR SUMMARY operation; and a bit-to-state mapper configured to map a second data sequence to be stored in a first word line According to some embodiments of the inventive con together with an output sequence, which is calculated by cept, there is provided a method of operating a memory 50 performing a second XOR operation on the coset represen controller. The method includes receiving a first data tative sequence and the Survivor path sequence, and the sequence and generating a coset representative sequence that output sequence to programmed States. can be divided into m-bit strings, where “m' is a natural The Viterbi detector may calculate all possible branch number of at least 2; performing a first XOR operation on metrics according to the result of the first XOR operation. each of the m-bit strings in the coset representative sequence 55 The all possible branch metrics may be each calculated as and binary bits; calculating all possible branch metrics the Sum of parameters. The parameters may be defined according to a result of the first XOR operation; determining according to a selection bit. a Survivor path sequence based on the all possible branch The Viterbi detector may calculate the all possible branch metrics; and performing a second XOR operation on the metrics using a first programmed State sequence, which is coset representative sequence and the Survivor path 60 determined based on the result of the first XOR operation sequence and generating an output sequence. and the second data sequence to be stored in the first word The method may further include mapping a second data line together with the output sequence, and a second pro sequence to be stored in a first word line together with the grammed State sequence determined based on page data bits output sequence and the output sequence to programmed that have been stored in a second word line. states and controlling a non-volatile memory device to 65 According to further embodiments of the inventive con perform a program operation according to the mapped cept, there is provided a memory system including the programmed States. above-described memory controller and a non-volatile US 9,460,782 B2 3 4 memory device configured to perform a program operation be directly connected or coupled to the other element or according to programmed States output from the memory intervening elements may be present. In contrast, when an controller. element is referred to as being “directly connected' or The memory system may be a Smart card, a secure digital “directly coupled to another element, there are no inter (SD) card, a multi-media card (MMC), or a vening elements present. As used herein, the term “and/or drive. The memory system may be a solid state drive (SSD). includes any and all combinations of one or more of the associated listed items and may be abbreviated as "/. BRIEF DESCRIPTION OF THE DRAWINGS It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these The above and other features and advantages of the 10 elements should not be limited by these terms. These terms inventive concept along with the making and use of the are only used to distinguish one element from another. For inventive concept will become more apparent to those example, a first signal could be termed a second signal, and, skilled in the art upon consideration of certain exemplary similarly, a second signal could be termed a first signal embodiments with reference to the attached drawings in without departing from the teachings of the disclosure. which: 15 The terminology used herein is for the purpose of describ FIG. 1 is a block diagram illustrating a memory system ing particular embodiments only and is not intended to be including a memory controller according to certain embodi limiting of the invention. As used herein, the singular forms ments of the inventive concept; “a”, “an and “the are intended to include the plural forms FIGS. 2 and 3 are respective diagrams illustrating thresh as well, unless the context clearly indicates otherwise. It will old voltage distributions with respect to operation of the be further understood that the terms “comprises” and/or encoder of FIG. 1 according to certain embodiments of the “comprising,” or “includes and/or “including when used inventive concept; in this specification, specify the presence of stated features, FIG. 4 is a block diagram further illustrating in one regions, integers, steps, operations, elements, and/or com possible example the encoder of FIG. 1; ponents, but do not preclude the presence or addition of one FIG. 5 is a diagram illustrating in one possible example a 25 or more other features, regions, integers, steps, operations, coset representative sequence that may be provided by the elements, components, and/or groups thereof. inverse syndrome former of FIG. 4; Unless otherwise defined, all terms (including technical FIG. 6 is a block diagram further illustrating in one and Scientific terms) used herein have the same meaning as possible example the inverse syndrome former of FIG. 4; commonly understood by one of ordinary skill in the art to FIGS. 7, 8 and 9 are block diagrams that illustrate possible 30 which this invention belongs. It will be further understood mode(s) of operation for the inverse syndrome former of that terms. Such as those defined in commonly used diction FIG. 6; aries, should be interpreted as having a meaning that is FIG. 10 is a trellis diagram that further illustrates the consistent with their meaning in the context of the relevant operation of the Viterbi detector of FIG. 4 during the art and/or the present application, and will not be interpreted calculation of branch metrics; 35 in an idealized or overly formal sense unless expressly so FIG. 11 is a trellis diagram that further illustrates the defined herein. operation of the Viterbi detector of FIG. 4 during the FIG. 1 is a block diagram illustrating a memory system determination of a Survivor path sequence; 100 including a memory controller 20 according to certain FIG. 12 is a block diagram further illustrating in one embodiments of the inventive concept. possible example the decoder of FIG. 1; 40 The memory system 100 may be implemented as an FIGS. 13, 14 and 15 are respective block diagrams further electronic device or a portable device. Such as a cellular illustrating the operation of the syndrome former of FIG. 12; telephone, a Smartphone, a tablet personal computer (PC), FIG. 16 is a flowchart summarizing one possible method a personal digital assistant (PDA), an enterprise digital of operating the memory controller of FIG. 1; assistant (EDA), a digital still camera, a digital video FIG. 17 is a block diagram of a memory system according 45 camera, a portable multimedia player (PMP), a personal to certain embodiments of the inventive concept; navigation device or portable navigation device (PND), a FIG. 18 is a block diagram of a memory card system handheld game console, or an e-book. according to certain embodiments of the inventive concept; The memory system 100 of FIG. 1 generally comprises a and host 10, a memory controller 20, and a non-volatile memory FIG. 19 is a block diagram of a memory system according 50 device 90. to still other embodiments of the inventive concept. The host 10 communicates an input data sequence DS1 to the memory controller 20 and receives an output data DETAILED DESCRIPTION sequence DS2 from the memory controller 20. The memory controller 20 controls the operation of the Embodiments of the inventive concept now will be 55 non-volatile memory device 90. For example, the memory described in some additional detail with reference to the controller 20 may be used to encode "input data from the accompanying drawings. The inventive concept may, how input data sequence DS1 received from the host 10, and ever, be embodied in many different forms and should not be control the non-volatile memory device 90 during a program construed as being limited to only the illustrated embodi operation used to program a write data sequence WD related ments. Rather, these embodiments are provided so that this 60 to the encoded input data. The program operation may be disclosure will be thorough and complete, and will fully performed by the memory controller 20 on a page by page convey the scope of the invention to those skilled in the art. basis, where a defined page size may be (e.g.) 512 bytes, Throughout the written description and drawings, like ref 2048 bytes, or 4096 bytes, etc. erence numbers and labels are used to denote like or similar During a read operation requested by the host 10, the elements. 65 memory controller 20 may be used to receive a read data It will be understood that when an element is referred to sequence RD from the non-volatile memory device 90. as being “connected' or “coupled to another element, it can decode the read data sequence RD, and then communicate US 9,460,782 B2 5 6 the resulting output data sequence DS2 to the host 10. In the intentionally biased, data patterning scheme that favors one foregoing context, the memory controller 20 of FIG. 1 is or more data states over another data state during the generally illustrated as including an encoder 30 and a definition of a write data sequence may be termed “state decoder 60. shaping. Consequently, more undesirable data patterns may The encoder 30 may be used to encode the input data be avoided by searching the input data sequence DS1 for sequence DS1 to avoid an undesirable data pattern, and data corresponding to a less favored data state in order to instead to provide an appropriate write data sequence WD reduce the number of memory cells that would otherwise be less likely to engender serious coupling effects during the arbitrarily programmed to the less favored State (e.g., the programming operation. That is, in many instances, were the third programmed state P3). input data sequence DS1 to be written to the non-volatile 10 FIG. 3 is a diagram illustrating threshold voltage distri memory device 90 without encoding during a program butions with respect to the operation of the encoder 30 of in operation, serious coupling effects might arise between FIG. 1 according to another embodiment of the inventive proximate memory cells of the non-volatile memory device concept. FIG. 3 shows the threshold voltage distributions 90. associated with triple-level memory cells (TLCs) capable of Use of the encoder 30 to avoid serious coupling effects 15 storing 3-bit data. Referring to FIGS. 1 and 3, E again necessitates the used commensurate use of the decoder 60 to denotes an erased state, while and P1, P2, P3, P4, P5, P6 and decode a read data sequence RD and output a corresponding P7 denote respective programmed States. output data sequence DS2. In the context of the FIG. 3, the encoder 30 may again be The non-volatile memory device 90 of FIG. 1 is assumed used to search the input data of an input data sequence DS1 to be a flash memory device in the working examples that in order to reduce a number of memory cells that will be follow. However, the non-volatile memory device 90 might programmed to a less favored State (e.g., seventh pro alternately be implemented using read-only memory grammed State P7). Assuming that the number of memory (ROM), programmable ROM (PROM), erasable PROM cells programmed to the seventh programmed State P7 is (EPROM), electrically erasable PROM (EEPROM), ferro reduced, the number of memory cells programmed to the electric random access memory (FRAM), magnetic RAM 25 fourth programmed state P4 is increases and the threshold (MRAM), phase-change RAM (PRAM), nano-RAM Voltage distribution associated with memory cells pro (NRAM), silicon-oxide-nitride-oxide-silicon (SONOS), grammed to the erased State E changes (i.e., widens). resistive memory, or . Consequently, undesirable patterns (e.g., a case where one In FIG. 1, the non-volatile memory device 90 includes a memory cell has the erased State E while an adjacent memory cell array 91 in which a plurality of memory cells 30 memory cell is programmed to the seventh programmed are arranged to store data provided by the memory controller state P7) is avoided. 20. Each of the memory cells is located at an intersection FIG. 4 is a block diagram further illustrating in one between one word line among a plurality of word lines possible example the encoder 30 of FIG. 1, and FIG. 5 is a (WL1 through WLX, where “x' is a natural number) and one diagram illustrating a coset representative sequence RS that bit line among a plurality of bit liens (BL1 through Bly, 35 may be provided by the inverse syndrome former 40 of FIG. where “y” is a natural number). 4. Referring collectively to FIGS. 1, 2, 3, and 4, the encoder FIG. 2 is a diagram illustrating threshold voltage distri 30 includes the inverse syndrome former 40, a Viterbi butions with respect to the operation of the encoder 30 of detector 50, a buffer 51, an XOR operator 53, and a FIG. 1 according to an embodiment of the inventive concept. bit-to-state mapper 55. FIG. 2 shows threshold voltage distributions associated with 40 The inverse syndrome former 40 receives the input data multi-level cells (MLCs) capable of storing 2-bit data (i.e., sequence DS1 and may be used to generate a corresponding data values '00', '01, '01, and 11) Referring to FIGS. 1 “coset representative sequence' RS that is divisible into and 2, the label E denotes an erased state for the MLC and m-bit strings, where “m' is a natural number greater than 1. P1, P2 and P3 denote respective first, second and third Referring to FIG. 5, the length of the coset representative programmed states for the MLC. Those skilled in the art will 45 sequence RS is N, where N is a natural number and may be recognize that the assumption of a 2-bit capable MLC is just divided into a plurality of m-bit strings. The operation of the one type of MLC that may be used in various embodiments inverse syndrome former 40 will be described in some of the inventive concept. additional detail with reference to FIGS. 6, 7, 8, and 9 The encoder 30 controls (i.e., defines) the “pattern' with hereafter. which the input data of the input data sequence DS1 will be 50 Referring to FIGS. 1, 2, 3, and 4, the viterbi detector 50 programmed in order to enhance the stored data reliability of may be used to perform a first XOR operation on each of the the non-volatile memory device 90 and minimize the cou m-bit strings in the coset representative sequence RS. That pling effects caused by the corresponding program opera is, convolutionally-encoded binary bits and the m-bit strings tion. For example, the encoder 30 may define a write data may be used during the first XOR operation to determine a sequence WD that does not have an undesirable pattern (e.g., 55 survivor path sequence SP. The Viterbi detector 50 may be a case where one memory cell has the erased state E while used to perform the first XOR operation on each m-bit an adjacent memory cell is programmed to the third pro string. The operation of the Viterbi detector 50 will be grammed state P3). described in some additional detail with reference to FIG. 10 In other words, the encoder 30 seeks to define write data hereafter. sequence WD that reduces the number of memory cells 60 The buffer 51 may be used to temporarily store the coset arbitrarily programmed to one or more less favored pro representative sequence RS. The XOR operator 53 may be grammed States (e.g., the third program State P3). In the used to perform a second XOR operation on the coset context of FIG. 1, when the number of memory cells representative sequence RS and the Survivor path sequence programmed to the third programmed State P3 is reduced, SP in order to calculate an output sequence OS. Then, the the number of memory cells programmed to the first pro 65 bit-to-state mapper 55 may be used to map the output grammed State P1 are increased and the threshold Voltage sequence OS. A resulting second data sequence to be stored distribution for the erased state E changes (i.e., widens). This in memory cells connected to a particular word line (e.g., the US 9,460,782 B2 7 8 first word line WL1) together with the output sequence OS bit SEL. For instance, when the selection bit SEL is “1” and that is used to define the programmed States for data in the the result of the first XOR operation is bit “0”, one of the write data sequence WD indicating the mapped programmed parameters W1, W2, M3, w4, and W5 corresponding to the bit states are provided to the non-volatile memory device 90. “0” is “0”. When the result of the first XOR operation is FIG. 6 is a block diagram of an example 40' of the inverse 5 “00110, the parameters 1, 2, 3, 4, and 5 are “0”, “0”, syndrome former 40 of FIG. 4. Referring to FIGS. 1, 4, and “1”. “1”, and “O'”, respectively. A branch metric is calculated 6, the inverse syndrome former 40' is constructed based on as the Sum of the parameters W1, W2, M3, w4, and W5, and a convolutional code that have a constraint length of 3 and therefore, the branch metric is 0+0+1+1+0=2. Table 1 sum generator polynomials of I1 0 1 and 1 1 1. marizes these result. The inverse syndrome former 40' includes a plurality of 10 inverse syndrome former units 40-1, 40-2, 40-3, and 40-4. TABLE 1. When output bits yO through y4 of the inverse syndrome former 40' are “m bits, input bits XO through x3 of the m-bit string Binary Result in coset bits of first inverse syndrome former 40' are (m-1) bits. Each of the representative A, B, C, XOR All possible branch input bits XO through x3 may be a most significant bit 15 sequence RS and D operation metrics (MSB) to be stored in the first word line WL1. The input bits XO through x3 of the inverse syndrome OO110 A = OOOOO OO110 O + 0 + 1 + 1 + 0 = 2 B = 11111 11 OO1 1 + 1 + 0 + 0 + 1 = 3 former 40' are part of the data sequence DS1. The first C = 10101 10011 1 + 0 + 0 + 1 + 1 = 3 inverse syndrome former unit 40-1 includes a plurality of D = O1010 O1100 O + 1 + 1 + 0 + 0 = 2 XOR operators 41 and 43 and a plurality of shift registers 45 O1011 A = OOOOO O1011 O + 1 + 0 + 1 + 1 = 3 B = 11111 101 OO 1 + 0 + 1 + 0 + 0 = 2 and 47. The structure of the other inverse syndrome former C = 10101 11110 1 + 1 + 1 + 1 + 0 = 4 units 40-2, 40-3, and 40-4 is the same as that of the first D = O1010 OOOO1 O + 0 + 0 + 0 + 1 = 1 inverse syndrome former unit 4.0-1. The number of inverse OO111 A = OOOOO OO111 O + 0 + 1 + 1 + 1 = 3 syndrome former units may vary with embodiments of the B = 11111 11 OOO 1 + 1 + 0 + 0 + 0 = 2 inventive concept. 25 C = 10101 10010 1 + 0 + 0 + 1 + 0 = 2 When the data sequence DS1 is “01101101 1010, the D = O1010 O1101 O + 1 + 1 + 0 + 1 = 3 inverse syndrome former 40' sequentially receives (m-1)-bit strings, i.e., “0110”, “1101’, and “1010 and sequentially When the selection bit SEL is “1” and the result of the first outputs m-bit strings "00110”, “01011”, and “00111'. XOR operation is bit “1”, one of the parameters W1, W2, M3, FIGS. 7, 8 and 9 are respective block diagrams further 30 W4, and W5 corresponding to the bit “1” is “1”. illustrating operation of the inverse syndrome former 40' of FIG. 11 is a trellis diagram illustrating operation of the FIG. 6. Referring to FIGS. 6 and 7, the inverse syndrome viterbi detector 50 of FIG. 4 during the determination of the former 40" receives the (m-1)-bit string "0110' and outputs survivor path sequence SP. In FIG. 11, BMA, BMB, BMC, the m-bit string "00110. Referring to FIGS. 6 and 8, after and BMD denote branch metrics and PMO, PM1, PM2, and outputting the m-bit string "00110, the inverse syndrome 35 PM3 denote path metrics. former 40" receives the (m-1)-bit string “1101 and outputs Referring to FIGS. 1, 4, and 11, the viterbi detector 50 the m-bit string “01011”. determines the survivor path sequence SP based on all Referring to FIGS. 6 and 9, after outputting the m-bit possible branch metrics. The survivor path sequence SP is string "01011, the inverse syndrome former 40" receives the “00000 11111 10101. Path metrics are calculated from all (m-1)-bit string “1010 and outputs the m-bit string 40 possible branch metrics and the survivor path sequence SP "00111. Consequently, when the inverse syndrome former is determined based on the path metrics. 40' receives the data sequence DS1 “01101101 1010, the The XOR operator 53 performs the second XOR opera inverse syndrome former 40' outputs the coset representative tion on the coset representative sequence RS "0011001011 sequence RS “0011001011 00111. 00111” and the survivor path sequence SP “00000 11111 FIG. 10 is a trellis diagram illustrating operation of the 45 10101” and calculates the output sequence OS “00110 Viterbi detector 50 of FIG. 4 during the calculation of branch 101 OO 1001 O. metrics. In FIG. 10, SO(k), S1(k), S2(k), and S3(k) denote The bit-to-state mapper 55 maps the output sequence OS present states; and SO(k+1), S1(k+1), S2(k+1), and S3(k+1) “00110 10100 10010 and the data sequence DS2 “11000 denote next states. 01001 11100 to be stored in the first word line WL1 Referring to FIGS. 1, 4, and 10, the viterbi detector 50 50 together with the output sequence OS “001101010010010 performs the first XOR operation on each of m-bit strings in to program states. Referring to FIG. 2, the erased state E is the coset representative sequence RS and binary bits A, B, “11”, the programmed state P1 is “10, the programmed C, and D and calculates all possible branch metrics accord state P2 is “00, and the programmed state P3 is “01. ing to the result of the first XOR operation. Therefore, the mapped programmed states are P3, P3, P1, For instance, when an m-bit string in the coset represen 55 P1, P2, P1, P3, P1, P2, P3, E, P3, P3, P1, and P2. tative sequence RS is "00110' and the binary bits A, B, C, The bit-to-state mapper 55 controls the actual data pro and D are “00000”, “11111”, “10101, and “01010, respec grammed by the non-volatile memory device 90 during a tively, the result of the first XOR operation is "00110, program operation according to the mapped program states. “11001”, “10011”, and “01100. When an m-bit string in the In this manner, the encoder 30 may be used to search for a coset representative sequence RS is "01011, the result of 60 data sequence that reduces the number of cells in the third the first XOR operation is “01011”, “10100”, “11110”, and programmed State P3. "00001. When an m-bit string in the coset representative For instance, the encoder 30 may search for a data sequence RS is "00111, the result of the first XOR opera sequence that avoids an undesirable pattern (e.g., a case tion is “00111”, “11000”, “10010, and “01101. where one memory cell has the erased State E and an Each of all possible branch metrics is calculated as the 65 adjacent memory cell is to be programmed to the third Sum of parameters W1, W2, M3, W4, and W5. The parameters programmed state P3). The Viterbi detector 50 receives a W1, W2, M3, W4, and W5 are defined according to a selection first data sequence to be stored in the first word line WL1 US 9,460,782 B2 10 together with the output sequence OS. When the output TABLE 4 sequence OS corresponds to an MSB data sequence in the State corresponding to k-th bit E E E E P1 P2 P3. Other first word line WL1, the first data sequence corresponds to line in first programmed C3Se:S a least significant bit (LSB) data sequence. The results of the state sequence first XOR operation and the first data sequence form a “first State corresponding to k-th bit E P1 P2 P3 E E E line in second programmed programmed State sequence'. state sequence For instance, when the first bit in the result of the first Parameter k corresponding to 1 4 9 16 4 9 16 O XOR operation is “0” and the first bit in the first data k-th bit line sequence is '1', the first state in the first programmed State 10 sequence is P3 since the LSB is “0” and the MSB is “1” in In other embodiments, when the Viterbi detector 50 the State P3 in FIG. 2. receives the first data sequence to be stored in the first word The Viterbi detector 50 also receives a second pro line WL1 together with the output sequence OS, it may grammed State sequence determined by page data bits stored calculate all possible branch metrics based on the result of in the second word line WL2. For instance, when the first 15 the first XOR operation and programmed states determined MSB and the first LSB are “0” and “1”, respectively, in the according to the first data sequence. second word line WL2, the first state in the second pro Each of all possible branch metrics is calculates as the grammed state sequence is P1 since the LSB and the MSB Sum of the parameters W1, W2, M3, W4, and W5. The parameter are “1” and “0”, respectively, in the state P1 in FIG. 2. wk corresponding to the k-th bit line may have a different The Viterbi detector 50 calculates all possible branch value according to a programmed State corresponding to the metrics based on the first programmed State sequence and k-th bit line and a programmed State corresponding to the the second programmed State sequence. Each of all possible (k-1)-th bit line among the programmed States, as shown in branch metrics is calculated as the sum of parameters. Table 5. The first programmed State sequence corresponds to a 25 sequence of bit lines. For instance, a k-th state in the first TABLE 5 programmed State sequence corresponds to the k-th bit line Programmed State corresponding E E E E P1 P2 P3. Other among the plurality of bit lines. to k-th bit line C3Se:S Programmed State corresponding E P1 P2 P3 E. E. E. When a program state corresponding to the k-th bit line in to (k - 1)-th bit line the first programmed State sequence is the erased State E and 30 Parameter k corresponding to 1 4 9 16 4 9 16 O a program state corresponding to the k-th bit line in the k-th bit line second programmed state sequence is the third programmed state P3, the parameter k corresponding to the k-th bit line FIG. 12 is a block diagram further illustrating in one is “1” and the other parameters are “0”. Table 2 summarizes example the decoder 60 of FIG. 1. Referring to FIGS. 1 and these results. 35 12, the decoder 60 comprises a selector 61 and a syndrome former 70. The decoder 60 receives a read data sequence RD TABLE 2 from the non-volatile memory device 90. The read data State corresponding to k-th bit line in first E P3 Other sequence RD may include an MSB data sequence BD1 programmed State sequence C3Se:S State corresponding to k-th bit line in second P3 E Other 40 stored in a word line, e.g., WL1, and an LSB data sequence programmed State sequence C3Se:S BD2 of the word line WL1. Parameter k corresponding to k-th bit 1 1 O The selector 61 outputs the MSB data sequence BD1 to line the syndrome former 70 in response to a selection signal PN and outputs the LSB data sequence BD2 to the host 10. The For instance, when the result of the first XOR operation 45 data sequence DS2 includes a data sequence BD1' output is "00110' and the first data sequence is “11100', the first from the syndrome former 70 and the LSB data sequence programmed state sequence is “P1, P1, E, P3, and P2’. BD2. When the second programmed state sequence is “P2, P2, E, FIGS. 13, 14 and 15 are block diagrams further illustrat E. and P1’, the parameters W1, W2, M3, 4, and 5 are “0”. ing operation of the syndrome former 70 of FIG. 12. “0”, “0”, “1”, and “0”. Since a branch metric is calculated as 50 Referring to FIGS. 1, 12, and 13, a syndrome former 70' the sum of the parameters w1, 2, 3, 4, and W5, the branch corresponding to the syndrome former 70 includes a plural metric is 0+0+0+1+0=1. Table 3 summarizes these results. ity of syndrome former units 70-1, 70-2, 70-3, 70-4, and 70-5. When input bits rO through ral of the syndrome TABLE 3 former 70' are “m” bits, output bits XO through x3 of the 55 syndrome former 70' are (m-1) bits. State in first P1 P1 E P3 P2 Each of the input bits rO through ra) may be an MSB programmed state sequence that has been stored in the first word line WL1. The input bits State in second P2 P2 E E P1 rO through ral of the syndrome former 70' are part of the programmed read data sequence RD. The first syndrome former unit 70-1 state sequence 60 includes a plurality of XOR operators 71 and 73 and a Parameters 1, 2, 1 = 0 2 = 0 3 = 0 A = 1 5 = 0 3, 4, and 2.5 plurality of shift registers 75 and 77. The structure of the Branch metric O + 0 + 0 + 1 + 0 = 1 other syndrome former units 70-2, 70-3, 70-4, and 70-5 is the same as that of the first syndrome former unit 70-1. The number of syndrome former units may vary with the A parameter may have a different value according to the 65 embodiments of the inventive concept. first programmed State sequence and the second pro When the MSB data sequence BD1 is "00110 10100 grammed State sequence, as shown in Table 4. 10010, the syndrome former 70' sequentially receives m-bit US 9,460,782 B2 11 12 strings "00110”, “10100', and “10010 and sequentially ring to FIG. 18, the memory system 1800 may be imple outputs (m-1)-bit strings “0110”, “1101’, and “1010”. mented as a memory card or a Smart card. The memory FIG. 16 is a flowchart summarizing in one possible system 1800 includes a host 1820 and a card system 1810. example a method of operating the memory controller 20 of The card system 1810 includes a memory controller 1813, FIG. 1. Referring to FIGS. 1, 4, and 16, the inverse syn 5 a non-volatile memory device 1815, and a card interface drome former 40 receives the input data sequence DS1 and 1811. The host 1820, the memory controller 1813, and the generates a corresponding coset representative sequence RS non-volatile memory device 1815 respectively correspond capable of being divided into m-bit strings (S10). to the host 10, the memory controller 20, and the non The viterbi detector 50 performs the first XOR operation volatile memory device 90 illustrated in FIG.1. The memory on each of the m-bit strings in the coset representative 10 controller 1813 may control data exchange between the sequence RS and then calculates all possible branch metrics non-volatile memory device 1815 and the card interface according to the result of the first XOR operation (S20). The 1811. Viterbi detector 50 then determines the survivor path The card interface 1811 may be a secure digital (SD) card sequence SP based on the all possible branch metrics (S30). interface or a multi-media card (MMC) interface, but the The XOR operator 53 performs the second XOR opera 15 inventive concept is not restricted to the current embodi tion on the coset representative sequence RS and the Survi ments. The card interface 1811 may interface the host 1820 Vor path sequence SP and outputs the output sequence OS and the memory controller 1813 for data exchange accord (S40). The bit-to-state mapper 55 then maps the output ing to a protocol of the host 1820. The card interface 1811 sequence OS and a second data sequence to be stored in the may support a universal serial bus (USB) protocol and an first word line WL1 together with the output sequence OS to inter-chip (IC)-USB protocol. Here, the card interface 1811 programmed states (S50). Finally, the non-volatile memory may indicate a hardware Supporting a protocol used by the device 90 performs a program operation according to the host 1820, software installed in the hardware, or a signal mapped programmed States (S60). transmission mode. FIG. 17 is a block diagram of a memory system 1700 When the card system 1810 is connected with a host according to certain embodiments of the inventive concept. 25 interface 1823 of the host 1820, the host interface 1823 may Referring to FIG. 17, the memory system 1700 includes a perform data communication with the non-volatile memory memory controller 1730, a non-volatile memory device device 1815 through the card interface 1811 and the memory 1740, and a processor 1710. The memory controller 1730 controller 1813 according to the control of a processor 1821. may be implemented within the processor 1710. At this time, the host 1820 may be a PC, a tablet PC, a digital The memory controller 1730 and the non-volatile memory 30 camera, a digital audio player, a cellular phone, a console device 1740 respectively correspond to the memory con Video game hardware, or a digital set-top box. The card troller 20 and the non-volatile memory device 90 illustrated system 1810 may be implemented as a flash memory drive, in FIG. 1. The memory controller 1730 may control the a USB memory drive, an IC-USB memory drive, or a access operations, e.g., a program operation, an erase opera memory Stick. tion, and a read operation, of the non-volatile memory 35 FIG. 19 is a block diagram of a memory system 1900 device 1740 according to the control of the processor 1710. according to certain embodiments of the inventive concept. Data programmed in the non-volatile memory device Referring to FIG. 19, the memory system 1900 may be 1740 may be displayed through a display 1720 according to implemented as a device Such as a Solid state the control of the processor 1710 and/or the memory con drive (SSD). troller 1730. An input device 1760 enables control signals 40 The memory system 1900 includes a host 1910, a memory for controlling the operation of the processor 1710 or data to controller 1950, a plurality of memory devices 1960, e.g., be processed by the processor 1710 to be input to the NAND flash memory devices, a buffer manager 1920, a memory system 1700. The input device 1760 may be dynamic random access memory (DRAM) controller 1930, implemented by a pointing device Such as a touch pad or a and a DRAM 1940. The host 1910, the memory controller computer mouse, a keypad, or a keyboard. 45 1950, and one of the memory devices 1960 respectively A radio transceiver 1750 transmits or receives radio correspond to the host 10, the memory controller 20, and the signals through an antenna ANT. The radio transceiver 1750 non-volatile memory device 90 illustrated in FIG. 1. The may convert radio signals received through the antenna ANT memory controller 1950 may control the access operation of into signals that can be processed by the processor 1710. The the memory devices 1960. processor 1710 may process the signals output from the 50 The buffer manager 1920 may control data transmission radio transceiver 1750 and transmit the processed signals to among the host 1910, the memory controller 1950, and the the memory controller 1730 or the display 1720. DRAM controller 1930. The DRAM controller 1930 may The memory controller 1730 may program the signals control data transmission between the buffer manager 1920 processed by the processor 1710 to the non-volatile memory and the DRAM 1940. device 1740. The radio transceiver 1750 may also convert 55 As described above, according to certain embodiments of signals output from the processor 1710 into radio signals and the inventive concept, a memory controller may be used to output the radio signals to an external device through the search for a data sequence having a desirable data pattern. antenna ANT. This desirable (or more desirable) data pattern may then be The processor 1710 may control the operation of the used to define a write data sequence for a non-volatile display 1720 to display data output from the memory 60 memory device, thereby enhancing the reliability of the controller 1730, data output from the radio transceiver 1750, non-volatile memory device. or data output from the input device 1760. The elements While the inventive concept has been particularly shown 1710, 1720, 1730, 1740, 1750, and 1760 of the memory and described with reference to exemplary embodiments system 1700 may communicate with one another through a thereof, it will be understood by those of ordinary skill in the buS 1701. 65 art that various changes in forms and details may be made FIG. 18 is a block diagram of a memory card system 1800 therein without departing from the scope of the inventive according to embodiments of the inventive concept. Refer concept as defined by the following claims. US 9,460,782 B2 13 14 What is claimed is: generating a coset representative sequence divisible into 1. A method of operating a memory controller, the method m-bit strings, where “m' is a natural number greater comprising: than 1, from the input data sequence; receiving an input data sequence from a host; performing a first XOR operation on each of the m-bit generating a coset representative sequence divisible into strings in the coset representative sequence; m-bit strings, where “m' is a natural number greater calculating all possible branch metrics according to a than 1, from the input data sequence; result of the first XOR operation; performing a first XOR operation on each of the m-bit determining a Survivor path sequence based on the all strings in the coset representative sequence; possible branch metrics; calculating all possible branch metrics according to a 10 performing a second XOR operation on the coset repre result of the first XOR operation; sentative sequence and the Survivor path sequence to determining a Survivor -path - - sequence based on the all generate an output sequence; and performingpossible brancha second metrics; XOR operation on the coset repre- providingidi writeite dadata sequence based on theh output sentative sequence and the Survivor path sequence to 15 sequence to a non-volatile memory device, generate an output sequence; and wherein the calculating the all possible branch metrics providing write data sequence based on the output comprises calculating the all possible branch metrics sequence to a non-volatile memory device, uS1ng programmed states determined as a result of the wherein the calculating the all possible branch metrics first XOR operation and a second data sequence to be comprises: 2O stored in a first word line together with the output calculating the all possible branch metrics using a first Sequence. programmed State sequence determined on the basis of 8. The method of claim 7, wherein the all possible branch the first XOR operation and a second data sequence to metrics are each calculated as a Sum of parameters, and a be stored in a first Word line together with the output value of a parameter corresponding to a k-th bit line among sequence, and a second programmed State Sequence 25 the parameters is determined based on a programmed state determined on the basis of page data bits that have been corresponding to the k-th bit line among the programmed stored in a second word line. states and a programmed State corresponding to (k-1)-th bit 2. The method of claim 1, further comprising: line among the programmed State. meets data th to be I 1 a E. 9. A memory controller configured for use in a memory word line of the non-volatile memory device together 30 system with a non-volatile memory device, the memory with the output sequence, wherein the output sequence controller comprising:- - - - defines mapped programmed states for data in the write an inverse syndrome former that receives an input data data sequence; and sequence and generates a coset representative sequence controlling the non-volatile memory device to perform a divisible i bi here “m i 1 program operation according to the mapped pro- 35 1V1S1ble 1 to n-b1t strings, Where in 1S a natura grammed States. number greater than 1; 3. The method of claim 1, wherein the all possible branch a viterbi detector that performs a first XOR operation on metrics are each calculated as the Sum of parameters, each of the m-bit strings in the coset representative wherein the parameters are defined according to a selection sequence to determine a survivor path sequence accord bit. 40 ing to a result of the first XOR operation; and 4. The method of claim 3, wherein when the selection bit a bit-to-state mapper that maps a second data sequence to is “1” and the result of the first XOR operation is bit “0”, one be stored in a first word line of the non-volatile memory of the parameters corresponding to the bit “O'” is “0”, and device together with an output sequence calculated by when the Selection bit is “1” and the result of the first XOR performing a second XOR operation on the coset operation is bit “1”, one of the parameters corresponding to 45 representative sequence and the Survivor path the bit 1 is 1. sequence, and provides an output sequence defining 5. The method of claim 1. wherein the non-volatile programmed States for data in a write data sequence memory device comprises multi-level memory cells capable provided to the non-volatile memory device, of being programmed to one of an erased state and a number wherein the Viterbi detector calculates the all possible of Rigitells indig highest E.Ogrstate, 50 branch metrics using a first programmed State sequence the a R e an tries are each Calculated as a determined based on the first XOR operation and the Sum of parameters, an - second data sequence to be stored in the first word line when a programmed State corresponding to a k-th bit line together with the output sequence, and a second pro in the first programmed State sequence is the erased grammed State sequence determined on the basis of state and a programmed State corresponding to the k-th 55 data bits that have b di d d bit line in the second programmed State sequence is the page tab1tS that have been Stored 1n a Second WOr highest programmed State, a parameter corresponding line. to the k-th bit line among the parameters is “1” and the 10. A memory system comprising: other parameters are “0”. the memory controller of claim 9; and 6. The method of claim 1, wherein the all possible branch 60 a non-volatile memory device that performs a program metrics are each calculated as a Sum of parameters, and the operation according to the programmed States of the parameters have different values according to the first pro write data sequence received from the memory con grammed State sequence and the second programmed State troller. Sequence. 11. The memory system of claim 10, wherein the memory 7. A method of operating a memory controller, the method 65 system is one selected from the group consisting of a Smart comprising: card, a secure digital (SD) card, a multi-media card (MMC), receiving an input data sequence from a host; and a flash memory drive. US 9,460,782 B2 15 16 12. The memory system of claim 10, wherein the memory system is a solid state drive (SSD). k k k k k