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Produced by the NASA Center for Aerospace Information (CASI) NASA CR 145a91 ^[vAS.^^CR-1^5t)5'i) Z#^'U^Sa.Er^^^[3N OF F^^sLD .^ H7'7w^-3337 ^I^DUGLD Tk^APPS#aG Gl^ k'IGt^TIhG i^i^^'^S (^^xa5 xnst,^umQnts, Inc.} 8G A fiC t^QS/^#^ &Q7 . CSCT, 09C Unclas ' G3/33 ^82^#3 [NVEST[GATIQN OF F[I=I~D [NDUGED T[^APPLNG DN FLOATING GATI~S By W. Milian Gosney, Frincipal In^estigatar Walter T. Matzen and Gary E. Nelsan '. Prepared under Contract No. NAS1-1361.0 Uy TEXAa INSTRUMENTS INCORPORATED l'. O. Bax 5Al2 Dallas, Texas 75222 ^^Q ^ ^^^ ^ ^ ^. 9j 7 for ^^ ^^^ 197 ^^^, o ^ ^^^^ ^} ^ ^ ^^ ^u^ ^ f r, H^^ gRA^CH g^c ; ^^ s^^^^^^Zt^^^6^'^^^^ National Aeronautics and Space Administration Langley Research Center Ham.pto^^, Virginia 23665 ... W ^_ ,_._ _ _^ ._ _ e -. .. ,- _ ,_ ! _ ! t II11 1^ ^^ ^ 1 i ^ ^^ t f^ 1^ ^^ TABLE OF CONTENTS ^^ }^1t Section Title ^ Page 1 ^ —i ^ I. INTRODUCTION I I II, FIRST EXPEA.iiviENTAL SERIES 3 A. DIFMG^ Development 3 III. SECOND EXPERIMENTAL SERIES : 7 A. DIFMOS Development 7 B. Bootstrapping . 18 IV, THIRD EXPERIMENTAL SERIES . 23 A, Description of Task . , 23 B. Ian Irnplanted Injector Junction . 24 C, Electron Injector Insulator Variations , , , 26 I D. Hole Injector Insulator Variations 27 V. FOURTH EXPERIMENTAL SERIES . 33 _, VI. FIFTH EXPERIMENTAL SERIES : 43 I A. Theoretical Study of Previous Devices . 43 B. Avalanche Injector Analysis 44 1. Consideration of Physical Reality of Avala^iching Holes =j , and Injecting Positive Charges . 49 C. Figure of Merit , . - . 52 ^ >' D. Design Ruie Changes 54 =f E, Device Designs . 55 ^. F. Processing 61 1, G. Testing 61 ^t 1. Data Write, Erase, and Read Speed and Power 65 2, Data Storage Without Applied Power 69 ;:.; 3. Data Degradation Due to Read Cycles 70 4. Device Degradation Due to V4'rite^Erase Cycling 71 VII, CONCLUSION AND SUMMARY . 73 - VIII. References 75 ^t ,. iii . ^ . ,, r..._ ^ , . .... _„ _.._ ' _ 1-- LIST OF ILLUSTRATIONS Figure Title Page ^,i" ^^f ; l J 1. Dual Avalanche Injection Nonvolatile Semiconductor Memory Device Featuring Low-Voltage Hole and Electron Avalanche Injection to a Floating Gate 5 ! } 2. Isometric Drawing of a Cross Section Sltawing Details of the i3 -' ° Hale and EIectron Injection Regions . 6 ^^ ^' ^^ 3. Test Structures 1-4 (Sheet 1 of 3} 8 -- Test Structures 5-$ (Sheet 2 of 3) 9 ^^,^ Test Structures 4-10 (Sheet 3 of 3) 10 '^ ^r 4. Final Floating Gate Voltage as a Function of Avalanche Voltage for p^Jn+ Electron Injectors. Avalanche pulse was 500 uA at 100 ms I2 S. Avalanche Injection Experiments on Structure DIFIS (NASA Structure 4a} 13 ^^ `"' - b. Comparison of 22 and 13 BV CMOS Slices—Fixed Gate Bias Hole ,:.!^ ':. Injection Experiments . 14 ^ " 7. Floating Gate Discharge Experiments, 13 BV CMOS, Pulsed f Negative Avalanche . 16 t '^ : , 8. CMOS Test Bar Bonded for Avalanche Experiments l7 r. ^' " 9, Bonding Dia ^'am for the CMOS 13ootstrap Ca1? acitor Ex I?eriments . 19 '< 10. Schematic Diagram and Physical Structure of the Bootstrap CMOS Test Device 20 11. Measurement of the WriteJErase Window as a Function of the Bootstrap Bias Voltage Using Discrete CMOS Test Structures . 2I _ 12. Avalanche Breakdown in DIFMOS Structures . 2S 13. Circuit for M^:asuring Electron Injection Current 27 . 14, Eiectran Injection Gate Current versus Time far Various Oxide Conditions 28 lS. Circuits for Evaluating "Write" and "Erase" Injectors 30 lb. DIFMOS Memory Cell Design — Dua113its with LeftJRight Select Cb Sized far 90%Coupling . 34 17. DIFMOS Memory Cell Designs — 0.50 C b (left}, 0.25 C h (right) . 34 :" 18, Example of Charge Retention an Floating Gate Array 37 E 19. Degradation of WJE Envelope versusNumber of WJE Cycles 37 ,, 20, Lag Plot of Degradation of WJE Envelope versus Number of WJE Cycles 38 ^^ti^ '^ °^^IG PACE BLAND£ NO^F 1"°is . , -4, I v F_ __ ,.._.. LIST OF ILLUSTRATI4N5 (cas^tinuedj Figure Title Page 21. Comparison of WEE Characteristics of Full, One-Half, and One-Quarter-Sized DIF1viOS Cells 39 22, Goanparison of WEE Characteristics of Fuil-Sized DIFMOS CeIis versus. Pulse Widths . 40 23. Recovery of WfE Window Following Storage at 125°C : : 4I l 24: .Schematic Representation of DIFMOS Nonvolatile Memory Cell 4S 25. Energy Band Diagram for Electron Injection Showing Perturbation of the Barrier Height by the Insulator Field {Schottky lowering} 48 26, Avalanche Injection of Holes and Electrons into SiO^ Fixed Gate Bias : : SO 27. Energy Band Diagram Showing Mechanism of Hot Hole.Injection Whereby ' Empty States are Created Deep in the Valence Band During the Avalanche: Filling these states by electrons from the SiO^ Constitutes hole injection.. .. .. .: , 51 28. Fifth Experimental Series -- STAGG ` 56 29. Fifth Experimental Series — AGGNP S7 30. Fifth Experimental Series — NOCON S9 31. Fifth Experimental Series --- NOCON 60 32. Fifth Experimental Series = CNSGT 62 33. Fifth Experimental Series — AGSGT 63 34. Time Dependence of Floating Gate Voltage During Avalanche of the pin} Electron Injector G6 35. Time Dependence of Floating Gate Voltage During Avalanche of a p^/nom Hole Injector Junction I A = — 500 ^cA at — 14.9 volts 67 36. Time Dependence of Floating Gate Voltage During Writing and l;rasing . 68 37. Temperature Dependence of Charge Storage , . 70 38. Envelope of On/Off Window versus Number of Cycles 71 vi. ^f i LIST OF TABLES Table Title !'age ^:" i I.: Processing Sequence: Ten Structure Designs I 1 II. Structure 10 junction Spacings ^(nm) (p-and n-Channel Devices) . 11 III. Experimental Process ^Iariations . 2^ ^ . IV. Characteristics c (Electron Injectors for Various Oxides . 2G I V. Device Characteristics for Various Hole-Injector Dielectrsc Filrns 31 ^ ` VL: Average Peak Electric Fields in Device Tnsulatnrs During Read (Sense), Write and Erase Cycles . 46 VII. DIFMOS Process Sequence 64 VIII. DIFMOS Process Comparison (Metal-Gate PMOS Pasis) 64 .^ ^^ fl ^^ ^' h. }^. _ .. .. ^.. _ - - 1 4 .. i ^ `... t Uil ;.. I^^:^^^:^^^ING . PAGli i3LAN^ NUT Iri^A^»:^>w^^ SUMMARY In a series of five experimental design iterations, an electrically-alterable read-only 1 memory (EAROM} ar repro^rammabie xead-only memory (R^ROM} technology has been developed which can be fabricated using asingle-level, metal-gate p-channel MOS process with all conventional manufacturing steps. Given the acronym DIFMOS for , Dual Injector, Floating gate MOS, this technology utilizes the floating-gate technique for nonvolatile storage of data. Avalanche injection of hat electrons through gate oxide from a special injector diode in each bit is used to charge the floating gates. From 30% to ^0% of the electron injector avalanche voltage can be attained by the floating gate in about 50 ms far S00 µA avalanche currents. Once charged, the floating gates will stay charged almost indefinitely. Measurements of charge decay from the floating gates indicate a log time dependence of the lass of approximately 0.06% per decade of time. Thus, over 90% of the original charge will remain after 100 years at roam temperature. A second injector structure included in each bit permits discharge of the floating gate by avalanche injection of holes through gate oxide. A special bootstrap capacitor must be operated with the hole injector to provide electric fields favorable for Bole injection. Like the charging operation, the discharge operation is accomplished within 50 ms using S00 uA avalanche currents. The size of the bootstrap capacitor and its associated voltage must be sufficient to provide at least a 1 S molt change on the floating gate to assure complete discharge. Thus, the overall design of the DIFMOS bit is dictated by the physical considerations rec}uired for each of the avalanche injector types. The presence of electron and hole traps in the injector oxides causes a slow build-up of charge in the injector oxides as the injectors are operated, resulting in a decreasing efficiency of injection. This means that DIFMOS bits can only be charged and discharged a finite number of times—at present, the limit is about 10 `f cycles. $ut this limitation is sufficiently large to permit application of the DIFMOS technology to electrically alterable, read-mostly memories. Since it is basically a PMOS plus three diffusion technology, and since its cell size is in the 0 to 16 nm2 to 16 nmZ size range, circuits of 1 K to 2K bits should be economically feasible. The ease with which DiFMOS can be used in system designs makes it attractive for many applications such as calculator and microprocessor program storage. Standard processing, electrically erasable by rvw or by bit, fully decodable without substrate isolation, unlimited reading capability; and a variety of possible organizations tend to offset the programming limitations. Additional reductions in cell size and improvements in device performance and circuit density will be realized as the floating gate, avalanche-injected, nonvolatile semiconductor memories continue to evolve. ix ^-;^I'I?flDU^^^IL.I'i'^c^ GF T::^; ; INVESTIGATION OF FIELD INDUCED TRAPPING ON FLOATING GATES W.