USOO946O782B2 (12) United States Patent (10) Patent No.: US 9,460,782 B2 Seol et al. (45) Date of Patent: Oct. 4, 2016 (54) METHOD OF OPERATING MEMORY (56) References Cited CONTROLLER AND DEVICES INCLUDING MEMORY CONTROLLER U.S. PATENT DOCUMENTS 8,050,086 B2 11/2011 Shalvi et al. (71) Applicant: SAMSUNGELECTRONICS CO., 8,085,605 B2 12/2011 Yang et al. LTD., Suwon-si, Gyeonggi-do (KR) 2005.0089121 A1* 4/2005 Tsai ...................... HO3M13/41 375,341 (72) Inventors: Chang Kyu Seol, Osan-si (KR); Jun 2011 0145487 A1 6/2011 Haratsch et al. Jin Kong, Yongin-si (KR); Hong Rak 2011 (0289.376 A1 1 1/2011 Maccarrone et al. 2012,0005409 A1 1/2012 Yang Son, Anyang-Si (KR) 2012/0066436 A1 3/2012 Yang (73) Assignee: Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do (KR) FOREIGN PATENT DOCUMENTS JP 2011504276 A 2, 2011 (*) Notice: Subject to any disclaimer, the term of this KR 2011.0128852. A 11/2011 patent is extended or adjusted under 35 KR 2012O061214 A 6, 2012 U.S.C. 154(b) by 274 days. * cited by examiner (21) Appl. No.: 14/205,496 Primary Examiner — Idriss N Alrobaye (22) Filed: Mar. 12, 2014 Assistant Examiner — Dayton Lewis-Taylor (65) Prior Publication Data (74) Attorney, Agent, or Firm — Volentine & Whitt, US 2014/0281293 A1 Sep. 18, 2014 PLLC (30) Foreign Application Priority Data (57) ABSTRACT Mar. 15, 2013 (KR) ........................ 10-2013-0O28O21 A method of operating a memory controller includes receiv ing a first data sequence and generating a coset representa (51) Int. Cl. tive sequence that can be divided into m-bit strings, where G06F 2/02 (2006.01) “m' is a natural number of at least 2; performing a first XOR GIC II/56 (2006.01) operation on each of the m-bit strings in the coset represen GITC 7/10 (2006.01) tative sequence and binary bits; calculating all possible GI IC 16/34 (2006.01) branch metrics according to a result of the first XOR (52) U.S. Cl. operation; determining a Survivor path sequence based on CPC ......... GIIC II/5642 (2013.01); GIIC 7/1006 the all possible branch metrics; and performing a second (2013.01); GIIC II/5628 (2013.01); G1 IC XOR operation on the coset representative sequence and the 16/3418 (2013.01); G1 IC 2211/5632 (2013.01) Survivor path sequence and generating an output sequence. (58) Field of Classification Search None See application file for complete search history. 12 Claims, 19 Drawing Sheets 100 BL1BL2 BLy Memory Controller Memory Device U.S. Patent Oct. 4, 2016 Sheet 1 of 19 US 9,460,782 B2 FIG. 1 EnCOder BL1 BL2 BLy Memory Controller Memory Device U.S. Patent Oct. 4, 2016 Sheet 2 of 19 US 9,460,782 B2 FIG 2 State Normal (conventional) E P1 P2 P3 Voltage margin LSB 1 O (obtained by state shaping) MSB 1 () O (9) U.S. Patent Oct. 4, 2016 Sheet 3 of 19 US 9,460,782 B2 FIG 3 State shaping (reduce bit 1 at MSB/LSB page, reduced bit 0 at CSB page - - - - - - Normal (conventional) Threshold Voltage Voltage margin (obtained by State shaping) U.S. Patent Oct. 4, 2016 Sheet 4 of 19 US 9,460,782 B2 FIG 4 40 55 Inverse DS1 Syndrome Former Viterb SEL DeCOder U.S. Patent Oct. 4, 2016 Sheet 5 Of 19 US 9,460,782 B2 FIG 5 RS ... I mbit mbit mbit m bit U.S. Patent Oct. 4, 2016 Sheet 6 of 19 US 9,460,782 B2 FIG. 6 40 O- - - y4) ^ x(3)--GD-CD/S y3 ============= x2) y2) (m-1) bit - 40–2 m bit X1 - - - - - - - - - - - - - - y1 - 40-3 XO - - - - - - - - - - - - - - yO - r- 40-4 U.S. Patent Oct. 4, 2016 Sheet 7 Of 19 US 9,460,782 B2 FIG 7 40 r - - - - - - - - - - - - - - - - - y40 CD-CD y30 1 x2 -(D-CD-I-y(2) ----E.------ 1x1) -(D-CDI-y(1) ============= OXO CD-CD yO 0 U.S. Patent Oct. 4, 2016 Sheet 8 of 19 US 9,460,782 B2 FIG. 8 1x3) 1 x2 OX1 1 x0 U.S. Patent Oct. 4, 2016 Sheet 9 Of 19 US 9,460,782 B2 FIG 9 1x3) 0x2) 1x1) OXO U.S. Patent Oct. 4, 2016 Sheet 10 of 19 US 9,460,782 B2 A=OOOOO B=11111 C=10101 D=01010 U.S. Patent Oct. 4, 2016 Sheet 11 of 19 US 9,460,782 B2 U.S. Patent Oct. 4, 2016 Sheet 12 of 19 US 9,460,782 B2 FIG. 12 70 61 Syndrome Former ose Selector PN U.S. Patent Oct. 4, 2016 Sheet 13 Of 19 US 9,460,782 B2 FIG 13 U.S. Patent Oct. 4, 2016 Sheet 14 of 19 US 9,460,782 B2 FIG 14. 70' U.S. Patent Oct. 4, 2016 Sheet 15 Of 19 US 9,460,782 B2 FIG 15 U.S. Patent Oct. 4, 2016 Sheet 16 of 19 US 9,460,782 B2 FIG 16 GENERATE COSET REPRESENTATIVE SEQUENCE S10 CALCULATE ALL POSSIBLE BRANCH METRICS -S2O DETERMINE SURVIVOR PATH SEQUENCE S30 OUTPUT OUTPUT SEQUENCE S40 MAP SECOND DATA SEQUENCE AND OUTPUT SEQUENCE TO PROGRAMMED STATES S50 PERFORM PROGRAM OPERATION ACCORDING TO THE MAPPED PROGRAMMED STATES S60 U.S. Patent Oct. 4, 2016 Sheet 17 Of 19 US 9,460,782 B2 FIG. 17 1700 1701 1720 Display RADIO TRANSCEIVER 1710 Processor 1730 Memory 1760 Controller Input Device KO U.S. Patent Oct. 4, 2016 Sheet 18 of 19 US 9,460,782 B2 FIG. 18 1820 1810 HOST 1821 1823 1811 HOSt Card ProCeSSOr Interface Interface U.S. Patent Oct. 4, 2016 Sheet 19 Of 19 US 9,460,782 B2 ~~~~096|| US 9,460,782 B2 1. 2 METHOD OF OPERATING MEMORY The all possible branch metrics may be each calculated as CONTROLLER AND DEVICES INCLUDING the Sum of parameters. The parameters may be defined MEMORY CONTROLLER according to a selection bit. When the selection bit is “1” and the result of the first CROSS-REFERENCE TO RELATED XOR operation is bit “0”, one of the parameters correspond APPLICATIONS ing to the bit “0” may be “0”. When the selection bit is “1” and the result of the first XOR operation is bit “1”, one of This application claims priority under 35 U.S.C. S 119(a) the parameters corresponding to the bit “1” may be “1”. from Korean Patent Application No. 10-2013-0028021 filed The calculating the all possible branch metrics may on Mar. 15, 2013, the subject matter of which is hereby 10 include calculating the all possible branch metrics using a incorporated by reference. first programmed State sequence, which is determined based on the result of the first XOR operation and a second data BACKGROUND sequence to be stored in a first word line together with the output sequence, and a second programmed State sequence Embodiments of the inventive concept relate to memory 15 systems and memory controllers. Embodiments of the determined based on page data bits that have been stored in inventive concept relate to methods of operating a memory a second word line. controller that control the definition or shaping of a data When a programmed State corresponding to a k-th bit line pattern. in the first programmed State sequence is an erased state and A non-volatile memory device, such as a NAND flash a programmed State corresponding to the k-th bit line in the memory device, includes a great number of memory cells. second programmed State sequence is a highest programmed With increased integration density made possible by emerg state, a parameter corresponding to the k-th bit line among ing fabrication technologies, the separation distance the parameters may be “1” and the other parameters may be between adjacent (and nearby) memory cells has decreased “0”. The parameters may have different values according to markedly. The increasingly close proximity of individual 25 the first programmed State sequence and the second pro memory cells, together with other systemic and functional grammed State sequence. considerations, cause certain problems related to the reli Alternatively, the calculating the all possible branch met ability of stored data. rics may include calculating the all possible branch metrics One important functional consideration related to data using programmed States determined based on the result of reliability in emerging non-volatile memory devices is the 30 the first XOR operation and a second data sequence to be pattern with which data is stored across an array of proxi stored in a first word line together with the output sequence. mate memory cells. Poorly defined (or undesirable) data At this time, a value of a parameter corresponding to a programming patterns can lead to data degradation, whereas k-th bit line among the parameters may be determined based more appropriately defined data programming patterns on a programmed State corresponding to the k-th bit line result in better data reliability. For instance, during program 35 among the programmed States and a programmed State ming of a “target memory cell' selected during a program corresponding to (k-1)-th bit line among the programmed ming operation, data previously stored in adjacent or proxi State. mate memory cells may be unintentionally disturbed (i.e., According to other embodiments of the inventive concept, erroneously changed) due to certain coupling effects (e.g., there is provided a memory controller including an inverse electric field coupling or F-poly coupling). That is, coupling 40 syndrome former configured to receive a first data sequence effects may change (e.g., widened) the threshold Voltage and generate a coset representative sequence that can be distribution of proximate memory cells and adversely affect divided into m-bit strings, where “m' is a natural number of the reliability of the non-volatile memory device.