Fundamentals of Computer Systems Sequential Logic
Stephen A. Edwards
Columbia University
Fall 2011 State-Holding Elements Bistable Elements
Q Q Q
Q
Equivalent circuits; right is more traditional.
Two stable states:
0 1
1 0 A Bistable in the Wild
This “debounces” the coin switch.
Breakout, Atari 1976. SR Latch
R Q S Q
R Q Q S SR Latch
0 R 1 Q S Q
R Q 1 Q S 0
R S
Q Set Q SR Latch
0 R 1 Q S Q
R Q 0 Q S 0
R S
Q Hold, State 1 Q SR Latch
1 R 0 Q S Q
R Q 0 Q S 1
R S
Q Reset Q SR Latch
0 R 0 Q S Q
R Q 0 Q S 1
R S
Q Hold, State 0 Q SR Latch
1 R 0 Q S Q
R Q 1 Q S 0
R S
Q Huh? Q SR Latch
0 R 1 Q S Q
R Q 1 Q S 0
R S
Q Set Q SR Latch
0 R 1 Q S Q
R Q 0 Q S 0
R S
Q Hold, State 1 Q SR Latch
1 R 0 Q S Q
R Q 1 Q S 0
R S
Q Huh? Q SR Latch
0 R X Q S Q
R Q 0 Q S X
R S
Q Undefined Q SR Latches in the Wild
Generates horizontal and vertical synchronization waveforms from counter bits. Stunt Cycle, Atari 1976. D Latch
D Q D Q C C Q Q
inputs outputs CDQ Q 0 X Q Q 1 0 0 1 1 1 1 0 A Challenge
A simple traffic light controller. Want the lights to cycle green-yellow-red.
D Q R C
D Q Y C
D Q G C
Does this work?
Positive-Edge-Triggered D Flip-Flop
Master Slave D D D Q 0 D Q Q D Q
CM C CS C
C
C D
transparent CM D 0 opaque CS Q Positive-Edge-Triggered D Flip-Flop
Master Slave D D D Q 0 D Q Q D Q
CM C CS C
C
C D
transparent CM D 0 opaque CS Q Positive-Edge-Triggered D Flip-Flop
Master Slave D D D Q 0 D Q Q D Q
CM C CS C
C
C D
transparent opaque CM D 0 opaque transparent CS Q Positive-Edge-Triggered D Flip-Flop
Master Slave D D D Q 0 D Q Q D Q
CM C CS C
C
C D
transparent opaque CM D 0 opaque transparent CS Q Positive-Edge-Triggered D Flip-Flop
Master Slave D D D Q 0 D Q Q D Q
CM C CS C
C
C D
transparent opaque transparent CM D 0 opaque transparent opaque CS Q Positive-Edge-Triggered D Flip-Flop
Master Slave D D D Q 0 D Q Q D Q
CM C CS C
C
C D
transparent opaque transparent opaque CM D 0 opaque transparent opaque transparent CS Q The Traffic Light Controller: A second try Let’s try this again with D flip-flops.
D Q R CLK
D Q Y
D Q G
CLK R Y G The Traffic Light Controller: A second try Let’s try this again with D flip-flops.
D Q R CLK
D Q Y
D Q G
CLK R Y G The Traffic Light Controller: A second try Let’s try this again with D flip-flops.
D Q R CLK
D Q Y
D Q G
CLK R Y G The Traffic Light Controller: A second try Let’s try this again with D flip-flops.
D Q R CLK
D Q Y
D Q G
CLK R Y G The Traffic Light Controller: A second try Let’s try this again with D flip-flops.
D Q R CLK
D Q Y
D Q G
CLK R Y G The Traffic Light Controller with Reset
D Q R
RESET D Q Y
D Q G CLK
CLK RESET R Y G The Traffic Light Controller with Reset
D Q R
RESET D Q Y
D Q G CLK
CLK RESET R Y G The Traffic Light Controller with Reset
D Q R
RESET D Q Y
D Q G CLK
CLK RESET R Y G The Traffic Light Controller with Reset
D Q R
RESET D Q Y
D Q G CLK
CLK RESET R Y G The Traffic Light Controller with Reset
D Q R
RESET D Q Y
D Q G CLK
CLK RESET R Y G The Traffic Light Controller with Reset
D Q R
RESET D Q Y
D Q G CLK
CLK RESET R Y G D Flip-Flop with Enable
0 D Q Q D 1
E C D D Q Q E CEDQ C 0 X Q What’s wrong with this ↑ 1 0 0 solution? ↑ 1 1 1 0↑ X X Q 1 X X Q Asynchronous Preset/Clear
PRE D Q
CLR
CLK D PRE CLR Q The Traffic Light Controller w/ Async. Reset
RESET
PRE D Q R CLK CLR
PRE D Q Y
CLR
PRE D Q G
CLR The Synchronous Digital Logic Paradigm
Gates and D
flip-flops only INPUTS OUTPUTS Each flip-flop C driven by the L same clock STATE
Every cyclic CLOCK path contains at least one NEXT STATE flip-flop Cool Sequential Circuits: Shift Registers
AQ0Q1Q2Q3 Q0 Q1 Q2 0 X X X X
A Q3 1 0 X X X 1 1 0 X X
CLK 0 1 1 0 X 1 0 1 1 0 0 1 0 1 1 0 0 1 0 1 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 Universal Shift Register
L 3 2 Q0 D0 1 0 S1 S0 Q3 Q2 Q1 Q0
3 0 0 RQ3 Q2 Q1 2 Q1 0 1 D D D D D1 1 3 2 1 0 0 1 0 Q3 Q2 Q1 Q0 1 1 Q2 Q1 Q0 L 3 2 Q D 2 2 1 S1 S0 Operation 0 0 0 Shift right 3 0 1 Load 2 Q3 1 0 Hold D3 1 R 0 1 1 Shift left
S1 CLK S0 Cool Sequential Circuits: Counters
Cycle through sequences of numbers, e.g.,
00 01 10 11 The 74LS163 Synchronous Binary Counter Flip-Flop Timing
Setup Time: Time before the clock edge after which the data may not change
tsu
CLK D Q Flip-Flop Timing
Setup Time: Time before Hold Time: Time after the the clock edge after which clock edge after which the data may not change the data may change
tsu th
CLK D Q Flip-Flop Timing
Setup Time: Time before Hold Time: Time after the the clock edge after which clock edge after which the data may not change the data may change
tsu th
CLK D Q
tp(min) Minimum Propagation Delay: Time from clock edge to when Q might start changing Flip-Flop Timing
Setup Time: Time before Hold Time: Time after the the clock edge after which clock edge after which the data may not change the data may change
tsu th
CLK D Q
tp(min) Maximum Minimum Propagation Propagation Delay: Delay: Time from tp(max) Time from clock edge clock edge to when Q to when Q might start changing guaranteed stable Timing in Synchronous Circuits
Q C D ··· L ···
CLK
tc
CLK Q D
tc: Clock period. E.g., 10 ns for a 100 MHz clock Timing in Synchronous Circuits
Q C D ··· L ···
CLK
Sufficient Hold Time?
tp(min,FF) tp(min,CL) CLK Q D
Hold time constraint: how soon after the clock edge can D start changing? Min. FF delay + min. logic delay Timing in Synchronous Circuits
Q C D ··· L ···
CLK
Sufficient Setup Time? tp(max,CL) tp(max,FF) CLK Q D
Setup time constraint: when before the clock edge is D guaranteed stable? Max. FF delay + max. logic delay Clock Skew: What Really Happens
Q C D ··· CLK1 L CLK2 ···
CLK
Sufficient Hold Time?
tskew
CLK1
CLK2 Q D tp(min,FF) tp(min,CL)
CLK2 arrives late: clock skew reduces hold time Clock Skew: What Really Happens
Q C D ··· CLK1 L CLK2 ···
CLK
Sufficient Setup Time?
tskew
CLK1
CLK2 Q D tp(max,FF) tp(max,CL)
CLK1 arrives early: clock skew reduces setup time