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15ECL38 Digital-Electronics LM.Pdf APPROVED BY AICTE NEW DELHI, AFFILIATED TO VTU BELGAUM DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING DIGITAL ELECTRONICS LABORATORY LAB MANUAL – 15ECL38 III-SEMESTER 2016-2017 Prepared by: Reviewed by: Approved by: Mrs. A. Deepa Mrs. Kavitha M V Dr. A.A. Powly Thomas Assistant Professor Head of the Department Principal Dept. of ECE Dept. of ECE GCEM GCEM GCEM 81/1, 182/1, Hoodi Village, Sonnenahalli, K.R. Puram, Bengaluru, Karnataka-560048. Contents S.No Title Page No 1. Syllabus 2-2 2. Course objective 2-2 3. Course outcome 3-3 4. Do‟s & Don‟ts 4-4 5. List of experiments 5-46 6. Viva questions 47-48 7. Appendix-1 49-52 1 Syllabus DIGITAL ELECTRONICS LABORATORY [As per Choice Based Credit System (CBCS) scheme] SEMESTER – III (EC/TC) Laboratory Code 15ECL38 IA Marks 20 Number of Lecture 01Hr Tutorial (Instructions) Exam Marks 50 Hours/Week + 02 Hours Laboratory Laboratory Experiments: 1. Verify (a) Demorgan‟s Theorem for 2 variables. (b) The sum-of product and product-of-sum expressions using universal gates. 2. Design and implement (a) Full Adder using basic logic gates. (b) Full subtractor using basic logic gates. 3. Design and implement 4-bit Parallel Adder/ subtractor using IC 7483. 4. Design and Implementation of 4-bit Magnitude Comparator using IC 7485. 5. Realize (a) 4:1 Multiplexer using gates. (b) 3-variable function using IC 74151(8:1MUX). 6. Realize 1:8 Demux and 3:8 Decoder using IC74138. 7. Realize the following flip-flops using NAND Gates. (a) Clocked SR Flip-Flop (b) JK Flip-Flop. 8. Realize the following shift registers using IC7474 (a) SISO (b) SIPO (c) PISO (d)PIPO. 9. Realize the Ring Counter and Johnson Counter using IC7476. 10. Realize the Mod-N Counter using IC7490. 11. Simulate Full- Adder using simulation tool. 12. Simulate Mod-8 Synchronous UP/DOWN Counter using Simulation tool. 2 Course Objectives: This laboratory course enables students to get practical experience in design, realization and verification of Demorgan‟s Theorem, SOP, POS forms Full/Parallel Adders, Subtractors and Magnitude Comparator Multiplexer using logic gates Demultiplexers and Decoders Flip-Flops, Shift registers and Counters. Course Outcomes: On the completion of this laboratory course, the students will be able to: Demonstrate the truth table of various expressions and combinational circuits using logic gates. Design, test and evaluate various combinational circuits such as adders, subtractors, comparators, multiplexers and demultiplexers. Construct flips-flops, counters and shift registers. Simulate full adder and up/down counters. 3 Do’s & Dont’s Do’s Conduct yourself in a responsible manner at all times in the laboratory. Dress properly during a laboratory activity. Long hair, dangling jewelry and loose or baggy clothing are a hazard in the laboratory. Observe good housekeeping practices. Replace the materials in proper place after work to keep the lab area tidy. Dont’s Do not wander around the room, distract other students, startle other students or interfere with the laboratory experiments of others. Do not eat food, drink beverages or chew gum in the laboratory and do not use laboratory glassware as containers for food or beverages. Do not open any irrelevant internet sites on lab computer Do not use a flash drive on lab computers. Do not upload, delete or alter any software on the lab PC. Do not switch on the trainer kit without verifying connection. 4 List of Experiments EXPT. PAGE Name of the Experiment NO. NO. Introduction 7 Study of Logic gates To verify (a) Demorgan‟s Theorem for 2 variables 01 10 (b) The sum-of product and product-of-sum expressions using universal gates To design and implement 02 (a) Full Adder using basic logic gates. 14 (b) Full subtractor using basic logic gates. 03 To design and implement 4-bit Parallel Adder/ subtractor using IC 7483. 18 04 Design and Implementation of 4-bit Magnitude Comparator using IC 7485. 21 To realize (a) 4:1 Multiplexer using gates 05 23 (b) 3-variable function using IC 74151(8:1 MUX) 06 Realize 1:8 Demux and 3:8 Decoder using IC74138. 27 To realise the following flip-flops using NAND Gates. 07 29 (a) Clocked SR Flip-Flop (b) JK Flip-Flop To realize the following shift registers using IC7474 08 32 (a) SISO (b) SIPO (c)PISO 09 To realize the Ring Counter and Johnson Counter using IC7476. 39 10 To realize the Mod-N Counter using IC7490. 42 Simulate Full- Adder using simulation tool. 11 44 12 Simulate Mod-8 Synchronous UP/DOWN Counter using simulation tool. 46 5 INTRODUCTION STUDY OF LOGIC GATES Aim: Truth Table verification of logic gates General Characteristics: a. Pin „Vcc‟ on an I.C is to be connected to a regulated power supply of +5 volts. b. Pin „GND‟ on an I.C is to be connected to the power supply ground. c. = High or „1‟ state implies a voltage between 2.4V and 5.0V in the input state. Procedure: 1. Fix the I.C on the I.C trainer kit. 2. Connections are made as shown, using the pin details of the gates. Toggle switches and LED‟s in the trainer are used as inputs and outputs respectively. 3. Switch on the supply on the trainer and verify the truth table of the gates AND GATE (7408) 1 VCC 14 A Y 13 2 12 B Truth Table 3 11 7408 A B Y=A.B 4 10 5 0 0 0 9 0 1 0 1 0 0 6 7 GND 8 1 1 1 6 OR GATE (7432) A 1 VCC 14 Y 13 2 12 B Truth Table 3 11 7432 A B Y=A+B 4 10 5 0 0 0 9 0 1 1 1 0 1 6 7 GND 8 1 1 1 NOT GATE (7404) Truth Table A Y=Ā 0 1 1 0 7 NAND GATE (7400) A Y B Truth Table A B 0 0 1 0 1 1 1 0 1 1 1 0 NOR GATE (7402) A Y 1 VCC 14 13 B Truth Table 2 3 12 A B 7402 11 4 0 0 1 10 0 1 0 5 6 9 1 0 0 7 GND 8 1 1 0 8 EX-OR GATE (7486) A Y 1 VCC 14 13 2 B 12 Truth Table 3 11 7486 A B Y=AB 4 10 5 0 0 0 9 0 1 1 1 0 1 6 7 GND 8 1 1 0 9 Experiment No: 01 Date: VERIFICATION OF DEMORGAN’S THEOREM & REALIZATION SOP &POS EXPRESSIONS AIM: 1. To verify De-Morgan‟s theorem for two variables 2. To realize sum of product (SOP) and product of sum (POS) expressions using OF SOPuniversal AND gatesPOS. EEEEEEEEXPRESSIONSEXPRESSIONS COMPONENTS REQUIRED: IC Trainer kit, IC 7400, IC 7402 THEORY: 1. De Morgan theorem states that a) AB‟=A‟+B‟ b) (A+B)‟=A‟.B‟ De-Morgan‟s theorem is highly useful to simplify the Boolean expression 2. Gates NAND and NOR are known as universal gates, because any logic gates or Boolean expression can be realized by either NAND or NOR gate alone. Each product term in the SOP expression is called minterm and each sum term in the POS expression is called maxterm. SOP expression can be economically realized using NAND gates and POS expression can be economically realized using NOR gates Realization of SOP expression Using NAND gates i)Use NAND gates for each minterm ii) Use one NAND gate for whole summation Using NOR gates i) Invert all the variables in each minterm ii) Use NOR gates for each minterm having inverted variables iii) Use NOR gate for whole summation iv) Use another NOR gate at the output for inverting. Realization of POS expression Using NOR gates i) Use NOR gates for each maxterm ii) Use one NOR gate for whole multiplication 10 Using NAND gates i) Invert all the variables in each maxterm ii) Use NAND gates for each maxterm having inverted variables iii) Use NAND gate for whole multiplication iv) Use another NAND gate at the output for inverting DEMORGAN’S THEOREM: a) AB‟=A‟+B‟ TRUTH TABLE: A B 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 0 CIRCUIT DIAGRAM: b) (A+B)‟=A‟.B‟ TRUTH TABLE: A B 0 0 1 1 0 1 0 0 1 0 0 0 1 1 0 0 11 CIRCUIT DIAGRAM: b) Realization SOP & POS Expressions: 12 PROCEDURE: 1) Test all the IC packages using digital IC tester. 2) Set up the circuit one by one and verify their truth table. 3) Observe the output corresponding to input combinations and enter it in truth table. RESULT: De-Morgan‟s theorem and postulate of Boolean algebra were verified. Sum of products and product of sum expressions were realized using universal gates 13 Experiment No: 02 (a) Date: FULL ADDER AIM: To realize the Full Adder circuits using basic logic gates and and to verify their truth tables. COMPONENTS REQUIRED: Digital Trainer Kit 01 AND Gate IC 7408 01 OR Gate IC 7432 01 NOT Gate IC 7404 01 NAND Gate (2 Input) IC 7400 03 XOR Gate IC 7486 01 Patch chords / Connecting wires 35 THEORY: Full Adder is a logical circuit, which performs addition of three bits (i.e. addition of two bits with previous carry) and provides an output with a Sum and Carry. It can be built using 2-half adders and an OR gate. PROCEDURE: 1. Connections are made as shown in the logic diagram using the pin details of the gates 2.
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