IJRECE VOL. 6 ISSUE 2 APR.-JUNE 2018 ISSN: 2393-9028 (PRINT) | ISSN: 2348-2281 (ONLINE) Design of Fault Tolerant Full Subtractor Rita Mahajan1, Sharu Bansal2, Deepak Bagai3 Department of Electronics and Communication Engineering Punjab Engineering College (Deemed to be University), Chandigarh, India.
[email protected],
[email protected],
[email protected] Abstract- Now days, the complexity of integrated circuits is extra circuit like generating 2's complement of a number increasing while reliability of the components is decreasing which is to be subtracted. The proposed design is an due to small gates and transistor. One of the impacts of independent subtractor so that addition and subtraction can be technology scaling is more sensitivity to transient and carried out parallel which improves the performance of permanent faults. It is very difficult to detect these faults system. So, the design of faster and reliable subtractor is of offline. The fault tolerant subtractor can detect the faults and great importance in such systems. There are many approaches tolerate the detected faults. There are many fault tolerant full to achieve the fault tolerance in full subtractor. The subtractor which can detect these faults online. So, an efficient researchers have introduced the concept of redundancy to fault tolerant full subtractor is proposed in this paper which detect the fault in full subtractor. But in order to detect and can detect the faults with their exact location and also tolerate tolerate the faults there is need of an efficient fault tolerant full the faults. The proposed subtractor can detect the faults in subtractor. single and multi net.