Final-Del-Lab-Manual-2018-19
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Digital Electronic Circuits
DIGITAL ELECTRONIC CIRCUITS SUBJECT CODE: PEI4I103 B.Tech, Fourth Semester Prepared By Dr. Kanhu Charan Bhuyan Asst. Professor Instrumentation and Electronics Engineering COLLEGE OF ENGINEERING AND TECHNOLOGY BHUBANESWAR B.Tech (E&IE/AE&I) detail Syllabus for Admission Batch 2015-16 PEI4I103- DIGITAL ELECTRONICS University level 80% MODULE – I (12 Hours)1. Number System: Introduction to various number systems and their Conversion. Arithmetic Operation using 1’s and 2`s Compliments, Signed Binary and Floating Point Number Representation Introduction to Binary codes and their applications. (5 Hours) 2. Boolean Algebra and Logic Gates: Boolean algebra and identities, Complete Logic set, logic gates and truth tables. Universal logic gates, Algebraic Reduction and realization using logic gates (3 Hours) 3. Combinational Logic Design: Specifying the Problem, Canonical Logic Forms, Extracting Canonical Forms, EX-OR Equivalence Operations, Logic Array, K-Maps: Two, Three and Four variable K-maps, NAND and NOR Logic Implementations. (4 Hours) MODULE – II (14 Hours) 4. Logic Components: Concept of Digital Components, Binary Adders, Subtraction and Multiplication, An Equality Detector and comparator, Line Decoder, encoders, Multiplexers and De-multiplexers. (5 Hours) 5. Synchronous Sequential logic Design: sequential circuits, storage elements: Latches (SR,D), Storage elements: Flip-Flops inclusion of Master-Slave, characteristics equation and state diagram of each FFs and Conversion of Flip-Flops. Analysis of Clocked Sequential circuits and Mealy and Moore Models of Finite State Machines (6 Hours) 6. Binary Counters: Introduction, Principle and design of synchronous and asynchronous counters, Design of MOD-N counters, Ring counters. Decade counters, State Diagram of binary counters (4 hours) MODULE – III (12 hours) 7. -
EE 2008 Fall 2008 EE 231 Exam 3 November 19, 2008 Name: Show All Work. Partial Credit Will Be Given. No Credit Will Be Given If
EE 2008 Fall 2008 EE 231 Exam 3 November 19, 2008 Name: Show all work. Partial credit will be given. No credit will be given if an answer appears with no supporting work. 1. Circle the correct answer to questions (a) through (i); give a numerical answer for (j) and (k): (a) A movement of data from right (least significant bit) to left (most significant bit) is what type of shift: A. Right B. Left C. Parallel D. Finite state machine (b) A serial shift register with non-complemented feedback from the output of the last flip-flop to the input of the first is called a: A. Binary Counter B. Gray Code Counter C. Johnson Counter D. Ring Counter (c) A finite state machine in which the output depends on the present state and the present inputs is called a: A. Mealy machine B. Mannie machine C. Moore machine D. Vending machine (d) A finite state machine in which the output depends only on the present state is called a: A. Mealy machine B. Mannie machine C. Moore machine D. Vending machine VCC Q VCC (e) The circuit shown above is used for what purpose? A. Counter B. Pulser C. Shift register D. Switch debounce (f) The multiplexer is an example of what type of Boolean circuit? A. Sequential B. Combinational C. Moore machine D. Analog (g) Which sequential device has an output that is only dependent on the level of the inputs? A. Latch B. Multiplexer C. Flip-Flop D. Clock Tree 1 EE 2008 Fall 2008 module ex3 (input clock, clear, load, x, output reg y) always @(posedge clock, negedge clear) if (clear == 1’b0) y <= 0; else if (load == 1’b0) y <= x; else y <= y; endmodule (h) For the Verilog code above, what type on input is clear? A. -
Laboratory Sequence Circuits
Laboratory Sequence Circuits Digital Design IE1204/5 Attention! To access the laboratory experiment you must have: • booked a lab time in the reservation system (Daisy). • completed your personal knowledge control on the Web (Web-quiz). • done all preparation tasks mentioned in the lab booklet. If a preparation task has this "label", you must also be prepared to to present an oral solution for your peers at the lab. During the lab you work in groups of two, but both students are responsible individually for their preparation and implementation. Booth students should bring their lab booklets. This frontpage is used as your receipt that the lab is completed. Save the receipt until you have received the full course registered in the database (Ladok). Since this is your receipt you must fill in the table with ink. 1 Introduction This lab is about sequence circuits in synchronously clocked applications. We continue to use standard CMOS circuits. It's the CMOS technology that has enabled extremely low-power battery-operated portable devices. CMOS gates only consume power at the clock pulse edges! (In the lab equipment it is the LEDs that are the big "power consumers"). On the breadboard you will connect and measure some basic sequence circuits like latches and clocked D flip-flops. With a systematic method you construct a state machine, a controlled counter, which you then test in the laboratory. Other sequence circuits with simple structure, such as feedback shift registers, can often be examined directly. The task will be to "control" such a sequence circuit to run through various cycles. -
A New Approach to the Snake-In-The-Box Problem
462 ECAI 2012 Luc De Raedt et al. (Eds.) © 2012 The Author(s). This article is published online with Open Access by IOS Press and distributed under the terms of the Creative Commons Attribution Non-Commercial License. doi:10.3233/978-1-61499-098-7-462 A New Approach to the Snake-In-The-Box Problem David Kinny1 Abstract. The “Snake-In-The-Box” problem, first described more Research on the SIB problem initially focused on applications in than 50 years ago, is a hard combinatorial search problem whose coding [14]. Coils are spread-k circuit codes for k =2, in which solutions have many practical applications. Until recently, techniques n-words k or more positions apart in the code differ in at least k based on Evolutionary Computation have been considered the state- bit positions [12]. (The well-known Gray codes are spread-1 circuit of-the-art for solving this deterministic maximization problem, and codes.) Longest snakes and coils provide the maximum number of held most significant records. This paper reviews the problem and code words for a given word size (i.e., hypercube dimension). prior solution techniques, then presents a new technique, based on A related application is in encoding schemes for analogue-to- Monte-Carlo Tree Search, which finds significantly better solutions digital converters including shaft (rotation) encoders. Longest SIB than prior techniques, is considerably faster, and requires no tuning. codes provide greatest resolution, and single bit errors are either recognised as such or map to an adjacent codeword causing an off- 1 INTRODUCTION by-one error. -
NOTE on GRAY CODES for PERMUTATION LISTS Seymour
PUBLICATIONS DE L’INSTITUT MATHEMATIQUE´ Nouvelle s´erie,tome 78(92) (2005), 87–92 NOTE ON GRAY CODES FOR PERMUTATION LISTS Seymour Lipschutz, Jie Gao, and Dianjun Wang Communicated by Slobodan Simi´c Abstract. Robert Sedgewick [5] lists various Gray codes for the permutations in Sn including the classical algorithm by Johnson and Trotter. Here we give an algorithm which constructs many families of Gray codes for Sn, which closely follows the construction of the Binary Reflexive Gray Code for the n-cube Qn. 1. Introduction There are (n!)! ways to list the n! permutations in Sn. Some such permutation lists have been generated by a computer, and some such permutation lists are Gray codes (where successive permutations differ by a transposition). One such famous Gray code for Sn is by Johnson [4] and Trotter [6]. In fact, each new permutation in the Johnson–Trotter (JT ) list for Sn is obtained from the preceding permutation by an adjacent transposition. Sedgewick [5] gave a survey of various Gray codes for Sn in 1977. Subsequently, Conway, Sloane and Wilks [1] gave a new Gray code CSW for Sn in 1989 while proving the existence of Gray codes for the reflection groups. Recently, Gao and Wang [2] gave simple algorithms, each with an efficient implementation, for two new permutation lists GW1 and GW2 for Sn, where the second such list is a Gray code for Sn. The four lists, JT , CSW , GW1 and GW2, for n = 4, are pictured in Figure 1. This paper gives an algorithm for constructing many families of Gray codes for Sn which uses an idea from the construction of the Binary Reflected Gray Code (BRGC) of the n-cube Qn. -
Other Binary Codes (3A)
Other Binary Codes (3A) Young Won Lim 1/3/14 Copyright (c) 2011-2013 Young W. Lim. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the section entitled "GNU Free Documentation License". Please send corrections (or suggestions) to [email protected]. This document was produced by using OpenOffice and Octave. Young Won Lim 1/3/14 Coding A code is a rule for converting a piece of information (for example, a letter, word, phrase, or gesture) into another form or representation (one sign into another sign), not necessarily of the same type. In communications and information processing, encoding is the process by which information from a source is converted into symbols to be communicated. Decoding is the reverse process, converting these code symbols back into information understandable by a receiver. Young Won Lim Other Binary Codes (4A) 3 1/3/14 Character Coding ASCII code BCD (Binary Coded Decimal) definitions for 128 characters: Number characters (0-9) 33 non-printing control characters (many now obsolete) 95 printable charactersi Young Won Lim Other Binary Codes (4A) 4 1/3/14 Representation of Numbers Fixed Point Number representation ● 2's complement +1234 ● 1's complement 0 -582978 coding ● sign-magnitude Floating Point Number representation +23.84380 ● IEEE 754 -1.388E+08 -
Loopless Gray Code Enumeration and the Tower of Bucharest
Loopless Gray Code Enumeration and the Tower of Bucharest Felix Herter1 and Günter Rote1 1 Institut für Informatik, Freie Universität Berlin Takustr. 9, 14195 Berlin, Germany [email protected], [email protected] Abstract We give new algorithms for generating all n-tuples over an alphabet of m letters, changing only one letter at a time (Gray codes). These algorithms are based on the connection with variations of the Towers of Hanoi game. Our algorithms are loopless, in the sense that the next change can be determined in a constant number of steps, and they can be implemented in hardware. We also give another family of loopless algorithms that is based on the idea of working ahead and saving the work in a buffer. 1998 ACM Subject Classification F.2.2 Nonnumerical Algorithms and Problems Keywords and phrases Tower of Hanoi, Gray code, enumeration, loopless generation Contents 1 Introduction: the binary reflected Gray code and the Towers of Hanoi 2 1.1 The Gray code . .2 1.2 Loopless algorithms . .2 1.3 The Tower of Hanoi . .3 1.4 Connections between the Towers of Hanoi and Gray codes . .4 1.5 Loopless Tower of Hanoi and binary Gray code . .4 1.6 Overview . .4 2 Ternary Gray codes and the Towers of Bucharest 5 3 Gray codes with general radixes 7 4 Generating the m-ary Gray code with odd m 7 5 Generating the m-ary Gray code with even m 9 arXiv:1604.06707v1 [cs.DM] 22 Apr 2016 6 The Towers of Bucharest++ 9 7 Simulation 11 8 Working ahead 11 8.1 An alternative STEP procedure . -
Draft Chapter on the ENIAC Circuits
CHAPTER 1 CIRCUITS Section 1. Vacuum Tube Basics 1. Introduction During the 1940s, when the ENIAC was under construction, the basic principles of vacuum tubes and their circuits were familiar to most electrical engineers. Today, however, that knowledge is far less common. For that reason, we begin our discussion of the circuit design of the ENIAC with a brief look at how vacuum tubes work and how they are used as switching elements in circuits. Conversely, the reader is expected to be somewhat familiar with the functions of other circuit components, especially resistors and capacitors. 2. Tube Structure As the name implies a vacuum tube operates in a vacuum. This allows the electrons (e−) to flow freely between the electrodes in the tube without being impeded by gas molocules. That vacuum is usually contained in a glass envelope, though sometimes we find them in metal cans. These devices contain at least two electrodes, and those that are used in logic circuits that we study here all have at least three. a. Cathode. The cathode is the electrode from which the electrons origi- nate. To cause it to give off electrons, its temperature is raised with a heater. In some tubes the heater is the cathode, but for the tubes used in the logic of the ENIAC, the heater is inside a small metal can. This can is coated with a mixture of oxides, such as those of barium and strontium, that efficiently emit electrons at lower temperatures than the heater itself. b. Plate. The plate (or sometimes anode) is physically designed as a metal can surrounding the cathode with some free space between them. -
Algorithms for Generating Binary Reflected Gray Code Sequence: Time Efficient Approaches
2009 International Conference on Future Computer and Communication Algorithms for Generating Binary Reflected Gray Code Sequence: Time Efficient Approaches Md. Mohsin Ali, Muhammad Nazrul Islam, and A. B. M. Foysal Dept. of Computer Science and Engineering Khulna University of Engineering & Technology Khulna – 9203, Bangladesh e-mail: [email protected], [email protected], and [email protected] Abstract—In this paper, we propose two algorithms for Coxeter groups [4], capanology (the study of bell-ringing) generating a complete n-bit binary reflected Gray code [5], continuous space-filling curves [6], classification of sequence. The first one is called Backtracking. It generates a Venn diagrams [7]. Today, Gray codes are widely used to complete n-bit binary reflected Gray code sequence by facilitate error correction in digital communications such as generating only a sub-tree instead of the complete tree. In this digital terrestrial television and some cable TV systems. approach, both the sequence and its reflection for n-bit is In this paper, we present the derivation and generated by concatenating a “0” and a “1” to the most implementation of two algorithms for generating the significant bit position of the n-1 bit result generated at each complete binary reflected Gray code sequence leaf node of the sub-tree. The second one is called MOptimal. It () ≤ ≤ n − is the modification of a Space and time optimal approach [8] G i ,0 i 2 1 , for a given number of bits n. We by considering the minimization of the total number of outer evaluate the performance of these algorithms and other and inner loop execution for this purpose. -
GRAPHS INDUCED by GRAY CODES 1. Introduction an N-Bit
GRAPHS INDUCED BY GRAY CODES ELIZABETH L. WILMER AND MICHAEL D. ERNST Abstract. We disprove a conjecture of Bultena and Ruskey [1], that all trees which are cyclic graphs of cyclic Gray codes have diameter 2 or 4, by producing codes whose cyclic graphs are trees of arbitrarily large diameter. We answer affirmatively two other questions from [1], showing that strongly Pn Pn- compatible codes exist and that it is possible for a cyclic code to induce× a cyclic digraph with no bidirectional edge. A major tool in these proofs is our introduction of supercomposite Gray codes; these generalize the standard reflected Gray code by allowing shifts. We find supercomposite Gray codes which induce large diameter trees, but also show that many trees are not induced by supercomposite Gray codes. We also find the first infinite family of connected graphs known not to be induced by any Gray code | trees of diameter 3 with no vertices of degree 2. 1. Introduction n An n-bit Gray code B = (b1; b2;:::; bN ), N = 2 , lists all the binary n-tuples (\codewords") so that consecutive n-tuples differ in one bit. In a cyclic code, the first and last n-tuples also differ in one bit. Gray codes can be viewed as Hamiltonian paths on the hypercube graph; cyclic codes correspond to Hamiltonian cycles. Two Gray codes are isomorphic when one is carried to the other by a hypercube isomorphism. The transition sequence τ(B) = (τ1; τ2; : : : ; τN 1) of an n-bit Gray code B lists − the bit positions τi [n] = 1; 2; : : : ; n where bi and bi+1 differ. -
Design and Implementation of an On-Chip Test Generation Scheme
Available online at www.sciencedirect.com ScienceDirect Procedia Computer Science 46 ( 2015 ) 1409 – 1416 International Conference on Information and Communication Technologies (ICICT 2014) Design and Implementation of an On-Chip Test Generation Scheme Based on Reconfigurable Run-Time Programmable and Multiple Twisted-Ring Counters Aida S Tharakana*, Binu K Mathewb a,bDept. of Electronics and Communication, Saintgits College of Engineering, Kottayam-686532, India Abstract Built-in-self-test (BIST) has emerged as a very effective solution to VLSI testing problems. Related work based on single fixed- order twisted-ring-counter design requires longer testing time to achieve high fault coverage and large storage space to store the seeds and the control data. By using multiple programmable twisted-ring-counters (PTRC), a considerable reduction in test application cycles were achieved. In this paper, an on-chip test generation scheme based on reconfigurable run-time programmable multiple twisted-ring-counters is proposed to generate more number of different test patterns based on the requirements. The design was modeled in VHDL and simulated and synthesized using Xilinx ISE 14.2. ©© 2015 2014 The The Authors. Authors. Published Published by by Elsevier Elsevier B.V. B.V. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/). Peer-review under responsibility of organizing committee of the International Conference on Information and Communication Peer-review under responsibility of organizing committee of the International Conference on Information and Communication Technologies (ICICT 2014). Technologies (ICICT 2014) Keywords: Fault Coverage;Logic BIST;Reconfiguration;Twisted-ring-counters 1. -
Lab Manual Exp Code Converter.Pdf
Hybrid Electronics Laboratory Design and Simulation of Various Code Converters Aim: To Design and Simulate Binary to Gray, Gray to Binary , BCD to Excess 3, Excess 3 to BCD code converters. Objectives: 1. To understand different codes 2. To design various Code converters using logic gates 3. To simulate various code converters 4. To understand the importance of code converters in real life applications Theory Binary Codes A symbolic representation of data/ information is called code. The base or radix of the binary number is 2. Hence, it has two independent symbols. The symbols used are 0 and 1. A binary digit is called as a bit. A binary number consists of sequence of bits, each of which is either a 0 or 1. Each bit carries a weight based on its position relative to the binary point. The weight of each bit position is one power of 2 greater than the weight of the position to its immediate right. e. g. of binary number is 100011 which is equivalent to decimal number 35. BCD Codes Numeric codes represent numeric information i.e. only numbers as a series of 0’s and 1’s. Numeric codes used to represent decimal digits are called Binary Coded Decimal (BCD) codes. A BCD code is one, in which the digits of a decimal number are encoded-one at a time into group of four binary digits. There are a large number of BCD codes in order to represent decimal digits0, 1, 2 …9, it is necessary to use a sequence of at least four binary digits.