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Validated Products List, 1995 No. 3: Programming Languages, Database
NISTIR 5693 (Supersedes NISTIR 5629) VALIDATED PRODUCTS LIST Volume 1 1995 No. 3 Programming Languages Database Language SQL Graphics POSIX Computer Security Judy B. Kailey Product Data - IGES Editor U.S. DEPARTMENT OF COMMERCE Technology Administration National Institute of Standards and Technology Computer Systems Laboratory Software Standards Validation Group Gaithersburg, MD 20899 July 1995 QC 100 NIST .056 NO. 5693 1995 NISTIR 5693 (Supersedes NISTIR 5629) VALIDATED PRODUCTS LIST Volume 1 1995 No. 3 Programming Languages Database Language SQL Graphics POSIX Computer Security Judy B. Kailey Product Data - IGES Editor U.S. DEPARTMENT OF COMMERCE Technology Administration National Institute of Standards and Technology Computer Systems Laboratory Software Standards Validation Group Gaithersburg, MD 20899 July 1995 (Supersedes April 1995 issue) U.S. DEPARTMENT OF COMMERCE Ronald H. Brown, Secretary TECHNOLOGY ADMINISTRATION Mary L. Good, Under Secretary for Technology NATIONAL INSTITUTE OF STANDARDS AND TECHNOLOGY Arati Prabhakar, Director FOREWORD The Validated Products List (VPL) identifies information technology products that have been tested for conformance to Federal Information Processing Standards (FIPS) in accordance with Computer Systems Laboratory (CSL) conformance testing procedures, and have a current validation certificate or registered test report. The VPL also contains information about the organizations, test methods and procedures that support the validation programs for the FIPS identified in this document. The VPL includes computer language processors for programming languages COBOL, Fortran, Ada, Pascal, C, M[UMPS], and database language SQL; computer graphic implementations for GKS, COM, PHIGS, and Raster Graphics; operating system implementations for POSIX; Open Systems Interconnection implementations; and computer security implementations for DES, MAC and Key Management. -
The Design and Verification of the Alphastation 600 5-Series Workstation by John H
The Design and Verification of the AlphaStation 600 5-series Workstation by John H. Zurawski, John E. Murray, and Paul J. Lemmon ABSTRACT The AlphaStation 600 5-series workstation is a high-performance, uniprocessor design based on the Alpha 21164 microprocessor and on the PCI bus. Six CMOS ASICs provide high-bandwidth, low-latency interconnects between the CPU, the main memory, and the I/O subsystem. The verification effort used directed, pseudorandom testing on a VERILOG software model. A hardware-based verification technique provided a test throughput that resulted in a significant improvement over software tests. This technique currently involves the use of graphics cards to emulate generic DMA devices. A PCI hardware demon is under development to further enhance the capability of the hardware-based verification. INTRODUCTION The high-performance AlphaStation 600 5-series workstation is based on the fastest Alpha microprocessor to date -- the Alpha 21164.[1] The I/O subsystem uses the 64-bit version of the Peripheral Component Interconnect (PCI) and the Extended Industry Standard Architecture (EISA) bus. The AlphaStation 600 supports three operating systems: Digital UNIX (formerly DEC OSF/1), OpenVMS, and Microsoft's Windows NT. This workstation series uses the DECchip 21171 chip set designed and built by Digital. These chips provide high-bandwidth, low-latency interconnects between the CPU, the main memory, and the PCI bus. This paper describes the architecture and features of the AlphaStation 600 5-series workstation and the DECchip 21171 chip set. The system overview is first presented, followed by a detailed discussion of the chip set. The paper then describes the cache and memory designs, detailing how the memory design evolved from the workstation's requirements. -
1992 Cern School of Computing
ORGANISATION EUROPEENNE POUR LA RECHERCHE NUCLEAIRE CERN EUROPEAN ORGANIZATION FOR NUCLEAR RESEARCH 1992 CERN SCHOOL OF COMPUTING Scuola Superiore G. Reiss Romoli, L'Aquila, Italy 30 August-12 September 1992 PROCEEDINGS Editor: C. Verkerk GENEVA 1993 © Copyright CERN, Genève, 1993 Propriété littéraire et scientifique réservée Literary and scientific copyrights reserved in pour tous les paya < 11» inonde. Ce document ne all countries of the world. This report, or peut être reproduit ou traduit en tout ou en any part of it. may not be reprinted or trans partie sans l'autorisation écrite du Directeur lated without written permission ol the copy général du CERN, titulaire du droit d'auteur. right holder, the Director-General of CERN. Dans les cas appropriés, et s'il s'agit d'utiliser However, permission will be freely granted for le document à des fins non commerciales, cette appropriate non-commercial use. autorisation sera volontiers accordée. If any patentable invention or registrable Le CERN ne revendique pas la propriété des design is described in the report. CERN makes inventions brevetables et dessins ou modèles no claim to property rights in it but offers i( susceptibles de dépôt qui pourraient être for the free use of research institutions, man décrits dans le présent document ; ceux-ci peu ufacturers and others. CERN, however, may vent être librement utilisés par les instituts de oppose any attempt by a user to claim any recherche, les industriels et autres intéressés. proprietary or patent rights in such inventions Cependant, le CERN se réserve le droit de or designs as may be described in the present s'opposer à toute revendication qu'un usager document. -
DB2SPI B.03.02 User's Guide
HP OpenView Tiering Matrix For HP and Partner use Page 1 of 5 Updated: 18 August 2006 (For OV Performance Agent, OV Operations Agent, SPIs, OVIS, OVAI, GlancePlus and GlancePlus Pak) Usage Notes 1. This matrix is a tool for identifying what tier a system is in. NOT ALL of the listed products are supported on all systems in this matrix. Please read this introduction carefully and also look at the footnotes on each page provided for special cases. 2. Single-user Systems (Unix): For OV Operations Agents, Performance Agents and SPIs a workstation used as a single-user system is classified as a Tier 0 system. 3. Desktop Systems (Windows, Linux, Netware): Professional Desktop License is for use on a single-user Intel-based PC that is running Windows NT Workstation, Windows 2000 Professional, Windows XP Professional, RedHat Linux or Novell NetWare. 4. The tiering below is valid for all systems running AIX, HP-UX, Tru64 UNIX, Digital Unix, Linux, Sun Solaris, MS Windows and Novell NetWare. All other systems are tiered / priced using separate product numbers as follows: o OV Multi-vendor Agent - B7442AA, o OV Multi-vendor Operations Agent - B7443AA, o OV Multi-vendor Performance Agent - B7444AA. 5. Multiple Partitions (Virtual Servers): a. UNIX-based If an OV Agent is being ordered for an UNIX-based system which has multiple partitions / domains (virtual systems) a ‘password request form’ specifying the number of ‘additional’ partitions/domains has to be completed and sent to the password delivery center. There is one license required based upon the tiering of the hosting system and (n-1) free additional Tier 1 licenses for the additional partitions/domains. -
Binary Translation 1 Abstract Binary Translation Is a Technique Used To
Binary Translation 1 Abstract Binary translation is a technique used to change an executable program for one computer architecture and operating system into an executable program for a different computer architecture and operating system. Two binary translators are among the migration tools available for Alpha AXP computers: VEST translates OpenVMS VAX binary images to OpenVMS AXP images; mx translates ULTRIX MIPS images to DEC OSF/1 AXP images. In both cases, translated code usually runs on Alpha AXP computers as fast or faster than the original code runs on the original architecture. In contrast to other migration efforts in the industry, the VAX translator reproduces subtle CISC behavior on a RISC machine, and both open-ended translators provide good performance on dynamically modified programs. Alpha AXP binary translators are important migration tools - hundreds of translated OpenVMS VAX and ULTRIX MIPS images currently run on Alpha AXP systems. When Digital started to design the Alpha AXP architecture in the fall of 1988, the Alpha AXP team was concerned about how to run existing VAX code and soon-to-exist MIPS code on the new Alpha AXP computers.[1,2] To take full advantage of the performance capability of a new computer architecture, an application must be ported by rebuilding, using native compilers. For a single program written in a standard programming language, this is a matter of recompile and run. A complex software application, however, can be built from hundreds of source pieces using dozens of tools. A native port of such an application is possible only when all parts of the build path are running on the new architecture. -
Alpha and VAX Comparison Based on Industry-Standard Benchmark
Alpha and VAX Comparison based on Industry-standard Benchmark Results Digital Equipment Corporation December 1994 EC-N3909-10 Version 3.0 December 1994 The information in this document is subject to change without notice and should not be construed as a commitment by Digital Equipment Corporation. Digital Equipment Corporation assumes no responsibility for any errors that may appear in this document. Digital conducts its business in a manner that conserves the environment and protects the safety and health of its employees, customers, and the community. Restricted Rights: Use, duplication, or disclosure by the U.S. Government is subject to restrictions as set forth in subparagraph (c) (1 )(ii) of the Rights in Technical Data and Computer Software clause at DFARS 252.227 7013. Copyright© 1994 Digital Equipment Corporation All rights reserved. Printed in U.S.A. The following are trademarks of Digital Equipment Corporation: AlphaServer, AlphaStation, AlphaGeneration, DEC, OpenVMS, VMS, ULTRIX, and the DIGITAL logo. The following are third-party trademarks: MIPS is a trademark of MIPS Computer Systems, Inc. TPC-A is a trademark of the Transaction Processing Performance Council. INFORMIX is a registered trademark of lnformix Software, Inc. OSF/1 is a registered trademark of the Open Software Foundation, Inc. ORACLE is a registered trademark of Oracle Corporation. SPEC, SPECfp92, and SPECratio are trademarks of Standard Performance Evaluation Corporation. MIPS is a trademark of MIPS Computer Systems, Inc. All other trademarks and registered -
The Community Is the Infrastructure: a Short Discussion of the Petsc Community
The Community is the Infrastructure: A Short Discussion of the PETSc Community Mark Adams1, Jed Brown2, Satish Balay3, Victor Eijkhout4, Jacob Faibussowitsch5, Fande Kong6, Matthew Knepley7, Scott Kruger8, Oana Marin3, Richard Tran Mills3, Todd Munson3, Patrick Sanan9, Barry F. Smith10, Hong Zhang11, Hong Zhang3, and Junchao Zhang3 1Lawrence Berkeley National Laboratory 2University of Colorado at Boulder 3Argonne National Laboratory 4The University of Texas at Austin 5University of Illinois at Urbana-Champaign 6Idaho National Laboratory 7University of New York at Buffalo 8Tech-X Corporation 9ETH Zurich 10Argonne Associate, Argonne National Laboratory 11Illinois Institute of Technology July 5, 2021 Abstract Hard and soft infrastructure work in tandem to accomplish a particular enterprise. Soft infras- tructure { the formal and informal culture, institutions, standards, practices, and procedures that support an enterprise { is often more important to human endeavors than hard infrastructure. For example, a highway system's hard infrastructure (e.g., the roads) could not satisfy its enterprise { effective transportation | without the corresponding soft infrastructure of regulations, policing, driver habits, maintenance crews, and so forth. The relative cost and importance of the different aspects of infrastructure evolves, particularly during the development stages, from planning, to construction, to commissioning, operation, maintenance, and upgrading. The design, development, support, and dissemination of computer software is an archetypal example of soft infrastructure, regularly being the tail that wags the dog of computer hardware (prototypical hard infrastructure). Quantifying soft infrastructure is more difficult than hard in- frastructure. Thus, it is often ignored or under-emphasized when analyzing or proposing changes to human-developed systems. In particular, government understanding and funding of scientific soft infrastructure lags well behind that of hard infrastructure (for example, experimental devices such as accelerators). -
VAX 4000 Model 100 to DEC 3000 Model 400S AXP Upgrade Instr
VAX 4000 Model 100 to DEC 3000 Model 400S AXP Upgrade Instructions MLO-010669 Part Number: EK-VX44S-IN. A01 Options You Can Upgrade Can Cannot Upgrade Upgrade Disks: RZ23L*, RZ24L* RZ57 RZ24* RZ25* RZ26* RZ55* RZ56* RZ58* Drives: RRD42** B400X RWZ01** DSSI Devices RX26* R400X TLZ04 TF85 TLZ06** TK50 TSZ05* TK70 TSZ07* TKZ08 TZ30 TSV05 TZ85* TU81 TZK10 Expansion Boxes: SZ03 SZ12 SZ16 Memory: None *Supported only in external device. **Including tabletop device. Check Components Shipped Your shipment should contain the following two kits. If you are missing any of these components, contact your Digital sales representative. System Kit: Ethernet Loopback Connector System Unit SCSI Documentation Terminator Antistatic Modem Loopback Wrist Strap Connector Printer Port Terminator System Power Cord Network Label Screwdriver Accessory Kit: Upgrade xxxxxxx xxxxxxxxxxx Card xxx Rubber Grommets RX26 Brackets Metal Support Plate TZ30 RFI Return Shield Address Label MLO-010670 Remove the System Unit Cover Follow these steps to remove the system unit cover: 1. Turn off the system by pressing the on/off switch to the off (O) position. 2. Disconnect the cables, connectors, and terminators from the system unit. 3. Loosen the two captive screws on the back of the system unit. B 1 A 0 0 Captive Screws MLO-010744 4. Slide the cover forward and lift it up from the system unit. Set the cover aside. Remove Fixed Disk Drives Note: The DEC 3000 system can hold two fixed disk drives and one removable-media drive. 1. Press and hold the spring clip that locks the disk drive in position. 2. -
Chapter 4 Editors and Debugging Systems
Chapter 4 Editors and Debugging Systems This Chapter gives you… Text editors Interactive Debugging Systems 4.0 Introduction An Interactive text editor has become an important part of almost any computing environment. Text editor acts as a primary interface to the computer for all type of “knowledge workers” as they compose, organize, study, and manipulate computer-based information. An interactive debugging system provides programmers with facilities that aid in testing and debugging of programs. Many such systems are available during these days. Our discussion is broad in scope, giving the overview of interactive debugging systems – not specific to any particular existing system. 4.1 Text Editors An Interactive text editor has become an important part of almost any computing environment. Text editor acts as a primary interface to the computer for all type of “knowledge workers” as they compose, organize, study, and manipulate computer-based information. A text editor allows you to edit a text file (create, modify etc…). For example the Interactive text editors on Windows OS - Notepad, WordPad, Microsoft Word, and text editors on UNIX OS - vi, emacs, jed, pico. Normally, the common editing features associated with text editors are, Moving the cursor, Deleting, Replacing, Pasting, Searching, Searching and replacing, Saving and loading, and, Miscellaneous(e.g. quitting). 4.1.1 Overview of the editing process An interactive editor is a computer program that allows a user to create and revise a target document. Document includes objects such as computer diagrams, text, equations tables, diagrams, line art, and photographs. Here we restrict to text editors, where character strings are the primary elements of the target text. -
Personal Decstation 5000 User's Guide
Personal DECstation 5000 User’s Guide Order Number: EK–PM30E–RB.003 Digital Equipment Corporation Maynard, Massachusetts Second Printing, Sept, 1992 The information in this document is subject to change without notice and should not be construed as a commitment by Digital Equipment Corporation. Digital Equipment Corporation assumes no responsibility for any errors that may appear in this document. The software described in this document is furnished under a license and may be used or copied only in accordance with the terms of such license. All rights reserved. Printed in U.S.A. © Digital Equipment Corporation 1992. The postpaid Reader’s Comments forms at the end of this document request your critical evaluation to assist in preparing future documentation. The following are trademarks of Digital Equipment Corporation: DEC, DECconnect, DECnet, DECstation, DECsystem, DECUS, DESTA, ThinWire, Turbochannel, ULTRIX, ULTRIX-32, and the DIGITAL logo. Motif is a trademark of the Open Software Foundation, Inc. MS–DOS is a registered trademark of Microsoft Corporation. PostScript is a registered trademark of Adobe Systems, Inc. VELCRO is a trademark of VELCRO USA, Inc. FCC NOTICE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instruction manual, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to cause harmful interference, in which case the user will be required to correct the interference at his own expense. -
Computer Architectures an Overview
Computer Architectures An Overview PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 25 Feb 2012 22:35:32 UTC Contents Articles Microarchitecture 1 x86 7 PowerPC 23 IBM POWER 33 MIPS architecture 39 SPARC 57 ARM architecture 65 DEC Alpha 80 AlphaStation 92 AlphaServer 95 Very long instruction word 103 Instruction-level parallelism 107 Explicitly parallel instruction computing 108 References Article Sources and Contributors 111 Image Sources, Licenses and Contributors 113 Article Licenses License 114 Microarchitecture 1 Microarchitecture In computer engineering, microarchitecture (sometimes abbreviated to µarch or uarch), also called computer organization, is the way a given instruction set architecture (ISA) is implemented on a processor. A given ISA may be implemented with different microarchitectures.[1] Implementations might vary due to different goals of a given design or due to shifts in technology.[2] Computer architecture is the combination of microarchitecture and instruction set design. Relation to instruction set architecture The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address and data formats among other things. The Intel Core microarchitecture microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is usually represented as (more or less detailed) diagrams that describe the interconnections of the various microarchitectural elements of the machine, which may be everything from single gates and registers, to complete arithmetic logic units (ALU)s and even larger elements. -
Co-Ordination of the Nuclear Reaction Data Centers
XA9743324 Internotional Atomic Energy Agency INDC(NDS)-360 Distr. G,NC I N DC INTERNATIONAL NUCLEAR DATA COMMITTEE Co-ordination of the Nuclear Reaction Data Centers Report on an IAEA Advisory Group Meeting hosted by the U.S. National Nuclear Data Center on behalf of the U.S. Government Brookhaven, 3-7 June 1996 Edited by O. Schwerer and H.D. Lemmel November 1996 IAEA NUCLEAR DATA SECTION, WAGRAMERSTRASSE 5, A-1400 VIENNA Printed by the IAEA in Austria November 1996 INDC(NDS)-360 Distr. G,NC Co-ordination of the Nuclear Reaction Data Centers Report on an IAEA Advisory Group Meeting hosted by the U.S. National Nuclear Data Center on behalf of the U.S. Government Brookhaven, 3-7 June 1996 Abstract: This report summarizes the 1996 co-ordination meeting in Brookhaven, U.S.A., of the national and regional nuclear reaction data centers, convened by the IAEA at regular intervals. The main topics are - the international exchange of nuclear reaction data by means of the "EXFOR" system, and the further development of this system, the "CINDA" system as an international index and bibliography to neutron reaction data, the sharing of the workload for speedy and reliable nuclear data compilation and data center services, the exchange and documentation of evaluated data libraries in "ENDF" format, the rapid advances of online electronic information technologies, with the goal of rendering data center services to data users in IAEA Member States by means of computer retrievals, online services and printed materials. The scope of data covers microscopic cross-sections and related parameters of nuclear reactions induced by neutrons, charged-particles and photons.