Binary Translation 1 Abstract Binary Translation Is a Technique Used To
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Binary Translation Using Peephole Superoptimizers
Binary Translation Using Peephole Superoptimizers Sorav Bansal Alex Aiken Computer Systems Lab Computer Systems Lab Stanford University Stanford University [email protected] [email protected] Abstract tecture performance for compute-intensive applica- We present a new scheme for performing binary trans- tions. lation that produces code comparable to or better than 2. Because the instruction sets of modern machines existing binary translators with much less engineering tend to be large and idiosyncratic, just writing the effort. Instead of hand-coding the translation from one translation rules from one architecture to another instruction set to another, our approach automatically is a significant engineering challenge, especially if learns translation rules using superoptimization tech- there are significant differences in the semantics of niques. We have implemented a PowerPC-x86 binary the two instruction sets. This problem is exacer- translator and report results on small and large compute- bated by the need to perform optimizations wher- intensive benchmarks. When compared to the native ever possible to minimize problem (1). compiler, our translated code achieves median perfor- mance of 67% on large benchmarks and in some small 3. Because high-performancetranslations must exploit stress tests actually outperforms the native compiler. We architecture-specific semantics to maximize perfor- also report comparisons with the open source binary mance, it is challenging to design a binary translator translator Qemu and a commercial tool, Apple’s Rosetta. that can be quickly retargeted to new architectures. We consistently outperform the former and are compara- One popular approach is to design a common inter- ble to or faster than the latter on all but one benchmark. -
Validated Products List, 1995 No. 3: Programming Languages, Database
NISTIR 5693 (Supersedes NISTIR 5629) VALIDATED PRODUCTS LIST Volume 1 1995 No. 3 Programming Languages Database Language SQL Graphics POSIX Computer Security Judy B. Kailey Product Data - IGES Editor U.S. DEPARTMENT OF COMMERCE Technology Administration National Institute of Standards and Technology Computer Systems Laboratory Software Standards Validation Group Gaithersburg, MD 20899 July 1995 QC 100 NIST .056 NO. 5693 1995 NISTIR 5693 (Supersedes NISTIR 5629) VALIDATED PRODUCTS LIST Volume 1 1995 No. 3 Programming Languages Database Language SQL Graphics POSIX Computer Security Judy B. Kailey Product Data - IGES Editor U.S. DEPARTMENT OF COMMERCE Technology Administration National Institute of Standards and Technology Computer Systems Laboratory Software Standards Validation Group Gaithersburg, MD 20899 July 1995 (Supersedes April 1995 issue) U.S. DEPARTMENT OF COMMERCE Ronald H. Brown, Secretary TECHNOLOGY ADMINISTRATION Mary L. Good, Under Secretary for Technology NATIONAL INSTITUTE OF STANDARDS AND TECHNOLOGY Arati Prabhakar, Director FOREWORD The Validated Products List (VPL) identifies information technology products that have been tested for conformance to Federal Information Processing Standards (FIPS) in accordance with Computer Systems Laboratory (CSL) conformance testing procedures, and have a current validation certificate or registered test report. The VPL also contains information about the organizations, test methods and procedures that support the validation programs for the FIPS identified in this document. The VPL includes computer language processors for programming languages COBOL, Fortran, Ada, Pascal, C, M[UMPS], and database language SQL; computer graphic implementations for GKS, COM, PHIGS, and Raster Graphics; operating system implementations for POSIX; Open Systems Interconnection implementations; and computer security implementations for DES, MAC and Key Management. -
Understanding Full Virtualization, Paravirtualization, and Hardware Assist
VMware Understanding Full Virtualization, Paravirtualization, and Hardware Assist Contents Introduction .................................................................................................................1 Overview of x86 Virtualization..................................................................................2 CPU Virtualization .......................................................................................................3 The Challenges of x86 Hardware Virtualization ...........................................................................................................3 Technique 1 - Full Virtualization using Binary Translation......................................................................................4 Technique 2 - OS Assisted Virtualization or Paravirtualization.............................................................................5 Technique 3 - Hardware Assisted Virtualization ..........................................................................................................6 Memory Virtualization................................................................................................6 Device and I/O Virtualization.....................................................................................7 Summarizing the Current State of x86 Virtualization Techniques......................8 Full Virtualization with Binary Translation is the Most Established Technology Today..........................8 Hardware Assist is the Future of Virtualization, but the Real Gains Have -
Specification-Driven Dynamic Binary Translation
Specification-Driven Dynamic Binary Translation Jens Tr¨oger December 2004 A dissertation submitted in partial fulfillment of the requirements for the degree Doctor of Philosophy in Computer Science OUT Programming Languages and Systems Research Group Faculty of Information Technology Queensland University of Technology Brisbane, Australia Copyright c Jens Tr¨oger, MMIV. All rights reserved. [email protected] http://savage.light-speed.de/ The author hereby grants permission to the Queensland University of Technology to reproduce and distribute publicly paper and electronic copies of this thesis document in whole or in part. “But I’ve come to see that as nothing can be made that isn’t flawed, the challenge is twofold: first, not to berate oneself for what is, after all, inevitable; and second, to see in our failed perfection a different thing; a truer thing, perhaps, because it contains both our ambition and the spoiling of that ambition; the exhaustion of order, and the discovery – in the midst of despair – that the beast dogging the heels of beauty has a beauty all of its own.” Clive Barker (Galilee) Keywords Machine emulation; formal specification of machine instructions; dynamic optimization; dynamic binary translation; specification-driven dynamic binary translation. Abstract Machine emulation allows for the simulation of a real or virtual machine, the source machine, on various host computers. A machine emulator interprets programs that are compiled for the emulated machine, but normally at a much reduced speed. Therefore, in order to increase the execution speed of such interpreted programs, a machine emulator may apply different dynamic optimization techniques. In our research we focus on emulators for real machines, i.e. -
Systems, Methods, and Computer Programs for Dynamic Binary Translation in an Interpreter
(19) TZZ Z_¥4A_T (11) EP 2 605 134 A1 (12) EUROPEAN PATENT APPLICATION (43) Date of publication: (51) Int Cl.: 19.06.2013 Bulletin 2013/25 G06F 9/455 (2006.01) G06F 9/45 (2006.01) (21) Application number: 12186598.4 (22) Date of filing: 14.07.2010 (84) Designated Contracting States: (72) Inventors: AL AT BE BG CH CY CZ DE DK EE ES FI FR GB • Beale, Andrew GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO Mission Viejo, CA 92692 (US) PL PT RO SE SI SK SM TR • Wilton, Loren Rancho Cucamonga, CA 91730 (US) (30) Priority: 14.07.2009 US 502301 • Meyers, Robert 14.07.2009 US 502285 Garden Grove, CA 92840 (US) 14.07.2010 EP 10736925 (74) Representative: Hufton, David Alan (62) Document number(s) of the earlier application(s) in Harrison Goddard Foote accordance with Art. 76 EPC: Fountain Precinct 10736925.8 / 2 454 664 Balm Green Sheffield S1 2JA (GB) (27) Previously filed application: 14.07.2010 PCT/US2010/041973 Remarks: This application was filed on 28-09-2012 as a (71) Applicant: Unisys Corporation divisional application to the application mentioned Blue Bell, PA 19422 (US) under INID code 62. (54) Systems, methods, and computer programs for dynamic binary translation in an interpreter (57) Various embodiments of systems and methods the TCU causing the translation complete event; the TCU for dynamic binary translation in an interpreter are dis- preparing the second stack and scheduling the CPM to closed. An embodiment comprises a method of perform- the second stack; and the CPM executing the native ing dynamic binary translation in a Master Control Pro- code. -
1992 Cern School of Computing
ORGANISATION EUROPEENNE POUR LA RECHERCHE NUCLEAIRE CERN EUROPEAN ORGANIZATION FOR NUCLEAR RESEARCH 1992 CERN SCHOOL OF COMPUTING Scuola Superiore G. Reiss Romoli, L'Aquila, Italy 30 August-12 September 1992 PROCEEDINGS Editor: C. Verkerk GENEVA 1993 © Copyright CERN, Genève, 1993 Propriété littéraire et scientifique réservée Literary and scientific copyrights reserved in pour tous les paya < 11» inonde. Ce document ne all countries of the world. This report, or peut être reproduit ou traduit en tout ou en any part of it. may not be reprinted or trans partie sans l'autorisation écrite du Directeur lated without written permission ol the copy général du CERN, titulaire du droit d'auteur. right holder, the Director-General of CERN. Dans les cas appropriés, et s'il s'agit d'utiliser However, permission will be freely granted for le document à des fins non commerciales, cette appropriate non-commercial use. autorisation sera volontiers accordée. If any patentable invention or registrable Le CERN ne revendique pas la propriété des design is described in the report. CERN makes inventions brevetables et dessins ou modèles no claim to property rights in it but offers i( susceptibles de dépôt qui pourraient être for the free use of research institutions, man décrits dans le présent document ; ceux-ci peu ufacturers and others. CERN, however, may vent être librement utilisés par les instituts de oppose any attempt by a user to claim any recherche, les industriels et autres intéressés. proprietary or patent rights in such inventions Cependant, le CERN se réserve le droit de or designs as may be described in the present s'opposer à toute revendication qu'un usager document. -
DB2SPI B.03.02 User's Guide
HP OpenView Tiering Matrix For HP and Partner use Page 1 of 5 Updated: 18 August 2006 (For OV Performance Agent, OV Operations Agent, SPIs, OVIS, OVAI, GlancePlus and GlancePlus Pak) Usage Notes 1. This matrix is a tool for identifying what tier a system is in. NOT ALL of the listed products are supported on all systems in this matrix. Please read this introduction carefully and also look at the footnotes on each page provided for special cases. 2. Single-user Systems (Unix): For OV Operations Agents, Performance Agents and SPIs a workstation used as a single-user system is classified as a Tier 0 system. 3. Desktop Systems (Windows, Linux, Netware): Professional Desktop License is for use on a single-user Intel-based PC that is running Windows NT Workstation, Windows 2000 Professional, Windows XP Professional, RedHat Linux or Novell NetWare. 4. The tiering below is valid for all systems running AIX, HP-UX, Tru64 UNIX, Digital Unix, Linux, Sun Solaris, MS Windows and Novell NetWare. All other systems are tiered / priced using separate product numbers as follows: o OV Multi-vendor Agent - B7442AA, o OV Multi-vendor Operations Agent - B7443AA, o OV Multi-vendor Performance Agent - B7444AA. 5. Multiple Partitions (Virtual Servers): a. UNIX-based If an OV Agent is being ordered for an UNIX-based system which has multiple partitions / domains (virtual systems) a ‘password request form’ specifying the number of ‘additional’ partitions/domains has to be completed and sent to the password delivery center. There is one license required based upon the tiering of the hosting system and (n-1) free additional Tier 1 licenses for the additional partitions/domains. -
The Evolution of an X86 Virtual Machine Monitor
The Evolution of an x86 Virtual Machine Monitor Ole Agesen, Alex Garthwaite, Jeffrey Sheldon, Pratap Subrahmanyam {agesen, alextg, jeffshel, pratap}@vmware.com ABSTRACT While trap-and-emulate virtualization on mainframes was Twelve years have passed since VMware engineers first virtu- well understood at the time, it was – unsurprisingly – not a alized the x86 architecture. This technological breakthrough design goal for the 4004, whose first application was in fact kicked off a transformation of an entire industry, and virtu- a Busicom calculator [7]. However, as x86 CPUs expanded alization is now (once again) a thriving business with a wide their reach, the case for virtualization gradually emerged. range of solutions being deployed, developed and proposed. There was just one problem, seemingly fundamental: the But at the base of it all, the fundamental quest is still the generally accepted wisdom held that x86 virtualization was same: running virtual machines as well as we possibly can impossible, or at best merely impractical, due to inherited on top of a virtual machine monitor. architectural quirks and a requirement to retain compatibil- ity with legacy code. We review how the x86 architecture was originally virtual- ized in the days of the Pentium II (1998), and follow the This impasse was broken twelve years ago when VMware evolution of the virtual machine monitor forward through engineers first virtualized the x86 architecture entirely in the introduction of virtual SMP, 64 bit (x64), and hard- software. By basing the virtual machine monitor (VMM) ware support for virtualization to finish with a contempo- on binary translation, the architectural features that pre- rary challenge, nested virtualization. -
VAX 4000 Model 100 to DEC 3000 Model 400S AXP Upgrade Instr
VAX 4000 Model 100 to DEC 3000 Model 400S AXP Upgrade Instructions MLO-010669 Part Number: EK-VX44S-IN. A01 Options You Can Upgrade Can Cannot Upgrade Upgrade Disks: RZ23L*, RZ24L* RZ57 RZ24* RZ25* RZ26* RZ55* RZ56* RZ58* Drives: RRD42** B400X RWZ01** DSSI Devices RX26* R400X TLZ04 TF85 TLZ06** TK50 TSZ05* TK70 TSZ07* TKZ08 TZ30 TSV05 TZ85* TU81 TZK10 Expansion Boxes: SZ03 SZ12 SZ16 Memory: None *Supported only in external device. **Including tabletop device. Check Components Shipped Your shipment should contain the following two kits. If you are missing any of these components, contact your Digital sales representative. System Kit: Ethernet Loopback Connector System Unit SCSI Documentation Terminator Antistatic Modem Loopback Wrist Strap Connector Printer Port Terminator System Power Cord Network Label Screwdriver Accessory Kit: Upgrade xxxxxxx xxxxxxxxxxx Card xxx Rubber Grommets RX26 Brackets Metal Support Plate TZ30 RFI Return Shield Address Label MLO-010670 Remove the System Unit Cover Follow these steps to remove the system unit cover: 1. Turn off the system by pressing the on/off switch to the off (O) position. 2. Disconnect the cables, connectors, and terminators from the system unit. 3. Loosen the two captive screws on the back of the system unit. B 1 A 0 0 Captive Screws MLO-010744 4. Slide the cover forward and lift it up from the system unit. Set the cover aside. Remove Fixed Disk Drives Note: The DEC 3000 system can hold two fixed disk drives and one removable-media drive. 1. Press and hold the spring clip that locks the disk drive in position. 2. -
Computer Architectures an Overview
Computer Architectures An Overview PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 25 Feb 2012 22:35:32 UTC Contents Articles Microarchitecture 1 x86 7 PowerPC 23 IBM POWER 33 MIPS architecture 39 SPARC 57 ARM architecture 65 DEC Alpha 80 AlphaStation 92 AlphaServer 95 Very long instruction word 103 Instruction-level parallelism 107 Explicitly parallel instruction computing 108 References Article Sources and Contributors 111 Image Sources, Licenses and Contributors 113 Article Licenses License 114 Microarchitecture 1 Microarchitecture In computer engineering, microarchitecture (sometimes abbreviated to µarch or uarch), also called computer organization, is the way a given instruction set architecture (ISA) is implemented on a processor. A given ISA may be implemented with different microarchitectures.[1] Implementations might vary due to different goals of a given design or due to shifts in technology.[2] Computer architecture is the combination of microarchitecture and instruction set design. Relation to instruction set architecture The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address and data formats among other things. The Intel Core microarchitecture microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is usually represented as (more or less detailed) diagrams that describe the interconnections of the various microarchitectural elements of the machine, which may be everything from single gates and registers, to complete arithmetic logic units (ALU)s and even larger elements. -
Paper Describes a Technique for Improving Runtime Perfor- Mance of Statically Translated Programs
Performance, Correctness, Exceptions: Pick Three A Failproof Function Isolation Method for Improving Performance of Translated Binaries Andrea Gussoni Alessandro Di Federico Pietro Fezzardi Giovanni Agosta Politecnico di Milano Politecnico di Milano Politecnico di Milano Politecnico di Milano [email protected] [email protected] [email protected] [email protected] Abstract—Binary translation is the process of taking a pro- existing programs for which the source code is not available, gram compiled for a given CPU architecture and translate it to enabling the analyst to extract insights about its execution that run on another platform without compromising its functionality. would be otherwise very though to obtain. This paper describes a technique for improving runtime perfor- mance of statically translated programs. Binary translation presents two major challenges: func- tional correctness, and performance. Ideally, both are very First, the program to be translated is analyzed to detect important, but in practice any implementation of a binary function boundaries. Then, each function is cloned, isolated and disentangled from the rest of the executable code. This process is translator needs to make trade-offs between them. called function isolation, and it divides the code in two separate On one hand, dynamic binary translators choose to trans- portions: the isolated realm and the non-isolated realm. late code on-the-fly during execution, favoring functional cor- Isolated functions have a simpler control-flow, allowing much rectness. This choice allows to preserve functional correct- more aggressive compiler optimizations to increase performance, ness even in presence of self-modifying code, runtime code but possibly compromising functional correctness. -
18 a Retargetable Static Binary Translator for the ARM Architecture
A Retargetable Static Binary Translator for the ARM Architecture BOR-YEH SHEN, WEI-CHUNG HSU, and WUU YANG, National Chiao-Tung University Machines designed with new but incompatible Instruction Set Architecture (ISA) may lack proper applica- tions. Binary translation can address this incompatibility by migrating applications from one legacy ISA to a new one, although binary translation has problems such as code discovery for variable-length ISA and code location issues for handling indirect branches. Dynamic Binary Translation (DBT) has been widely adopted for migrating applications since it avoids those problems. Static Binary Translation (SBT) is a less general solution and has not been actively researched. However, SBT performs more aggressive optimizations, which could yield more compact code and better code quality. Applications translated by SBT can consume less memory, processor cycles, and power than DBT and can be started more quickly. These advantages are even more critical for embedded systems than for general systems. In this article, we designed and implemented a new SBT tool, called LLBT, which translates ARM in- structions into LLVM IRs and then retargets the LLVM IRs to various ISAs, including ×86, ×86–64, ARM, and MIPS. LLBT leverages two important functionalities from LLVM: comprehensive optimizations and 18 retargetability. More importantly, LLBT solves the code discovery problem for ARM/Thumb binaries without resorting to interpretation. LLBT also effectively reduced the size of the address mapping table, making SBT a viable solution for embedded systems. Our experiments based on the EEMBC benchmark suite show that the LLBT-generated code can run more than 6× and 2.3× faster on average than emulation with QEMU and HQEMU, respectively.