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HUI-DISSERTATION-2017.Pdf UNDERSTANDING AND ADVANCING SEMICONDUCTOR NANOWIRE SYNTHESIS A Dissertation Presented to The Academic Faculty by Ho Yee Hui In Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy in the School of Chemical & Biomolecular Engineering Georgia Institute of Technology May 2017 Copyright © 2017 by Ho Yee Hui UNDERSTANDING AND ADVANCING SEMICONDUCTOR NANOWIRE SYNTHESIS Approved by: Dr. Michael A. Filler, Advisor Dr. Elsa Reichmanis School of Chemical & Biomolecular School of Chemical & Biomolecular Engineering Engineering Georgia Institute of Technology Georgia Institute of Technology Dr. Martha A. Grover Dr. Younan Xia School of Chemical & Biomolecular Department of Biomedical Engineering Engineering Georgia Institute of Technology Georgia Institute of Technology Dr. Nazanin Bassiri-Gharb School of Mechanical Engineering Georgia Institute of Technology Date Approved:[April 5, 2017] ACKNOWLEDGEMENTS I would like to thank my thesis advisor, Dr. Michael A. Filler, for his guidance through these research projects and my professional career as a researcher. Also, I would like to thank my research group members for valuable discussions and assistance: Dr. Nae Chul Shin, Dr. Saujan, Dr. Li-wei Chou, Dr. Ildar Musin, Dmitriy Boyuk, Amar Mohabir, and Weize Hu, and my many friends who have supported me in my Ph.D. journey: Dr. Shilu Fu, Mengmeng Ye, Gary Pang, Jacob Wong, Crystal Tang, Howard Chan, Handerson Shin, Yolanda Yip, and Dr. Glynda Schaad. Finally, I would like to recognize these constructive comments and support from my committee members: Dr. Elsa Reichmanis, Dr. Younan Xia, Dr. Martha A. Grover, and Dr. Nazanin Bassiri- Gharb. I would like to acknowledge the School of Chemical & Biomolecular Engineering at Georgia Institute of Technology (Georgia Tech), the National Science Foundation, and Institute for Electronics and Nanotechnology (IEN) for their support of my research studies. Particularly, I would like to thank you for the technical assistance from Mr. John Pham, Dr. Chris Yang, Dr. Hang Chan, Mr. Tran-Vinh Nguyen, and Mr. Gary Spinner in IEN through these years. Also, I would like to thank Dr. Maria de la Mata, and Dr. Jordi Arbiol at Catalan Institute of Nanoscience and Nanotechnology and the Barcelona Institute of Science and Technology for conducting TEM measurements and their analyses. Finally, I would like to thank all my family members for the love and support. My parents and my brother, Pik-Mai Hui, gave me the full support and faith to overcome any challenges. iv TABLE OF CONTENTS ACKNOWLEDGEMENTS iv LIST OF TABLES viii LIST OF FIGURES viiii LIST OF SYMBOLS AND ABBREVIATIONS xxv SUMMARY xvi CHAPTER 1. Introduction & Background 1.1 Introduction 1 1.2 Semiconductor Nanowire Properties and Applications 3 1.2.1 Electrical Properties and Electronic Applications 3 1.2.2 Optical Properties and Photonic Applications 5 1.2.3 Mechanical Properties and Sensing Applications 8 1.3 Semiconductor Nanowire Sythesis: Top-down vs. Bottom-up 11 1.3.1 Top-down: Reactive Ion Etching Error! Bookmark not defined.1 1.3.2 Top-down: Metal-assisted Chemical Etching 1Error! Bookmark not defined. 1.3.3 Bottom-up: Solution-phase Sythesis 13 1.3.4 Bottom-up: Laser Ablation 15 1.3.5 Bottom-up: Molecular Bean Epitaxy 16 1.3.6 Bottom-up: Chemical Vapor Deposition 17 1.3.7 Vapor-Liquid-Solid Mechanism 19 1.3.8 Force Balance at the Triple-Phase Line 21 1.4 Synthetic Advantages in Semiconductor Nanowires via VLS Mechanism 23 1.4.1 Diameter Modulation 23 1.4.2 Doping Incorporation 28 1.4.3 Nanowire Heterostructures 30 1.4.4 Growth Direction Modulation 34 1.5 Summary and Perspective 37 1.6 References 39 CHAPTER 2. Experimental Methods 2.1 Chemical Vapor Deposition 80 2.1.1 Gas Phase Collision 80 2.1.2 Chemical Vapor Deposition Theory 82 2.2 Low-pressure Chemical Vapor Deposition 84 2.2.1 Introduction 84 2.2.2 Low-pressure Chemical Vapor Deposition Reactor 85 2.2.3 Reaction Parameter Controls 88 2.2.4 Substrate Preparation 89 v 2.3 Ultra-high Vacuum Chemical Vapor Deposition 89 2.3.1 Introduction 89 2.3.2 Ultra-high Chemical Vapor Deposition Reactor 90 2.3.3 Reaction Parameter Controls 92 2.3.4 Substrate Preparation 93 2.4 Semiconductor Nanowire Characterization 94 2.4.1 Scanning Electron Microscopy 94 2.4.2 Transmission Electron Microscopy 94 2.5 References 96 CHAPTER 3. Solid - Liquid - Vapor Etching of Semiconductor Nanowires 3.1 Introduction 98 3.2 Experiment Details 99 3.3 Results and Discussion 100 3.4 Conclusion 109 3.5 References 110 CHAPTER 4. Kinetic Model of Selective Solid - Liquid - Vapor Etching of Semiconductor Nanowires 4.1 Introduction 113 4.2 Kinetic Model, Results, and Discussion 114 4.3 Conclusion 127 4.4 References 128 CHAPTER 5. Axial Si/Ge Nanowire Heterostructures Grown via the Subeutectic Vapor - Liquid - Solid Mechanism 5.1 Introduction 130 5.2 Experiment Details 135 5.3.1. Nanowire Sythesis 135 5.3.2. Nanowire Characterization 136 5.3.3. Stain Determination 136 5.3 Results and Discussion 137 5.4 Conclusion 150 5.5 References 151 CHAPTER 6.CONCLUDING REMARKS 158 6.1 Summary 158 6.2 Outlook 160 6.3 References 163 vi LIST OF TABLES Page Table 1.1 – Performance of Different Types of Nanowire Based FETs 4 Table 1.2 – Lattice Constants, Lattice Mismatch, and Heterostructure Nanowire 33 Morphology for 13 Material Combinations. Adapted from 257 and reprinted with permission. Table 4.1 – Values of Constants A and B in the Etch Model 121 vii LIST OF FIGURES Page Figure 1.1. (a) A representative SEM image of coaxial silicon nanowire 6 solar cell as the nanoelectronic power source. Scale bar, 50 nm. Adapted from 18 and reprinted with permission. (b) A SEM image of a five-stage carbon nanotube ring oscillator circuit. Adapted from 78 and reprinted with permission. Figure 1.2. (a) A representative SEM image of silicon nanowire device with 9 source and drain terminals. Scale bar, 1 μm. Adapted from 106 and reprinted with permission. (b) A representative of SEM image of an as-made device. The yellow arrow and pink star mark the nanoscale FET and SU-8. Scale bar, 5 μm. Adapted from 25 and reprinted with permission. Figure 1.3. (a) Demonstration of vertical high aspect ratio nanopillars 14 without supercritical drying. Cross-sectional SEM image of p+ nanopillars etched for 20 min. Scale bar, 40 μm. Adapted from 201 and reprinted with permission. (b) TEM images of Si nanowires synthesized at 500 °C in hexane at pressures of 270 bar. Scale bar, 50 nm and 50Å. Adapted from 220 and reprinted with permission. Figure 1.4. (a) Representative SEM image, TEM image, and high-resolution 18 TEM image of Si nanowires synthesized by using Si0.99Ni0.01. Adapted from 229 and reprinted with permission. (b) SEM cross section image of Si whiskers grown in <111> Si substrate at 0.5 Å/s for 120 min growth time at 525 °C. Scale bar, 200 nm. Adapted from 246 and reprinted with permission. (c) Ge Nanowire growth from an AuGe liquid droplet at 340 °C and 4.6 -6 × 10 Torr Ge2H6 with a rate of 0.11 nm/s. The time is shown in seconds since the first image. Adapted from 257 and reprinted with permission. viii Figure 1.5. General illustration of VLS nanowire growth via chemical vapor 20 deposition (a) At the beginning of nanowire growth, metal catalyst is deposited at selective areas while semiconductor precursor molecules are introduced at or above the eutectic temperature. (b) With the help of the catalyst, semiconductor molecules are dissociated into the liquid catalyst through the vapor-liquid interface. The continuous dissociation of semiconductor molecules saturates the catalyst, favoring a nucleation event at the edge of liquid-solid interface. Once the nucleation occurs, a by-layer of the semiconductor material is quickly formed across the liquid-solid interface. (c) The layer- by-layer growth occurs repeatedly on the areas covered by the metal catalyst to form arrays of semiconductor nanowires across a substrate. Figure 1.6. (a)-(e) Bright field ETEM image sequence of the catalyst 22 interface around the TPB of a growing Ge nanowire at ≈ 310 °C -3 inGe2H6 (30% in He) at ≈ 4 × 10 mbar total The times indicated in (A)-(E). In (A) the atomically rough surface is denoted by R, the wetting angle by θc, and γlv, γls, and γvs are the surface energy differences between the liquid-vapor, liquid- solid, and vapor-solid surfaces, respectively. The inset shows a selected area FFT of the Ge nanowire. In(E) the original (111) solid-liquid interface is traced with a dotted black line to highlight the advancement of the growth interface. Adapted from 271 and reprinted with permission. Figure 1.7. (a) SEM image of an array of 60 nm-diameter GaP–Si–GaP 25 nanowires with GaP, Si and GaP segment lengths of 180, 150 and 270 nm, respectively. Tilt angle = 80°, scale bar, 1 μm. Adapted from 296 and reprinted with permission. (b-c) Exchange of material across the Ge NW/liquid drop interface after melting of the alloy Au-Ge nanoparticle at 368 °C. The marker delineates the surface of the Ge NW and provides a reference for the temperature dependent location of the Au- Ge/Ge interface. Adapted from 306 and reprinted with permission. ix Figure 1.8 a)-(e) User-programmable diameter-modulated Ge nanowire 27 superstructures fabricated from 20 nm Au colloid on a Ge(111) wafer via combinations of different flow conditions at 350 °C. The sequence of growth conditions utilized for each superstructure is shown to the left of each image.
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