Fabrication and characterization of nanodevices based on III-V nanowires Andrès De Luna Bugallo
To cite this version:
Andrès De Luna Bugallo. Fabrication and characterization of nanodevices based on III-V nanowires. Other [cond-mat.other]. Université Paris Sud - Paris XI, 2012. English. NNT : 2012PA112117. tel-00731763
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THÈSE DE DOCTORAT
Spécialité : Physique
École Doctorale ”Sciences et Technologies de l’Information des Télécommunications et des Systèmes”
présentée par : Andrés de Luna Bugallo
Fabrication and characterization of nanodevices based on III-V nanowires
Soutenue le ...... devant les membres du jury :
François Julien Directeur de thèse
Jean-Claude De Jaeger Rapporteur
Abdallah Ougazzaden Rapporteur
Christophe Durand Examinateur
Daniel Bouchier Examinateur
Maria Tchernycheva Co-directeur
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GENERAL INTRODUCTION 5
1. INTRODUCTION 8 1.1 NANOSCIENCE AND NANOWIRES 8 1.2 SEMICONDUCTOR MATERIALS 9 1.3 CRYSTALLINE STRUCTURE 10 POLARITY 11 HETEROSTRUCTURES 13 1.4 ELECTRONIC PROPERTIES 13 1.5 NANOWIRE EXPITAXY 16 PARTICLE-ASSISTED GROWTH 18 PARTICLE-FREE GROWTH 19 NANOWIRE GROWTH OF III-VS ON SI 19 SELECTIVE AREA GROWTH 20 1.6 APPLICATIONS 21 PHOTODETECTORS 21 LEDS 23 PHOTOVOLTAIC DEVICES 24 LASERS 25
2. NANOFABRICATION 29 INTRODUCTION 29 2.1 FABRICATION OF SINGLE NANOWIRE DEVICES 31 2.1.1 SUBSTRATE PREPARATION 31 2.1.2 NANOWIRE DISPERSION 32 2.1.3 ELECTRON BEAM LITHOGRAPHY 33 2.1.4 METALLIZATION 41 2.1.5 LIFT-OFF 42 2.1.6 CONTACT ANNEALING 43 2.2 PLANARIZATION 43 2.2.1 HSQ DEPOSITION AND TRANSFORMATION 45 2.2.2 HSQ ETCHING 47 2.2.3 HSQ REMOVAL 48 2.3 FABRICATION OF ARRAY NANOWIRE DEVICES 49 2.3.1 ENCAPSULATION AND TRANSFORMATION 50 2.3.2 RIE ETCHING 51 2.3.3 PHOTOLITHOGRAPHY 52 2.3.4 INDIUM TIN OXIDE DEPOSITION 55 CONCLUSIONS 58
3. PHOTODETECTORS BASED ON NANOWIRE ENSEMBLES 62 3.1 INTRODUCTION 62 3.2 NANOWIRE PHOTODETECTOR STRUCTURE 69 3.3 ELECTRICAL PROPERTIES OF THE NANOWIRE PHOTODETECTOR 71 3.4 ELECTRO-OPTICAL RESPONSE 73 3.5 OPERATION SPEED 75 3.6 PHOTOCURRENT SPECTROSCOPY 76 3.7 DEPENDENCE ON THE INCIDENT POWER 77 3.8 OPTICAL BEAM INDUCED CURRENT 78 CONCLUSIONS 80
4. GAN/ALN SINGLE NANOWIRE PHOTODETECTORS 84
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4.1 NANOWIRE STRUCTURE 85 4.2 MICRO PHOTOLUMINESCENCE SPECTROSCOPY 87 4.3 CATHODOLUMINESCENCE 89 4.4 ELECTRONIC TRANSPORT 92 4.4.1 INFLUENCE OF ENVIRONMENTAL CONDITIONS 94 4.4.2 RESONANT TUNNELING 95 4.5 OPTICAL RESPONSE AND PHOTOCURRENT SPECTROSCOPY 97 CONCLUSIONS 102
5. INGAN/GAN SINGLE WIRE PHOTODETECTORS AND LIGHT EMITTERS 105 INTRODUCTION 105 5.1 GAN/INGAN QW STRUCTURE 106 5.2 WIRE STRUCTURE OF AN N-I-N JUNCTION: THE T929 SAMPLE 108 5.2.1 MICRO PHOTOLUMINESCENCE SPECTROSCOPY 110 5.2.2 ELECTRICAL CHARACTERIZATION AND OPTICAL RESPONSE 111 5.2.3 OPERATION SPEED 113 5.2.4 PHOTOCURRENT SPECTROSCOPY 114 5.2.5 OPTICAL BEAM INDUCED CURRENT 115 5.3 INGAN/GAN NANOWIRE LEDS 116 5.3.1 WIRE P-I-N JUNCTION STRUCTURES : SAMPLES T1163, T1164 AND T1165 118 5.3.2 PHOTOLUMINESCENCE 119 5.3.3 IDENTIFICATION OF SPECTRAL CONTRIBUTIONS BY CATHODOLUMINESCENCE 121 5.3.4 ELECTROLUMINESCENCE 123 5.3.5 ON-CHIP INTEGRATION 127 CONCLUSIONS 129
CONCLUSIONS AND PERSPECTIVES 133
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General introduction
In the recent years the development in the field of III-N semiconductor technology has been spectacular.
Numerous GaN-based devices including light emitting diodes (LEDs), laser diodes (LDs), photodetectors and high power microwave power switches have been developed and brought to the market. The driving force behind the fast development of III-N semiconductors has been the demand for short wavelength emitters. To date there exists only a few semiconductor material systems suitable for such applications. Several II-VI semiconductors such as ZnSe and ZnS have been extensively studied but the devices short lifetime limits their use (Nakamura,
1998). Among the II-VI materials, zinc oxide (ZnO) holds promises as a material for blue and UV optoelectronics, but difficulties in p-type doping hinder the use of ZnO in devices (Klingshirn, 2007). Therefore, the III-N material system is currently the only practical solution for short wavelength semiconductor detectors and emitters.
The efficiency of devices based on III-N materials has improved substantially in the last decades by reducing the dimensions, and changing the design using e.g. quantum wells (QW), multiple QWs (superlattice heterostructures) and quantum dots (QDs) in the active layers. Such structures not only confine the carriers in the growth direction but also passivate surface states at the lower bandgap material surface. However, the choice of materials for the growth of defect free heterostructures is limited by the lattice mismatch issues. This is also one of the main reasons inhibiting the integration of III-V materials on Si.
Such problems can be avoided in the growth of III-N nanowires (NWs). NWs are structures with lengths up to few microns. However their small cross section (10ths of nanometers) favors an efficient elastic strain relaxation inhibiting the generation of structural defects. This fact opens the possibility of growing high-quality materials with an important lattice mismatch with the substrate. At the same time, III-V NWs preserve and enhance the properties of 2D layer epitaxial growth allowing the possibility to form axial heterostructures, quantum dots, p- and n-type doping but also more complex structures such as radial heterostructures and branched nanowires.
Because of these advantages, III-N nanowires have been proposed for a wide variety of applications. In particular they are consider as promising building blocks in nanoscale electronics and optoelectronics devices; such as
5 photodetectors (Soci, 2007)(Kouwe, 2010), transistors (Motayed, 2006), biosensors (Patolsky, 2006), light sources (Qian et al., 2008)(Koester, 2011), solar cells (Dong, 2009), etc.
In this context, the aim of the present work is to develop the fabrication of III-N nanowires devices presenting strategies to assemble single and ensemble nanowires into functional components, and to understand the device behavior by electrical and optical characterizations. The manuscript of this thesis is subdivided as follows:
In the first chapter I present a brief introduction to the structural, optical and electronic properties of III-V semiconductors with a special focus on nitride materials. Then, I give a general description of the different growth techniques of semiconductor nanowires emphasizing the possibility to integrate them on highly mismatched substrates such as silicon. The rest of the chapter provides a quick overview of the state of art in semiconductor nanowires and their applications.
The second chapter focuses on the technological processing to fabricate devices based on nanowires. I describe the different steps in order to electrically address a single nanowire by electron beam lithography as well as the metallization process for achieving ohmic contacts for n-type and p-type GaN nanowires. In the same context, I show the influence of the nanowires diameter and the strategy to follow in the case when it exceeds 350 nm.
Then, I expose a second type of devices based on vertical nanowire ensembles. Its fabrication procedure involves the encapsulation of the nanowires on a dielectric material, optical lithography (to define the device dimensions and to carry out the metal depositions) and the use of indium-tin oxide to contact the nanowire tips.
The third chapter is dedicated to the study of a visible-blind photodetector based on p-i-n GaN nanowires ensembles grown on a Si (111) substrate. Using electrical characterization in the dark and under UV illumination,
I show that these devices exhibit a peak responsivity of 0.47 A/W exceeding that of thin film counterparts. I then study the spectral response of the photocurrent. The devices show an onset at 3.27 eV and a high UV-to-visible rejection ratio; in addition, no spectral contribution from the Si substrate is present.
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Chapter four presents a study of UV photodetectors based on single heterostructured nanowires. The photodetector consists of an n-i-n structure containing GaN/AlN quantum discs in the intrinsic region of the nanowires. After describing the structural characteristics of the studied samples, I focus on the results of photoluminescence and cathodoluminescence spectroscopy evidencing the quantum disc emissions. Spectral contributions above and below the GaN bandgap are related to the variation of the discs thickness and the quantum confined Stark effect. Then, I present electronic transport in these nanowires; I show that when electrons are forced to pass through the multi quantum disc region, the electron transport occurs by tunneling which is revealed by a negative differential resistance in the I-V curves. I then study the spectral response of the nanowire photodetectors. The photocurrent spectra show a sub-band-gap peak related to the interband absorption between the confined states in the large quantum discs. The built-in electric field favors the extraction of photogenerated carriers from the discs.
The last chapter is dedicated to the demonstration of photodetectors and light emitters based on radial
InGaN/GaN multi quantum wells (MQW) embedded in GaN wires. I show how the spectra, obtained by photoluminescence and cathodoluminescence experiments vary according to the excitation spot position. I present the photoresponse results for wires used as photodetectors showing a contribution below the GaN band gap. Optical beam induced current (OBIC) measurements demonstrate that, this signal is exclusively generated in the InGaN MQW region. I then present the fabrication and characterization of LEDs based on these wires. The electroluminescence show a red shift when the In content in the QWs increases, which is in good agreement with photoluminescence results. I also show that the electroluminescence signal consists of two major contributions depending on the levels of current injection, due to the presence of radial and axial MQW systems. Finally, I propose an integrated optical system combining a simple wire emitter and detector, which opens prospects for future photonic structure for nanocircuits.
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1. Introduction
In this chapter I first present the general properties of III-nitride semiconductors that will be needed for the interpretation of experimental results. Then, I give a brief overview of the two main nanowire growth modes, particle-assisted and particle-free, and I present different types of nanowire heterostructures. The last part is dedicated to the review of optoelectronic devices based on nanowires.
1.1 Nanoscience and nanowires
It is well known that systems composed of a reduced number of atoms exhibit quantum effects that can have dramatic implications for their properties, behavior and potential applications. With the reduction of the system size, the physical principles important to atoms, but normally negligible in bulk, begin to increase in importance.
Size effects become important when at least one dimension of a crystal is reduced to the order of hundreds of atoms, which corresponds to the length scale of nanometers. This has instigated the explosive growth of the fields of nanoscience and nanotechnology -- the study and manipulation of matter at a scale of tens of nanometers. As understanding the unique properties of nanostructures increases, so does the interest in and potential of practical applications that take advantage of these properties.
Nanowires are quasi 1-dimensional semiconductor nano-crystals, they have a diameter < 100 nm, whereas the axis is considerably longer, typically in the μm range. Such structures are of particular interest for device applications, as they exhibit unique and fascinating physical properties (mechanic toughness, higher carrier mobility, luminescence efficiency, lowered lasing threshold). In the last decade, these systems have been one main topics of research of the scientific community, to the point of considering as fundamental ‘building blocks’ for
8 the realization of entirely new classes of nano-scale devices and circuits, with applications stretching from photonics to nano-electronics, and from sensors to photovoltaics.
1.2 Semiconductor materials
Among different domains addressed by the nanoscience, one of the most important research fields is related to the study of semiconductor materials. Semiconductor technology has enabled the information technology revolution. Computers, game consoles, satellites, mobile phones are now integral parts of daily life.
A semiconductor exhibits a band gap, which is an energy interval in which no electron states are allowed. In a semiconductor at low temperature the states below the gap are fully occupied by electrons, and the states above the gap are empty. Since completely filled bands (or empty bands) carry no net current, these materials are insulators at absolute zero (Weisstein, 1976). However, at room temperature these materials have a finite conductance that can be controlled by introducing impurity atoms (doping) and applying electrical fields. The complimentary metal oxide semiconductor (CMOS) transistor technology, which is the core of the current computer technology, is based on the ability to “switch” a semiconductor material (generally silicon) between a conducting and a non-conducting state.
The so-called III-V semiconductors are compound materials composed of elements from groups III and V of the periodic system, for example, GaAs, GaN and InP. They are more expensive than Si, and the processing technology is less mature. However, these materials have functionality that Si does not possess. The most important difference is perhaps that most of them exhibit a so-called direct band gap, meaning that electrons can relax to lower energy states radiatively (recombine with holes) with conserved momentum.
The group III-nitride family, consisting of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), their alloys and heterostructures exhibit some unique properties among III-V semiconductors, such as a band gap covering a large domain ranging from the deep UV to the infrared, high breakdown voltage, high thermal conductivity, chemical inertness, mechanical stability, etc. Because of these properties, group-III nitrides have been considered as very promising materials for optoelectronic devices.
9
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This leads to the formation of dipoles in each cell which add to each other through the crystal to give a total macroscopic polarization vector which, Due to the crystal symmetry the polarization is aligned along the [0001] direction, with the positive direction pointing parallel to the [0001]-axis. In Ga-polar GaN films the spontaneous field points towards the surface plane of the film (Bernardini, 1997). The spontaneous polarization constants (psp) for binary III-N materials according to Bernardini, are shown in Table 1.2. Parameter (C/m2) GaN InN AlN psp -0.029 -0.032 -0.081 e31 -0.49 -0.57 -0.60 e33 0.73 0.97 1.56 Table 1.2. Spontaneous polarization (psp) and piezoelectric constants ( e31 and e33 ) of group-III nitrides. The piezoelectric polarization is caused by a strain induced deformation of lattice parameters a, c and u. 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The parameters α and β are tabulated in table 1.5, taking into account the electron-phonon interaction. As shown in Table 1.5, the bandgap reduction (red shift) between 0 K and 300 K is about -68, -66, -96 meV for GaN, InN and AlN respectively. Eg (0) [eV] α [meV/K] β [K] Eg (300K) [eV] Reference GaN 3.489 0.887 874 3.421 [Leroux99] AnN 0.69 0.414 454 0.641 [Walukievicz04] AlN 6.126 1.799 1462 6.03 [Guo9] Table 1.5 : Tabulated values for Eg(0) and Varshni’s parameters (α and β) specifying the calculated band gap at RT 1.5 Nanowire Epitaxy The performance and reliability of semiconductor devices strongly depends on the material quality. Therefore, a high degree of crystallinity is required and the defects should be avoided (or at least controlled). The most difficult problem faced by nitride-based devices is the lack of a lattice-matched substrate. The most commonly used substrate is sapphire where the lattice mismatch with nitrides is 14% and has a thermal expansion coefficient that is almost twice as large of GaN. As a consequence, a large density of dislocations is present degrading the performance of light emitters and limiting the response of the detectors. The lattice mismatch between GaN and Si is even greater (17%), making the growth of high-quality nitride films on Si extremely challenging. 16 )9FGOAJ=)2=HAL9PQAFNGDN=KIM9KA ?JGOL@OAL@9)2 ;GEH9J=< OAL@ :MDC KL9JL LG 9HH=9J KMJ>9;= =F=J?A=K E9C= 9 KA?FA>A;9FL ;GFLJA:MLAGF LG L@= LGL9D =F=J?Q G> L@= KLJM;LMJ= 9F< KLJ9AF 9F< <=>=;L HJGH=JLA=K 9J= >=J=FL LG L@GK= G> :MDC (9FQ )2K 9J= J=HGJL=< LG := A<=9D ;JQKL9DK >J==G><=>=;LK 9F<E9Q;JQKL9DDAR=AF9KLJM;LMJ=>=J=FL>JGEL@=KL9:D=:MDCH@9K= (GJ=GN=J )2 =HAL9PQG>>=JK?J=9L=J>J== $5& 65& .5& !"#$%&& /$0#$%& 1*$2.'(0&3*+4)'& '()(*+,)*-.)-*(,& &'()(*+,)*-.)-*(,& !A?MJ= )2@=L=JGKLJM;LMJ=K9F<?JGOL@EG<=K $F!A?MJ= L@J==>=J=FL)2KLJM;LMJ=K9J=K@GOF #=L=JGKLJM;LMJ=K 9PA9D99F<J9 E9FQ<=NA;=K !GJL@=9PA9D@=L=JGKLJM;LMJ=K L@=)2?=GE=LJQG>>=JKL@=HGKKA:ADALQG>F=OE9L=JA9D;GE:AF9LAGFK :9KA;KLJM;LMJ=K EGJ=9 (GD=;MD9J :=9E =HAL9PQ ( 9F<E=L9DGJ?9FA; ;@=EA;9D N9HGMJ <=HGKALAGF (*1 9J= L@= EGKL =PHDGJ=< KQFL@=LA;E=L@G >GJ=A?FE9L=JA9DLG9KKAKLL@=F9FGOAJ=?JGOL@ /@AKH9JLA;MD9J?JGOL@E=L@G<AK9DKG;9DD=<;9L9DQLA;?JGOL@9F< <=H=F KGDA<1'.GJL@=N9HGJ KGDA< KGDA<1..E=;@9FAKE 17 ! !A?MJ= .;@=E9LA; ADDMKLJ9LAGF G> L@= 1'. ?JGOL@ G> .A OAJ=K MKAF? 9F M ;9L9DQKL H9JLA;D= /@=?J=Q9JJGO 9F<D9:=DKA AA9F<AAAADDMKLJ9L=L@=>=J=FLKL9?=KG>F9FGOAJ=?JGOL@ 1&%)(-'#5644(4)#+!"%*7)8! 29?F=J9F< DDAKHJGHGK=<L@=1'.E=;@9FAKEAFGJ<=JLG=PHD9AFL@=9FAKGLJGHA;?JGOL@G>KADA;GFF9FGOAJ=K 29?F=J DDAK 1'.E=;@9FAKEAK:9K=<GFL@=HJGH=JLA=KG>L@=?GD< KADA;GFH@9K= ;GF;=HLG>9DAIMA<?GD< L@= OADDL9C=HD9;=K=D=;LAN=DQMF<=JL@=MH9JLA;D= #AJME9>MJL@=J=PHDGJ=<M 9KKAKL=<?JGOL@G>$$$ 1F9FGO@AKC=JK AFL@= K#AJME9=L9D 9F<9LL@==F<G>L@= K9F<:=?AFFAF?G> K=N=J9D?JGMHKAFALA9L=< OGJC GF )2 KQFL@=KAK =EHDGQAF? ?GD< H9JLA;D=K !GJ $$$t1 F9FGOAJ=K L@AK M 9KKAKL=< F9FGOAJ= ?JGOL@ E=;@9FAKE AK KMAL9:D= LG 9 FME:=J G> KL9F<9J< ?JGOL@ KQKL=EK KM;@ 9K D9K=J 9KKAKL=< ;9L9DQLA; ?JGOL@ ( ;@=EA;9D:=9E=HAL9PQ 9F<(*1 18 ! Particle-Free Growth Foreign metal catalysts are widely used to direct the orientation and control the size of NWs, and they are intensively studied and well understood. However, contamination from catalysts and the limited selection of morphologies are the main drawbacks of the foreign-metal-catalyzed growth of NWs. Alternatively, NWs can be synthesized without using any foreign catalysts via a vapor deposition process. This offers a high lattice purity that is beneficial in many ways, such as eliminating unintentional doping and avoiding the effect of transition metals. Though this strategy has been widely used in NW synthesis, the growth mechanisms are less understood than those of metal-catalyzed NW growth. Typically, it is recognized that NWs are formed either directly from the vapor phase through a vapor-solid (VS) process or from an excess of metal adatoms through a self-catalyzed process. Nanowire Growth of III-Vs on Si Integration of III-V semiconductors on silicon is a field of great importance, as Si will probably remain the preferred platform for many applications for several reasons: it is available as large area wafers of extremely high purity and crystal quality, the material has good mechanical stability, it is an extremely well-characterized material, and simply because immense investments have been made in Si technology. A union between III-V and Si materials could provide standard CMOS devices with new functionalities. 19 !A?MJ= $DDMKLJ9LAGF G> L@= .A $$$ 1AFL=J>9;= 9 +D9F9J ?JGOL@ >GJ FGJE9D @=L=JGAFL=J>9;= KLJ9AF ;9F GFDQ := J=D9P=< 9DGF? GF= 9DDGOAF? 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G> 19F<K@GJL ;AJ;MAL;MJJ=FL<=FKALA=KG> E ;EO=J=9;@A=N=<9KL@=$F;GEHGKALAGFO9K J= <=KA?FAKL@==>>=;LAN=;9JJA=JK=H9J9LAGFAFL@=J9 D=F?L@G>L@=F9FGOAJ= K9J=KMDL H@GLG?=F=J9L=<;9JJA=JK9J=9:D=LGJ=9;@L@=H A FBMF;LAGFOAL@=F@9F;=< =>>A;A=F;A=K G>L@=>9:JA;9LAGFHJG;=KK !"# $"# %"# !A?MJ= 9 .;@=E9LA; ;JGKK K=;LAGF G> F "9) $F"9) H "9) ;GJ= K@=DD F9FGOAJ=K 9F< ;GJJ=KHGF $ 1;MJN=>GJF9FGOAJ=KOAL@>=J=FLAF @&4#%4! @M=L9D <=EGFKLJ9L=<L@=>AJKL=D=;LJA;9DDQHMEH=<D9K=J G>9@GEGBMF;LAGFG>9@A?@IM9DALQF LQH=D9Q=J?JGOL@:Q( 9F<.: =F;9HKMD9L=<AFHGDQ E=L@QD E=L@9;JQD9L=+((=L;@AFL@=LAHG>L@=F9FGOAJ=K9F<;GN=J=<:Q9F$/*D9Q=J 9K9LGH;GFL9;L>A?MJ= 9 '9KAF?9;LAGFO9K9;@A=N=<9LL@J=K@GD<G>S E OAL@K@9JH=EAKKAGFDAF=K9K F9JJGO9K FE9JGMF<FE !A?MJ= :K@GOL@9LL@=DA?@L=EAKKAGF=E=J?=K>JGEL@=LGHG>L@=OAJ=K9L @A?@;MJJ=FLAFB=;LAGF 25 ! !"# $"# %"# !A?MJ= 9 .;@=E9LA; G> L@= D9K=J <=NA;= O@A;@ ;GFKAKLK G> 9F F LQH= 5F* L@AF >ADE GF 9 ; K9HH@AJ= KM:KLJ9L= H LQH= N=JLA;9DDQ 9DA?F=< 5F* F9FGOAJ=K $/* ;GFL9;L 9F< M /A ;GFL9;L : D=;LJGDMEAF=K;=F;= KH=;LJ9 G> L@= D9K=J <=NA;= 9L E 9JJGOK AF L@= KH=;LJME J=HJ=K=FL IM9KA =IMA .AF?D= F9FGOAJ=D9K=JK MF<=JGHLA;9DAFB=;LAGF@9N=:==FJ=9DAR=<MKAF?$F"9) "9)(,2;GJ= K@=DDF9FGOAJ= @=L=JGKLJM;LMJ=K:Q,A9F=L9D /@="9);GJ=OAJ=O9K?JGOF:Q;9L9DQKL 9KKAKL=<(*1+ ?JGOL@J=KMDLAF?AF9 LJA9F?MD9J;JGKKK=;LAGF >GDDGO=<:Q9EMDLAHD=F$F"9) "9)(,29;LAN=D9Q=J>A?MJ= 9 /@=D9KAF? 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Nanofabrication The current chapter describes the technological processing to fabricate devices based on nanowire ensembles and single nanowires. The main techniques are the optical lithography and the electron beam lithography. A brief review of both techniques as well as of other processing issues and limitations is given. After a brief introduction, I describe the developed strategy to contact single nanowires by means of electron beam lithography. In particular, the influence of NW diameters on the contacting procedure is addressed. Finally, I discuss the fabrication of devices based on vertical nanowire ensembles using photolithographic techniques. The characteristics of such devices will be discussed in the following chapters. Introduction The term « nanofabrication » refers to the design and fabrication of devices having dimensions below 1 µm. Since the invention of the first transistor in 1947, the constant need to reduce the transistor size has been the driving force to push fabrication technologies to new dimensional limits. Following the so-called ‘‘Moore’s Law’’, the semiconductor industry was able to double the density of transistors on a unit area of silicon chip in every 18 months. Despite the fact that silicon has dominated the semiconductor industry, there is also an increasing demand for miniaturization in III-V semiconductor manufacturing. It is motivated by the need of exploiting the unique characteristics of these materials in large-scale integrated electronic and photonic devices. Furthermore, there have been attempts to integrate the III-V materials on Si, in order to exploit the opto-electronic properties of III-Vs integrated on a CMOS platform. Nevertheless, the III-V thin film growth and technology has so far proven to be not CMOS-compatible, mainly due to the lattice mismatch between Si and III-Vs, which induces a significant amount of defects at the hetero-interface and would thus degrade the performance of the final device. 29 Nanofabrication finds applications in numerous fields such as nanoelectronics, nanophotonics, nanomechanics, nanomedicine, etc. requiring different materials and geometries (disks, rods, holes, pyramids, etc). The goal of nanoscience is to develop reliable ways to fabricate nanostructures, and also to achieve macroscopic systems from nanoscale components with dimensions in the submicron range. The nanofabrication tools can be classified into two categories: (i) those that precisely engineer matter (etching and depositing) and (ii) those that define the shape of the elements to be engineered (patterning, mainly lithographic techniques). In this context, optical photolithography is the most common technique to define pattern geometry due to its large scalability, easy processing, and low cost. However, the resolution for conventional sources is limited by the wavelength of light and the optical diffraction phenomena. The range of photon wavelengths used in current optical lithography systems is typically 193–436nm. In addition, photolithography depends on other techniques for the mask fabrication. In order to achieve high resolution, recent efforts have been focused on the development of extreme UV lithography (EUVL), but the main inconvenients are the expensive light sources, scarceness of transparent refractive optics and difficulty to achieve defect-free EUVL masks. Electron beam lithography (EBL) is an alternative process to photolithography. It is a very precise and high- resolution method since electron wavelengths are much shorter than the wavelength of visible-UV photons. Modern EBL systems use high energy electrons (up to 100keV) which can be focused onto spots of several nanometers, which is typically about one order of magnitude smaller than the pattern size employed for the realization of single nanowire devices. No physical masks are needed, patterns can be designed and optimized using a CAD software. Nevertheless, exposure times can take several hours to cover small areas, making this process not efficient for industrial manufacturing. Another drawback is that the system has to be held in a vacuum making the e-beam equipment processing more complex and expensive. In conclusion, the choice between the e- beam lithography and the photolithography depends on final product, including shape, size, length, substrate, application. Both these nanofabrication tools will be used to develop nanowire devices as described in the following. 30 2.1 Fabrication of single nanowire devices In this study, I have developed a nanofabrication process to produce devices based on single nanowires. Here, the description of the technological steps is presented. In general, the fabrication process of individual nanowires consist in the following steps: i. Substrate preparation ii. Nanowire dispersion iii. E-beam lithography iv. Metallization v. Lift-off First Si/SiO2 substrate with alignment marks are prepared by e-beam lithography. The nanowires are then transferred from their growth substrate onto the Si/SiO2 template using either a wet or a dry dispersion method, Nanowire positions are then registered and recorded into a CAD software where contact patterns are designed. Next, the e-beam lithography followed by a metallization is performed to define the contacts on the nanowires. Finally, the excess of metal is removed by a lift-off step. 2.1.1 Substrate Preparation A substrate is a basic component of a nanoscale device, it provides a mechanical support and partly determines the dielectric environment of the device. In this work, silicon wafers are used as device substrates because of their availability and their relatively low cost. The silicon (100) wafers covered by a silicon oxide insulating layer of about 300 nm have been either purchased or produced in our clean rooms by a thermal oxidation of Si wafers. The role of the SiO2 layer is to provide a good insulation preventing current leakage from the nanowire and from the metal contacts to the silicon wafer. 31 The cleanness of the substrate is important to achieve reproducible electrical properties of the device. The silicon wafers are prepared in clean conditions by the manufacture, however, dust particles and other impurities may contaminate the substrate surface during wafer manipulation and fabrication steps. Chemical contaminants include grease from human contact and polymers left from the previous processing steps. Grease and polymer residue can interfere with the good adhesion of the deposited metal layers. Thus, before each fabrication step, the substrate surface must be cleaned in order to keep it dust- and impurity-free. The standard cleaning procedure is as follows: 1. 5 minutes of ultrasonication in acetone 2. 5 minutes of ultrasonication in isopropyl alcohol (IPA) 3. Blow-drying in nitrogen gas All the organic solvent cleaning is performed inside a fume hood. The first step is ultrasonication in acetone; this step is used to shake off the particulate contaminants from the substrate. A second ultrasonication step is carried out in isopropyl alcohol. The IPA step is used to remove any remaining contaminants including acetone traces. Although IPA is a weaker solvent than acetone, IPA itself doesn't leave any residue on the surface when it dries. When all the solvent cleaning is done, a nitrogen gun is used to dry the sample completely. Once the substrates are clean and before nanowire dispersion, a first e-beam lithography step is performed to place alignment marks on the substrate. These marks serve as a reference frame for tracking the position and orientation of the nanowires. They have been designed to easily locate the nanowire and to precisely align the electron beam within one writing field. This point will be discussed later in this section. 2.1.2 Nanowire dispersion GaN nanowires are usually grown on silicon or sapphire substrates. In order to process single nanowire devices, nanowires have to be removed from their native substrates. There are two different approaches to transfer nanowires to an appropriate substrate, i.e. by either dry or wet techniques. As a quick method one can use a dry 32 transfer method. In the dry transfer method, nanowires are collected from the growth substrate with a blade and brushed onto the SiO2/Si substrate. However, the dry transfer method tends to deposit nanowires unevenly, often glued together in bundles and it does not allow for controlling the density of the deposited nanowires. In the wet transfer method, the nanowires are detached from the substrate by ultrasonic agitation in Ethanol. One or several drops of the resulting nanowire suspension are deposited to the Si/SiO2 substrate. The wet transfer method allows for controlling the density of the deposited nanowires by changing the volume of the solvent or the number of drops deposited onto the Si/SiO2 substrate. 2.1.3 Electron beam lithography Electron beam lithography (EBL) is a very precise and high-resolution technique, for forming extremely fine patterns in a layer of material. In this work we developed a method based on EBL for writing contact electrodes on single nanowires using the Raith 150 electron-beam lithography system. The Raith 150 system is capable to control and place patterns with a resolution better than 50 nm making it well suited for contacting nanowires. We can contact a nanowire either by its extremities or deposit multiple contact electrodes within the length of a nanowire. The EBL standard configuration uses a hardware like a scanning electron microscope (SEM). First, the sample surface is coated with a thin layer of polymer – an electron-sensitive resist. The focused electron beam is guided on the surface to form patterns in the resist. The result of this exposure is to render the resist either soluble (called a positive tone resist) or insoluble (negative tone resist) in an appropriate developer solution. A typical electron beam lithography system is shown schematically in figure 2.1. It consists of an electron gun, an electron optical column, and a vacuum chamber containing an x/y stage for positioning the substrate under the beam. 33 !A? DG;C /@= =D=;LJGF GHLA;9D ;GDMEF AK MK=< LG >GJE 9F< KM:KLJ9L= O@A;@AKEGMFL=<GF9@GD<=J9F<;D9EH=<LGL@=KL9?= /@==D=;LJGFK9J=HJG K=;LAGF O@A;@AK;9DD=<L@==D=;LJGFKGMJ;=GJ?MF >L=JL@=:=9EG>=D=;LJGFK=E=J?=K>JGEL@=?MFALH9KK=K L@JGM?@ K=N=J9D 9< HJG;=KK=KLGHJG N=FA> 'AK;9H9:D=LG9;@A=N=N=JQLAFQH9LL=JFK O@=F=D=;LJGFKH=F=LJ9L=9J=KAKL>ADE9F<L@=KM:KLJ9L= L@=Q DGK==F=J?QNA9=D9KLA;9F<AF=D9KLA;;GDDAKAGFKCFGOF9KK;9LL=JAF? D=;LJGFKMF<=J?G:GL@KE9DD 9F?D=AF=D9KLA; GJ >GJO9J< K;9LL=J 9F< D9J?= 9F?D= =D9KLA; GJ :9;CK;9LL=J K;9LL=JAF? =N=FLK GF;= L@=Q =FL=J L@= J=KAKL 9F< KM:KLJ9L=>A?MJ= /@=K;9LL=JAF?HJG;=KKD=9 O@AD=L@=QH=F=LJ9L=AFLGL@=KGDA< K9;GFK=IM=F;= L@==F=J?QAK<=HGKAL=<OAL@AFL@=J=KAKLD9Q=JAF9J=?AGF O@A;@AKEGJ==PL=F<=<L@9FL@=;JGKKK=;LAGFG>L@==D=;LJGF:=9E /@=K=K;9LL=JAF?HJG;=KK=K@9N=AEHGJL9FL ;GFK=IM=F;=KGFL@=OJALAF?HJG;=KK $FH9JLA;MD9J >GJ9 LGL@==PHGKMJ=G>9FGL@=JDG;9L=<OAL@AFL@=K;9LL=JAF?J9F?=G>=D=;LJGFK /@AKAKCFGOF9KwHJGPAEALQ=>>=;Lx .M;@H@=FGE=F9AEHGK=;=JL9AFJ=KLJA;LAGFKG>L@=KAR=9F<K@9H=G>L@=J=DA=>KLJM;LMJ=KL@9L;9F:=OJALL=FAF L@= J=KAKL AF H9JLA;MD9J >GJ ;GEHD=P H9LL=JFK OAL@ KM: EA;JGE=LJ= <=HGKAL=<AF9H9LL=JF>=9LMJ=<=H=F !A?MJ= $DDMKLJ9LAGFG>L@=K@GJL J9F?=>GJO9J< K;9LL=J9F<DGF? J9F?=:9;CK;9LL=J AFL=J9;LAGFG>=D=;LJGFKOAL@J=KAKL ;G9L=<O9>=J GK=;9DA:J9LAGF KE=FLAGF=<9:GN= HJGPAEALQ=>>=;LK9J=MF<=KAJ9:D=AKKM=KAF 'L=;@FAIM=9F<L@=QEMKL:=9NGA<=< (9FQ >=J=FLK;@=E=K@9N=:==F<=KA?F=<LGEAFAEAR=L@AK H=J>GJEAF?L@=DAL@G?J9H@Q>GJKAF?D= F9FGOAJ=<=NA;=>9:JA;9LAGF $FGMJ;9K= LG<=L=JEAF=L@=GHLAE9D=PHGKMJ= H9J9E=L=JK O= MK=< 9 E=L@G< :9K=< GF A<=FLA;9D H9LL=JFK 9F< HJG?J=KKAN=DQ AF;J=9KAF? L@= KAR=K K@9H=K9F<KH9;=:=LO==FL@=E=KAEAL9LAF?L@=F9FGOAJ=;GFL9;LK /@=AFALA9D J=KAKL<9L9K@==LHJGNA<=<:QL@=E9FM>9;LMJ=J /@= GHLAE9DN9DM=9F<L@=KL=H:QO@A;@L@= <=L=JEAF=L@=GHLAE9DN9DM=OAL@9@A?@HJ=;AKAGF . (G:K=JN9LAGF9>L=JE=L9DDAR9LAGF9F<DA>L G>>9DDGOKL@=F>GJ >AF 35 ! a) b) c) !A?MJ= GK=EG =PHGK=< D=9NAF? w:M::D=Kx GF L@= =PHGK=< KMJ>9;= : O@A;@ AK =PHGK=< LG 9F =P;=KKAN= J=KMDLAF? AF 9F MF<=KAJ=< N9JA9LAGF G> L@= H9LL=JFK ; O@A;@ AK =PHGK=< LG 9F GHLAE9D H9LL=JFK@9H=AKO=DD<=>AF=<9F<L@=>=9LMJ=KAR=;GJJ=KHGF 'AL@G?J9H@Q *F;=L@=GHLAE9D KL=H :Q KL=HHJG;=KKG>>9:JA;9LAF?E=L9D;GFL9;LKGFF9FGOAJ=K:Q=D=;LJGF:=9EDAL@G?J9H@QAKK@GOFAF!A?MJ= 9 /@= F9FGOAJ= HGKALAGF OAL@ J=KH=;L LG L@= 9DA?FE=FL E9JCK AK J=;GJ<=< : /@= <= <=KA?F=<MKAF? L@=-9AL@.G>LO9J= ;D9Q=JG>+((J=KAKLAKKHAF ;G9L=<GFL@=K9EHD= <F=D=;LJG<= H9LL=JF AK OJALL=F :Q L@= =D=;LJGF :=9E /@= J=KAKL AK <=N=DGH=< 9>L=J =PHGK=J = (=L9D AK <=HGKAL=< > /@= J=E9AFAF?J=KAKLAK /@=;@AHAKL@=FOAJ=:GF<=<>GJE=9KMJ=E=FLK 36 ! !A?MJ= .;@=E9LA;NA=OG>>=J=FL>9:JA;9LAGFKL9?=K /,*10(170$5.6 DA?FE=FLE9JCK9J=J=IMAJ=<LGDG;9L=L@=F9FGOAJ=K9F<LG9DA?FL@==D=;LJGF:=9EOAL@9@A?@HJ=;AKAGF /G >9;ADAL9L=L@=9DA?FE=FLHJG;= AFLG9J=?MD9J9JJ9Q /G9DDGO>GJ9JGM?@9DA?FE=FL D9J?=;JGKK=K9J=HD9;=<AFL@=>GMJ;GJF=JKG>L@=?DG:9D OJALAF? >A=D< OAL@ 9 KH9;AF? G> EE /@=F 9F 9JJ9Q G> KE9DD=J ;JGKK=K OAL@ YE KH9;AF? AK H=JAG J=H=9L=<>GJ=9;@DG;9DOJAL= >A=D<OAL@9H=JAG<G> ME 2@=F GJ<=JLG@9N=9KA?FA>A;9FL9EGMFLG>OAJ=KHJ=K=FLAF=9;@OJAL=>A=D< *F=G>L@=E9AF9 KQKL=E AK ALK . ( AFL=?J9L=< KQKL=E L@9L >9;ADAL9L=K L@= F9NA?9LAGF 9DD GN=J L@= K9EHD= 9F< L@= HJ=;AK= DG;9LAGFG>L@=F9FGOAJ=HGKALAGFK 37 ! Mask design Nanowire positions are introduced into Raith 150 software, then a custom mask is designed to contact them. The intended pattern is created using a GDSII format layout-editor software. The typical contact width is between 100 nm and 400 nm and the spacing is between 100 nm and several microns depending on the nanowire length. We choose rectangular geometry for contacts as shown in Figs 2.6 and 2.7. One end of the contact strip covers the nanowire, while the other end is connected to the large area square contact used for macroscopic wire bonding. This latter contact can be either written using e-beam lithography with a large current or defined by optical lithography. Both strategies have been used depending on the desired application. PMMA resist After locating the position of the nanowires, a layer of e-beam resist is spin coated on top of the nanowires. We use Polymethyl methacrylate (PMMA A6) positive resist in this work. PMMA is a transparent polymer, which is electron-beam sensitive. When exposed to the electron beam, these complex macromolecules get broken down into simpler compounds, which can be easily dissolved in a chemical developer. The developer used is a cocktail of 3 parts IPA and 1 part methyl-isobutyl ketone (MIBK) by volume. The contacting of nanowires with average diameters between 50 nm and 200 nm requires that the deposited metal thickness should be at least 25-100 nm to avoid discontinuities in the deposited metal electrodes. We use a recipe resulting in a 500 nm thick layer of PMMA A6 to allow for a lift-off process of metal deposition. The actual spin coating recipe is the following. Multiple drops of PMMA A6 solution are deposited on the surface until covering entirely the whole sample. The spinning rate is then set up to 4000 rpm, which is maintained for 60 seconds to uniformly coat the chip with a layer thickness of 500nm. After spinning, the sample is baked on a hot plate at 180ºC for 15 minutes to harden the PMMA layer. 38 %($0:5,7,1* /@=-9AL@KQKL=EMLADAR=KL@=N=;LGJ K;9FFAF?9HHJG9;@O@=J=L@== :=9EwBMEHKx>JGEGF=H9LL=JF=<9J=9LGL@= F=PLKCAHHAF?GN=J9DDFGF H9LL=JF=<9J=9K /@AKE=L@G<G>FGLNAKALAF?=N=JQHGAFLAFL@=H9LL=JFE9C=KL@=N=;LGJ K;9F9HHJG9;@>9KL=JL@9FJ9KL=JK;9F>GJKH9JK=H9LL=JFK>A?MJ= 9 DKG L@=N=;LGJ K;9FC==HKL@=KM:KLJ9L= KL9LAGF9JQO@AD=L@== :=9EAK<=>D=;L=<GN=JL@=9J=9KLG:==PHGK=< (=;@9FA;9DNA:J9LAGFKE9QAF>DM=F;=L@= OJALAF?9;;MJ9;Q N=FA>L@=-9AL@@9K9F9FLA NA:J9LAGFKQKL=E K9EHD=KO=J=MKM9DDQDG9<=<@GMJK:=>GJ=L@= DAL@G?J9H@QAFGJ<=JLG=DAEAF9L=L@AKAKKM= *MJOJAL=KLJ9L=?Q;GFKAKLKLG 9JGMF< ME @GO=N=J>GJD9J?=OJALAF?>A=D OAL@ KM:EA;JGF ;GFL9;L >=9LMJ=K 9 KE9DD OJALAF? 9J=9 AK <=KAJ=< KG L@9L L@= = :=9E ;9F ;GN=J AL OAL@ ?GG< HJ=;AKAGF !GJL@AKJ=9KGF$;@GK=L@=OJAL=>A=D<KAR=G> MEP ME KE=FLAGF=<:=>GJ= >GMJ;JGKK K@9H=< 9DA?FE=FLE9JCK9J=HJ=K=FLAF=9;@OJAL=>A=D< >L=JL@=OJALAF?G>GF=>A=D<AK>AFAK@=< L@=KL9?=AKEGN=<LGL@= F=PLOJAL=>A=D<=L;>A?MJ= : a) b) ! ! !A?MJ= 9GEH9JAKGF:=LO==FJ9KL=J9F<N=;LGJK;9F:L@== :=9EAKKO=HL9;JGKKL@= =FLAJ=KMJ>9;= OJAL=>A=D<:QOJAL=>A=D< L@=:=9EAK:DAFC=<9;;GJ ! GJKE9DD:=9E >A=D<MKAF?L@=9DA?FE=FLKE9JCK /@=KLJ9L=?Q>GJ;9DA:J9LAGFL@= LG 39 ! the four crosses. The resulting image is the position to what computer thinks the original spot is. Looking at the image, we correct the difference between where the beam thinks we are and where the actual original spot is, we repeat the same step for the four crosses positions; the computer will register the data in order to implement a correction for the beam deflection. In order to write a design larger than one write-field, which is often what is needed, it is necessary to write over several write-fields by putting several write-fields adjacent to each other. For accurate stitching, the sample stage is translated by a combination of servo-motors and piezo-electric actuators guided by the laser-interferometer. Two step electron beam lithography For applications in which two different metallizations are required, it is necessary to perform two steps of electron beam lithography. This was for instance the case for nanowire-based p-n junctions, for which two different ohmic contacts on p-GaN and on n-GaN were required. In this case the e-beam writing, metallization and lift-off are repeated twice. Figure 2.7 show a p-i-n nanowire structure (where the half of the NW side is n-type while the other half is p-type). The n- and p-type sides have been recognized by SEM observation thanks to the tapering of the nanowire, yielding a diameter on the p-type side larger than on the n-type side. This recognition process is crucial in order to achieve ohmic contacts on each side. Figure 2.6 shows SEM image of a p-i-n GaN single nanowire contacted by two steps of e-beam lithography. Ti/Al/Ti/Au is deposited in the n-type region (yellow) while the p-type is covered by Ni/Au (brown). 40 2.1.4 Metallization The metallization is the fabrication step in which electrical interconnects are formed by depositing selected metals. There are several methods of metallization such as thermal evaporation, magnetron sputtering and electron beam evaporation. We used e-beam evaporation; this method uses an electron beam with a high energy of 10 keV to evaporate a small spot of a source material in the crucible. In evaporation methods the pressure inside the evaporation chamber is about 10-6 or 10- 7 Torr. At this low pressure, the mean free path of the evaporated atoms is of the same order of magnitude as the vacuum chamber dimensions, so these atoms travel in straight lines from the source to the substrate. The deposition is directional in opposition to sputtering technique, where a conformal coverage is obtained. The directional deposition is better adapted for lift-off process, which is one of the motivations of the choice of e-beam evaporation in this work. Before the metal deposition, we use in-situ Ar plasma cleaning to remove residual resist beneath the contacts. The choice of the deposited metals is important for the contact resistance. For n-type GaN nanowires Ti/Au metals are sometimes used in the literature to form ohmic contact (Schmitz A.C. et al., 1996). However, the optimization of ohmic contacts performed on thin films has shown that much lower contact resistance can be achieved by employing a Ti/Al/Ti/Au metallization. In this case, Ti layer provides a thermally stable and low- resistive contact to GaN as well as a stick platform for the rest of layers. It also interacts with GaN to form TiN interface layer. TiN has a lower work function (3.74 eV) than Ti. Also, the formation of a thin TiN interfacial layer generates a nitrogen-deficient layer near the Ti/GaN interface. This phenomenon causes the GaN to be locally highly n-doped and improves the tunneling effect on the Ti/GaN interface. Al is the metal with the closest work function with n-type GaN which improves the contact resistance. A second layer of Ti plays the role of a capping layer in order to avoid Al oxidation and Al-Au intermixing. Finally, the Au layer is used to allow wire bonding. This metallization scheme, allows achieving contacts resistivity as low as 6.0x10-7 Ωcm2 and 2.2.0x10-5 Ωcm2 for doping concentrations of 1.4x1020 cm-3 and 2.2x1018 respectively (Wang et al., 2001,)(Davydov et al., 2005). Difficulties in achieving low-resistance ohmic contacts in p-type GaN are due to the poor carrier concentration and the absence of suitable metals with a higher work function than that of p-GaN. Ni/Au metal approach is one alterative solution to overcome this issue attaining resistivity values around 10-4 Ωcm2 (Ho et al., 1999). When a thermal annealing is done under O2 ambient the Ni diffuse to the contact surface to form NiO, resulting in the 41 a) b) contact structure of p-GaN/NiO/Au. The oxygen atoms incorporated during annealing promote out-diffusion of Ga atoms, producing Ga vacancies below the contact. Thus, the net hole concentration in the near-surface region increases and the surface Fermi level moves to the energy level of the Ga vacancy, leading to a drastic reduction in contact resistivity (Jang, S. Y. Kim, & J.-L. Lee, 2003). 2.1.5 Lift-off The lift-off process removes the excess metal. The metal film on the PMMA resist is detached from the sample when the PMMA is dissolved in acetone. A thick layer of deposited metal can lead to difficulties in the lift-off process by forming a continuous metal layer across the developed area. Therefore, the metal thickness should be less than about 50% of the resist thickness to avoid a lift-off problem. To check that all the excess metal has been lifted-off, the chip can be controlled under an optical microscope. This has to be done while the sample is still wet, otherwise the excess metal will stick to the chip and won't come off. If all the excess metal has not been lifted-off, the chip can be soaked in acetone for longer time, rinsed with a syringe or put in an ultrasonication bath. However, with nanowires already present on the chip, we usually avoid using ultrasonication. When the lift-off of excess metal is completed, the sample is rinsed with isopropyl alcohol and blown dry with a nitrogen gun. Figure 2.7 SEM images of nanowires after the whole technological process. a) Multi-contacts along an InP nanowire b) Double contact on a single GaN nanowire. 42 C/./L!M*$)&-)!&$$#&'($?! !GJ9?GG<H=J>GJE9F;=G>H@GLG<=L=;LGJK9F<DA?@L=EALL=JK ALAKF=;=KK9JQLG@9N=G@EA;;GFL9;LK /@9FCKLG L@=JHD9KE9;D=9FAF? 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