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PURDUE UNIVERSITY GRADUATE SCHOOL Thesis/Dissertation Acceptance Graduate School ETD Form 9 (Revised 12/07) PURDUE UNIVERSITY GRADUATE SCHOOL Thesis/Dissertation Acceptance This is to certify that the thesis/dissertation prepared By Himadri S. Pal Entitled Device Physics Studies of III-V and Silicon MOSFETs for Digital Logic For the degree of Doctor of Philosophy Is approved by the final examining committee: MARK S. LUNDSTROM Chair GERHARD KLIMECK PEIDE YE SUPRIYO DATTA To the best of my knowledge and as understood by the student in the Research Integrity and Copyright Disclaimer (Graduate School Form 20), this thesis/dissertation adheres to the provisions of Purdue University’s “Policy on Integrity in Research” and the use of copyrighted material. MARK S. LUNDSTROM Approved by Major Professor(s): ____________________________________ ____________________________________ Approved by: V. Balakrishnan 09-27-2010 Head of the Graduate Program Date Graduate School Form 20 (Revised 6/09) PURDUE UNIVERSITY GRADUATE SCHOOL Research Integrity and Copyright Disclaimer Title of Thesis/Dissertation: Device Physics Studies of III-V and Silicon MOSFETs for Digital Logic For the degree of ________________________________________________________________Doctor of Philosophy I certify that in the preparation of this thesis, I have observed the provisions of Purdue University Executive Memorandum No. C-22, September 6, 1991, Policy on Integrity in Research.* Further, I certify that this work is free of plagiarism and all materials appearing in this thesis/dissertation have been properly quoted and attributed. I certify that all copyrighted material incorporated into this thesis/dissertation is in compliance with the United States’ copyright law and that I have received written permission from the copyright owners for my use of their work, which is beyond the scope of the law. I agree to indemnify and save harmless Purdue University from any and all claims that may be asserted or that may arise from any copyright violation. ______________________________________Himadri Pal Printed Name and Signature of Candidate 09-27-2010 ______________________________________ Date (month/day/year) *Located at http://www.purdue.edu/policies/pages/teach_res_outreach/c_22.html DEVICE PHYSICS STUDIES OF III-V AND SILICON MOSFETS FOR DIGITAL LOGIC A Dissertation Submitted to the Faculty of Purdue University by Himadri Sekhar Pal In Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy December 2010 Purdue University West Lafayette, Indiana ii To my parents and wife, for reinforcing my EHOLHILQHGXFDWLRQDQGOHDUQLQJ« iii ACKNOWLEDGMENTS My thesis advisor, Prof. Mark Lundstrom, deserves my earnest gratitude for his support throughout my graduate studies at Purdue. He is an excellent researcher and mentor, and has shaped the course of my work as well as other skills required to excel in a professional career. He has instilled in me a deep appreciation for process of scientific research, and the importance of applying and communicating my knowledge. I am also thankful to Prof. Supriyo Datta, Prof. Gerhard Klimeck and Prof. Peide Ye for the many helpful discussions and guidance, and for serving on my committee. I would like to express my deep appreciation for my collaborator, Dr. Dmitri Nikonov from Intel Corp., who has guided me professionally and on a personal level. I also appreciate the guidance of Dr. Titash Rakshit during my summer internship, and Dr. Martin Giles and Dr. Mark Stettler for giving me the opportunity to work as an intern at ,QWHO 0\ JUDGXDWH UHVHDUFK DW 3XUGXH ZRXOGQ¶W KDYH VXFFHHGHG ZLWKRXW WKH collaborations from my fellow researchers. Special thanks to Yang Liu, Dr. Tony Low, Raseong Kim, Changwook Jeong, Kurtis Cantley, Dr. Shaikh S. Ahmed for successful collaborations. I also appreciate the enlightening and entertaining discussions with my other group members and fellow researchers at EE350 and HDLR. I acknowledge the sponsors SRC MSD focus center and GRC center for funding my research, and NCN for computational support. I am grateful to Cheryl Haines for all the complicated travel forms that she prepared on my behalf. My deepest appreciation goes to my wife Sweta, DV,ZRXOGQ¶WKDYHEHHQDEOHWR continue on this journey without her invaluable enthusiasm and support. I am indebted to my parents and my brother, who have always had faith in me, and instilled a sense of independence that has been an integral part of my life. iv TABLE OF CONTENTS Page /,672)7$%/(6«««««««««««««««««««««««««««YL /,672)),*85(6««««««««««««««««««««««««««...vii ABSTRACT««««««««««««««««««««««««««««««[ 1. INTRODUCTION........................................................................................................1 2. QUANTUM CAPACITANCE AND DOS BOTTLENECK IN III-V‟S....................5 2.1 Introduction...........................................................................................................5 2.2 Approach...............................................................................................................8 2.3 Inversion layer capacitance.................................................................................11 2.4 Ballistic injection velocity and channel resistance.............................................15 2.5 Conclusion..........................................................................................................19 3. NEGF STUDY OF INGAAS SCHOTTKY BARRIER MOSFETS.........................20 3.1 Introduction.........................................................................................................20 3.2 Simulation Methodology....................................................................................24 3.3 Device Evaluation...............................................................................................27 3.4 Conclusion..........................................................................................................36 4. EXPERIMENTAL VERSUS BALLISTIC SIMULATION COMPARISON OF SHORT CHANNEL THIN SOI MOSFETS..............................................................37 4.1 Introduction.........................................................................................................37 4.2 IBM ETSOI device characterization...................................................................40 4.3 Comparison to ballistic simulations....................................................................43 4.4 Analysis using scattering theory.........................................................................47 4.5 Low temperature analysis...................................................................................50 4.6 Discussion...........................................................................................................55 4.7 Conclusion..........................................................................................................57 v Page 5. ELECTRON-PHONON SCATTERING WITH NEGF............................................59 5.1 ,QWURGXFWLRQ«..................................................................................................59 5.2 )RUPDOLVP«.....................................................................................................61 5.3 ,PSOHPHQWDWLRQ«.............................................................................................68 5.4 %HQFKPDUNLQJ«...............................................................................................69 5.5 &RQFOXVLRQ«.....................................................................................................79 6. NEGF SIMULATION OF ETSOI MOSFETS WITH SCATTERING.....................81 6.1 ,QWURGXFWLRQ«...................................................................................................81 6.2 Surface roughness scattering model....................................................................82 6.3 Surface roughness scatWHULQJZLWK1(*)«......................................................85 6.4 ETSOI simulations with phonon scatteULQJ«...................................................88 6.5 ETSOI simulations with phonons aQGVXUIDFHURXJKQHVVVFDWWHULQJ«90 6.6 Discussion...........................................................................................................94 6.7 &RQFOXVLRQ«....................................................................................................96 7. SUMMARY AND FUTURE WORK........................................................................98 7.1 Analysis of III-9GHYLFHV«...............................................................................98 7.2 7UHDWPHQWRIVFDWWHULQJLQ1(*)«...................................................................99 7.3 )XWXUHZRUN«.................................................................................................100 LIST OF REFERENCES.................................................................................................102 VITA................................................................................................................................113 vi LIST OF TABLES Table Page 2.1 *D$VHIIHFWLYHPDVVHVIRUGLIIHUHQW'*FKDQQHOWKLFNQHVV««««««««9 4.1 'HYLFHJHRPHWU\DQGPDWHULDOSDUDPHWHUV«««««««39 4.2 3DUDPHWHUVXVHGLQWKH96PRGHO««««««««55 vii LIST OF FIGURES Figure Page 2.1 C-V plot for bulk silicon, DG sLOLFRQDQG*D$V026)(7V««««««««.10 2.2 Valley subband energies vs. surfDFHSRWHQWLDO««««««««««.......12 2.3 CQ and Cinv vs. DG thickness at VDD = 1V and 0.5V........................................13 2.4 İ/qȥs vs. channel thickness at VDD 9DQG9«««««««.......14 2.5 GaAs Subband energy
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