DOCSLIB.ORG

Intel® Quark Soc X1000 Core Developer's Manual

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Intel® Quark Soc X1000 Core Developer's Manual Intel® Quark SoC X1000 Core Developer’s Manual October 2013 Order Number: 329679-001US INFORMATIONLegal Lines and Disclaimers IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. A "Mission Critical Application" is any application in which failure of the Intel Product could result, directly or indirectly, in personal injury or death. SHOULD YOU PURCHASE OR USE INTEL'S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION, YOU SHALL INDEMNIFY AND HOLD INTEL AND ITS SUBSIDIARIES, SUBCONTRACTORS AND AFFILIATES, AND THE DIRECTORS, OFFICERS, AND EMPLOYEES OF EACH, HARMLESS AGAINST ALL CLAIMS COSTS, DAMAGES, AND EXPENSES AND REASONABLE ATTORNEYS' FEES ARISING OUT OF, DIRECTLY OR INDIRECTLY, ANY CLAIM OF PRODUCT LIABILITY, PERSONAL INJURY, OR DEATH ARISING IN ANY WAY OUT OF SUCH MISSION CRITICAL APPLICATION, WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR WAS NEGLIGENT IN THE DESIGN, MANUFACTURE, OR WARNING OF THE INTEL PRODUCT OR ANY OF ITS PARTS. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined". Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with this information. The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548- 4725, or go to: http://www.intel.com/design/literature.htm Any software source code reprinted in this document is furnished for informational purposes only and may only be used or copied and no license, express or implied, by estoppel or otherwise, to any of the reprinted source code is granted by this document. Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. Go to: http://www.intel.com/products/processor_number/ Code Names are only for use by Intel to identify products, platforms, programs, services, etc. (“products”) in development by Intel that have not been made commercially available to the public, i.e., announced, launched or shipped. They are never to be used as “commercial” names for products. Also, they are not intended to function as trademarks. Intel and the Intel logo are trademarks of Intel Corporation in the U.S. and/or other countries. *Other names and brands may be claimed as the property of others. Copyright © 2013, Intel Corporation. All rights reserved. Intel® Quark SoC X1000 Core Developer’s Manual October 2013 2 Order Number: 329679-001US Revision History—Intel® Quark Core Revision History Date Revision Description September 2013 001 First external release of document. Intel® Quark SoC X1000 Core October 2013 Developer’s Manual Order Number: 329679-001US 3 Intel® Quark Core—Contents Contents 1.0 About this Manual .......................................................................................................17 1.1 Manual Contents................................................................................................17 1.2 Notation Conventions .........................................................................................18 1.3 Special Terminology ...........................................................................................19 1.4 Related Documents ............................................................................................20 2.0 Intel® Quark SoC X1000 Core Overview.........................................................................21 2.1 Intel® Quark Core Architecture............................................................................21 3.0 Architectural Overview.................................................................................................22 3.1 Internal Architecture ..........................................................................................22 3.2 System Architecture...........................................................................................22 3.3 Memory Organization .........................................................................................22 3.3.1 Address Spaces ......................................................................................23 3.3.2 Segment Register Usage..........................................................................24 3.4 I/O Space .........................................................................................................25 3.5 Addressing Modes..............................................................................................25 3.5.1 Addressing Modes Overview .....................................................................25 3.5.2 Register and Immediate Modes.................................................................26 3.5.3 32-Bit Memory Addressing Modes .............................................................26 3.5.4 Differences Between 16- and 32-Bit Addresses ...........................................28 3.6 Data Types .......................................................................................................28 3.6.1 Data Types ............................................................................................28 3.6.1.1 Unsigned Data Types .................................................................29 3.6.1.2 Signed Data Types ....................................................................29 3.6.1.3 BCD Data Types........................................................................30 3.6.1.4 Floating-Point Data Types...........................................................30 3.6.1.5 String Data Types .....................................................................30 3.6.1.6 ASCII Data Types......................................................................31 3.6.1.7 Pointer Data Types ....................................................................32 3.6.2 Little Endian vs. Big Endian Data Formats ..................................................33 3.7 Interrupts.........................................................................................................33 3.7.1 Interrupts and Exceptions ........................................................................33 3.7.2 Interrupt Processing................................................................................34 3.7.3 Maskable Interrupt..................................................................................34 3.7.4 Non-Maskable Interrupt...........................................................................35 3.7.5 Software Interrupts.................................................................................36 3.7.6 Interrupt and Exception Priorities..............................................................36 3.7.7 Instruction Restart..................................................................................37 3.7.8 Double Fault ..........................................................................................38 3.7.9 Floating-Point Interrupt Vectors ................................................................38 4.0 System Register Organization.......................................................................................39 4.1 Register Set Overview ........................................................................................39 4.2 Floating-Point Registers ......................................................................................39 4.3 Base Architecture Registers.................................................................................39 4.3.1 General Purpose Registers .......................................................................40 4.3.2 Instruction Pointer ..................................................................................41 4.3.3 Flags Register ........................................................................................41 4.3.4 Segment Registers..................................................................................44 4.3.5 Segment Descriptor Cache Registers .........................................................44 4.4 System-Level Registers ......................................................................................45 4.4.1 Control Registers ....................................................................................46 Intel® Quark SoC X1000 Core Developer’s Manual October 2013 4 Order Number: 329679-001US Contents—Intel® Quark Core 4.4.1.1 Control Register 0 (CR0)...........................................................
Load more

Recommended publications
  • What Is an Operating System III 2.1 Compnents II an Operating System
    Page 1 of 6 What is an Operating System III 2.1 Compnents II An operating system (OS) is software that manages computer hardware and software resources and provides common services for computer programs. The operating system is an essential component of the system software in a computer system. Application programs usually require an operating system to function. Memory management Among other things, a multiprogramming operating system kernel must be responsible for managing all system memory which is currently in use by programs. This ensures that a program does not interfere with memory already in use by another program. Since programs time share, each program must have independent access to memory. Cooperative memory management, used by many early operating systems, assumes that all programs make voluntary use of the kernel's memory manager, and do not exceed their allocated memory. This system of memory management is almost never seen any more, since programs often contain bugs which can cause them to exceed their allocated memory. If a program fails, it may cause memory used by one or more other programs to be affected or overwritten. Malicious programs or viruses may purposefully alter another program's memory, or may affect the operation of the operating system itself. With cooperative memory management, it takes only one misbehaved program to crash the system. Memory protection enables the kernel to limit a process' access to the computer's memory. Various methods of memory protection exist, including memory segmentation and paging. All methods require some level of hardware support (such as the 80286 MMU), which doesn't exist in all computers.
    [Show full text]
  • Irmx® 286/Irmx® II Troubleshooting Guide
    iRMX® 286/iRMX® II Troubleshooting Guide Q1/1990 Order Number: 273472-001 inter iRMX® 286/iRMX® II Troubleshooting Guide Q1/1990 Order Number: 273472-001 Intel Corporation 2402 W. Beardsley Road Phoenix, Arizona Mailstop DV2-42 Intel Corporation (UK) Ltd. Pipers Way Swindon, Wiltshire SN3 1 RJ United Kingdom Intel Japan KK 5-6 Tokodai, Toyosato-machi Tsukuba-gun Ibaragi-Pref. 300-26 An Intel Technical Report from Technical Support Operations Copyright ©1990, Intel Corporation Copyright ©1990, Intel Corporation The information in this document is subject to change without notice. Intel Corporation makes no warranty of any kind with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. Intel Corporation assumes no responsibility for any errors that ~ay :!ppe3r in this d~ur:::ent. Intel Corpomtion make:; nc ccmmitmcut tv update nor to keep C"l..iiTeilt thc information contained in this document. Intel Corporation assUmes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent licenses are implied. Intel software products are copyrighted by and shall remain the property of Intel Corporation. Use, duplication or disclosure is subject to restrictions stated in Intel's software license, or as defined in FAR 52.227-7013. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Intel Corporation. The following are trademarks of Intel Corporation
    [Show full text]
  • CS 151: Introduction to Computers
    Information Technology: Introduction to Computers Handout One Computer Hardware 1. Components a. System board, Main board, Motherboard b. Central Processing Unit (CPU) c. RAM (Random Access Memory) SDRAM. DDR-RAM, RAMBUS d. Expansion cards i. ISA - Industry Standard Architecture ii. PCI - Peripheral Component Interconnect iii. PCMCIA - Personal Computer Memory Card International Association iv. AGP – Accelerated Graphics Port e. Sound f. Network Interface Card (NIC) g. Modem h. Graphics Card (AGP – accelerated graphics port) i. Disk drives (A:\ floppy diskette; B:\ obsolete 5.25” floppy diskette; C:\Internal Hard Disk; D:\CD-ROM, CD-R/RW, DVD-ROM/R/RW (Compact Disk-Read Only Memory) 2. Peripherals a. Monitor b. Printer c. Keyboard d. Mouse e. Joystick f. Scanner g. Web cam Operating system – a collection of files and small programs that enables input and output. The operating system transforms the computer into a productive entity for human use. BIOS (Basic Input Output System) date, time, language, DOS – Disk Operating System Windows (Dual, parallel development for home and industry) Windows 3.1 Windows 3.11 (Windows for Workgroups) Windows 95 Windows N. T. (Network Technology) Windows 98 Windows N. T. 4.0 Windows Me Windows 2000 Windows XP Home Windows XP Professional The Evolution of Windows Early 80's IBM introduced the Personal PC using the Intel 8088 processor and Microsoft's Disk Operating System (DOS). This was a scaled down computer aimed at business which allowed a single user to execute a single program. Many changes have been introduced over the last 20 years to bring us to where we are now.
    [Show full text]
  • BCIS 1305 Business Computer Applications
    BCIS 1305 Business Computer Applications BCIS 1305 Business Computer Applications San Jacinto College This course was developed from generally available open educational resources (OER) in use at multiple institutions, drawing mostly from a primary work curated by the Extended Learning Institute (ELI) at Northern Virginia Community College (NOVA), but also including additional open works from various sources as noted in attributions on each page of materials. Cover Image: “Keyboard” by John Ward from https://flic.kr/p/tFuRZ licensed under a Creative Commons Attribution License. BCIS 1305 Business Computer Applications by Extended Learning Institute (ELI) at NOVA is licensed under a Creative Commons Attribution 4.0 International License, except where otherwise noted. CONTENTS Module 1: Introduction to Computers ..........................................................................................1 • Reading: File systems ....................................................................................................................................... 1 • Reading: Basic Computer Skills ........................................................................................................................ 1 • Reading: Computer Concepts ........................................................................................................................... 1 • Tutorials: Computer Basics................................................................................................................................ 1 Module 2: Computer
    [Show full text]
  • How Can I Test My Memory
    How can I test my memory A defective memory module(s) can cause various issues on your computer. These are just a few of the possible issues you may encounter. It is important to remember the issues below can also be caused by more than just defective memory. 1. Computer doesn't boot and/or you get a beep code. Check your motherboard manual for the error code if you are unsure what it means. 2. Random computer crashes including BSOD (Blue Screen of Death), General Protection Fault error messages, Illegal Operations, Fatal Exceptions, etc. 3. Random Reboots. 4. OS or other application installation failure. How can we be sure that the memory is defective before starting the RMA exchange process? There are programs available that are designed to test the computer's memory. We recommend Memtest86+ to test your computer's memory. Please visit this link to download and install Memtest86+ for an ISO image or USB Drive: Link To make a bootable Floppy from with in Windows, First you would download the memtest utility to your HDD, then using www.winzip.com extract it to the same directory. Please then get a floppy and do a fresh full format on it, and if there are any bad sectors just throw it away and get a new one. Then click on the install.bat file in the directory where you downloaded and extracted the files and follow the on screen prompts. To make a Bootable CD from within windows you would download the ISO image that has a .zip extension.
    [Show full text]
  • CS5460/6460: Operating Systems Lecture 6: Interrupts and Exceptions
    CS5460/6460: Operating Systems Lecture 6: Interrupts and Exceptions Several slides in this lecture use slides developed by Don Porter Anton Burtsev January, 2014 Why do we need interrupts? Remember: hardware interface is designed to help OS Why do we need interrupts? ● Fix an abnormal condition ● Page not mapped in memory ● Notifications from external devices ● Network packet received ● Preemptive scheduling ● Timer interrupt ● Secure interface between OS and applications ● System calls Two types Synchronous ● Exceptions – react to an abnormal condition ● Map the swapped out page back to memory ● Invoke a system call ● Intel distinguishes 3 types: faults, traps, aborts Asynchronous ● Interrupts – preempt normal execution ● Notify that something has happened (new packet, disk I/O completed, timer tick, notification from another CPU) Handling interrupts and exceptions ● Same procedure ● Stop execution of the current program ● Start execution of a handler ● Processor accesses the handler through an entry in the Interrupt Descriptor Table (IDT) ● Each interrupt is defined by a number ● E.g., 14 is pagefault, 3 debug ● This number is an index into the interrupt table (IDT) CPU Memory Interrupt descriptor Interrupt descriptor Interrupt descriptor ● Interrupt gate disables interrupts ● Clears the IF flag in EFLAGS register ● Trap gate doesn't ● IF flag is unchanged x86 interrupt table Device IRQs 128 = Linux System Call … … … 0 31 47 255 Software Configurable Reserved for the CPU Interrupts ● Each type of interrupt is assigned an index from
    [Show full text]
  • CS152: Computer Systems Architecture Virtual Memory
    CS152: Computer Systems Architecture Virtual Memory Sang-Woo Jun Winter 2019 Large amount of material adapted from MIT 6.004, “Computation Structures”, Morgan Kaufmann “Computer Organization and Design: The Hardware/Software Interface: RISC-V Edition”, and CS 152 Slides by Isaac Scherson So far… Operating System goals: o Protection and privacy: Processes cannot access each other’s data o Abstraction: OS hides details of underlying hardware • e.g., processes open and access files instead of issuing raw commands to disk o Resource management: OS controls how processes share hardware resources (CPU, memory, disk, etc.) Key enabling technologies: o User mode + supervisor mode w/ privileged instructions o Exceptions to safely transition into supervisor mode o Virtual memory to provide private address spaces and abstract the machine’s storage resources (today!) Remember context switching All running processes still share the same memory space o Does not support isolation between processes o e.g., If process 1 uses too much stack space, it will overrun process 2’s stack space o e.g., If process 1 maliciously writes to random address regions, it can overwrite process 2’s stack space Stack Stack Stack Timer Jump to Process 1 Process 1 Process 1 Stack pointer interrupt Proc1’s register values process 2 Proc1’s register values Stack pointer Process 2 Process 2 Proc2’s register values Stack pointer Isolation solution: Virtual Memory Illusion of a large, private, uniform store Virtual address o Address generated by a process (given to LW, SW,
    [Show full text]
  • CYBERSECURITY When Will You Be Hacked?
    SUFFOLK ACADEMY OF LAW The Educational Arm of the Suffolk County Bar Association 560 Wheeler Road, Hauppauge, NY 11788 (631) 234-5588 CYBERSECURITY When Will You Be Hacked? FACULTY Victor John Yannacone, Jr., Esq. April 26, 2017 Suffolk County Bar Center, NY Cybersecurity Part I 12 May 2017 COURSE MATERIALS 1. A cybersecurity primer 3 – 1.1. Cybersecurity practices for law firms 5 – 1.2. Cybersecurity and the future of law firms 11 – 2. Information Security 14 – 2.1. An information security policy 33 – 2.2. Data Privacy & Cloud Computing 39 – 2.3. Encryption 47 – 3. Computer security 51 – 3.1. NIST Cybersecurity Framework 77 – 4. Cybersecurity chain of trust; third party vendors 113 – 5. Ransomware 117 – 5.1. Exploit kits 132 – 6. Botnets 137 – 7. BIOS 139 – 7.1. Universal Extensible Firmware Interface (UEFI) 154– 8. Operating Systems 172 – 8.1. Microsoft Windows 197 – 8.2. macOS 236– 8.3. Open source operating system comparison 263 – 9. Firmware 273 – 10. Endpoint Security Buyers Guide 278 – 11. Glossaries & Acronym Dictionaries 11.1. Common Computer Abbreviations 282 – 11.2. BABEL 285 – 11.3. Information Technology Acronymns 291 – 11.4. Glossary of Operating System Terms 372 – 2 Cyber Security Primer Network outages, hacking, computer viruses, and similar incidents affect our lives in ways that range from inconvenient to life-threatening. As the number of mobile users, digital applications, and data networks increase, so do the opportunities for exploitation. Cyber security, also referred to as information technology security, focuses on protecting computers, networks, programs, and data from unintended or unauthorized access, change, or destruction.
    [Show full text]
  • IMF: Inferred Model-Based Fuzzer Hyungseok Han Sang Kil Cha KAIST KAIST [email protected] [email protected]
    IMF: Inferred Model-based Fuzzer HyungSeok Han Sang Kil Cha KAIST KAIST [email protected] [email protected] ABSTRACT aim of which is to find kernel vulnerabilities. There are also kernel- Kernel vulnerabilities are critical in security because they naturally level formal verification approaches [29, 30], but all such techniques allow attackers to gain unprivileged root access. Although there has require the source code. been much research on finding kernel vulnerabilities from source The current best practice for finding kernel vulnerabilities on code, there are relatively few research on kernel fuzzing, which is commodity OSes is fuzzing, which involves repeatedly calling an a practical bug finding technique that does not require any source arbitrary sequence of kernel API functions, e.g., system calls, with code. Existing kernel fuzzing techniques involve feeding in random randomly generated parameter values. There are various kernel input values to kernel API functions. However, such a simple ap- fuzzers developed by security experts and practitioners [4, 25, 37, proach does not reveal latent bugs deep in the kernel code, because 40, 53, 57] as well as academic researchers [17, 19, 55], but all of many API functions are dependent on each other, and they can them share the same idea: they call random kernel API functions quickly reject arbitrary parameter values based on their calling with randomly generated parameter values. context. In this paper, we propose a novel fuzzing technique for Unfortunately, all of the existing kernel fuzzers are associated commodity OS kernels that leverages inferred dependence model with a high failure rate in terms of how many API functions can be between API function calls to discover deep kernel bugs.
    [Show full text]
  • A Systematic Evaluation of Transient Execution Attacks and Defenses
    A Systematic Evaluation of Transient Execution Attacks and Defenses Claudio Canella1, Jo Van Bulck2, Michael Schwarz1, Moritz Lipp1, Benjamin von Berg1, Philipp Ortner1, Frank Piessens2, Dmitry Evtyushkin3, Daniel Gruss1 1 Graz University of Technology, 2 imec-DistriNet, KU Leuven, 3 College of William and Mary Abstract instruction which has not been executed (and retired) yet. Hence, to keep the pipeline full at all times, it is essential to Research on transient execution attacks including Spectre predict the control flow, data dependencies, and possibly even and Meltdown showed that exception or branch mispredic- the actual data. Modern CPUs, therefore, rely on intricate mi- tion events might leave secret-dependent traces in the CPU’s croarchitectural optimizations to predict and sometimes even microarchitectural state. This observation led to a prolifera- re-order the instruction stream. Crucially, however, as these tion of new Spectre and Meltdown attack variants and even predictions may turn out to be wrong, pipeline flushes may be more ad-hoc defenses (e.g., microcode and software patches). necessary, and instruction results should always be committed Both the industry and academia are now focusing on finding according to the intended in-order instruction stream. Pipeline effective defenses for known issues. However, we only have flushes may occur even without prediction mechanisms, as on limited insight on residual attack surface and the completeness modern CPUs virtually any instruction can raise a fault (e.g., of the proposed defenses. page fault or general protection fault), requiring a roll-back In this paper, we present a systematization of transient of all operations following the faulting instruction.
    [Show full text]
  • QD/QS Release Notes Kingston 08.20.Xx.00
    QD/QS Release Notes Kingston 08.20.xx.00 Product Firmware Version: 08.20.27.00 Date November 2017 Contents Introduction . 1 Purpose for This Release . 2 Resolved Issues . 2 Known Issues . 12 Contacting Quantum . 13 Introduction StorNext QD6000, QS1200, and QS2400 firmware is shipped as a bundle from Quantum. When updating to the 08.20.27.00 controller firmware, it is necessary to use SANtricity version 11.30 or later. Caution: The Kingston 08.20.27.00 controller firmware is for the Pikes Peak controllers in the QD6000, QS1200, and QS2400 systems. COPYRIGHT STATEMENT © 2017 Quantum Corporation. All rights reserved. Your right to copy this manual is limited by copyright law. Making copies or adaptations without prior written authorization of Quantum Corporation is prohibited by law and constitutes a punishable violation of the law. Artico, Be Certain (and the Q brackets design), DLT, DXi, DXi Accent, DXi V1000, DXi V2000, DXi V4000, DXiV-Series, FlexTier, Lattus, the Q logo, The Q Quantum logo, Q-Cloud, Quantum (and the Q brackets design), the SuperLoader, Symform, the Symform logo (and design), vmPRO, and Xcellis are either registered trademarks or trademarks of Quantum Corporation and its affiliates in the United States and/or other countries. All other trademarks are the property of their respective owners. Products mentioned herein are for identification purposes only and may be registered trademarks or trademarks of their respective companies. All other brand names or trademarks are the property of their respective owners. Quantum specifications are subject to change. 6-68255-05 Rev G, November 2017 *6-68255-05 QD/QS Release Notes 6-68255-05 Rev G November 2017 Purpose for This Release Release 08.20.27.00 is the latest firmware release and is a maintenance release.
    [Show full text]
  • ANTI-UNPACKER TRICKS CURRENT Peter Ferrie, Senior Anti-Virus Researcher, Microsoft Corporation
    ANTI-UNPACKER TRICKS CURRENT Peter Ferrie, Senior Anti-Virus Researcher, Microsoft Corporation Abstract Unpackers are as old as the packers themselves, but which the page will be restored to its non-present state. In anti-unpacking tricks are a more recent development. These either case, the page address is kept in a list. In the event of anti-unpacking tricks have developed quickly in number and, in exceptions triggered by execution of non-executable or non- some cases, complexity. In this paper, we will describe some of present pages, the page address is compared to the entries in the most common anti-unpacking tricks, along with some that list. A match indicates the execution of newly-written countermeasures. code, and is a possible host entrypoint. INTRODUCTION I. ANTI-UNPACKING BY ANTI-DUMPING nti-unpacking tricks can come in different forms, A depending on what kind of unpacker they want to attack. a. SizeOfImage The unpacker can be in the form of a memory-dumper, a debugger, an emulator, a code-buffer, or a W-X interceptor. The simplest of anti-dumping tricks is to change the It can be a tool in a virtual machine. There are corresponding SizeOfImage value in the Process Environment Block tricks for each of these, and they will be discussed separately. (PEB). This interferes with process access, including preventing a debugger from attaching to the process. It - A memory-dumper dumps the process memory of the running process, without regard to the code inside it. also breaks tools such as LordPE in default mode, among others.
    [Show full text]