Gpus: the Hype, the Reality, and the Future

Total Page:16

File Type:pdf, Size:1020Kb

Gpus: the Hype, the Reality, and the Future Uppsala Programming for Multicore Architectures Research Center GPUs: The Hype, The Reality, and The Future David Black-Schaffer Assistant Professor, Department of Informaon Technology Uppsala University David Black-Schaffer Uppsala University / Department of Informaon Technology 25/11/2011 | 2 Today 1. The hype 2. What makes a GPU a GPU? 3. Why are GPUs scaling so well? 4. What are the problems? 5. What’s the Future? David Black-Schaffer Uppsala University / Department of Informaon Technology 25/11/2011 | 3 THE HYPE David Black-Schaffer Uppsala University / Department of Informaon Technology 25/11/2011 | 4 How Good are GPUs? 100x 3x David Black-Schaffer Uppsala University / Department of Informaon Technology 25/11/2011 | 5 Real World SoVware • Press release 10 Nov 2011: – “NVIDIA today announced that four leading applicaons… have added support for mul<ple GPU acceleraon, enabling them to cut simulaon mes from days to hours.” • GROMACS – 2-3x overall – Implicit solvers 10x, PME simulaons 1x • LAMPS – 2-8x for double precision – Up to 15x for mixed • QMCPACK – 3x 2x is AWESOME! Most research claims 5-10%. David Black-Schaffer Uppsala University / Department of Informaon Technology 25/11/2011 | 6 GPUs for Linear Algebra 5 CPUs = 75% of 1 GPU StarPU for MAGMA David Black-Schaffer Uppsala University / Department of Informaon Technology 25/11/2011 | 7 GPUs by the Numbers (Peak and TDP) 5 791 675 4 192 176 3 Intel 32nm vs. 40nm 36% smaller per transistor 2 244 250 3.0 Normalized to Intel 3960X 130 172 51 3.3 2.3 2.4 1 1.5 0.9 0 WaEs GFLOP Bandwidth GHz Transistors Intel 3960X Nvidia GTX 580 AMD 6970 David Black-Schaffer Uppsala University / Department of Informaon Technology 25/11/2011 | 8 Efficiency (DP, peak) But how close to peak GPUs are enormously 4 do you really get? more efficient designs 400 for doing FLOPs 3 300 2 200 GFLOP/W 1 100 FLOP/cycle/B Transistors 0 0 Intel 3960X GTX 580 AMD 6970 Energy Efficiency Design Efficiency David Black-Schaffer Uppsala University / Department of Informaon Technology 25/11/2011 | 9 Efficiency in Perspec<ve Energy Efficiency Nvidia4 says that ARM + Laptop GPU LINPACK: Green 500 #1 7.5GFLOPS/W Blue Gene/Q LINPACK: 3 Green 500 #6 GPU/CPU 2 GFLOP/W 1 Peak Peak Peak Actual Actual 0 Intel 3960X GTX 580 AMD 6970 Blue Gene/Q DEGIMA Cluster David Black-Schaffer Uppsala University / Department of Informaon Technology 25/11/2011 | 11 Intel’s Response • Larabee – Manycore x86-“light” to compete with Nvidia/AMD in graphics and compute – Didn’t work out so well (despite huge fab advantages — graphics is hard) • Reposi/oned it as an HPC co-processor – Knight’s Corner – 1TF double precision in a huge (expensive) single 22nm chip – At 300W this would beat Nvidia’s peak efficiency today (40nm) David Black-Schaffer Uppsala University / Department of Informaon Technology 25/11/2011 | 12 Show Me the Money 4 9.4 3 2 1 Revenue in Billion USD 50% of this is 0 GPU in HPC AMD Q3 Nvidia Q3 Intel Q3 Professional Graphics Embedded Processors David Black-Schaffer Uppsala University / Department of Informaon Technology 25/11/2011 | 13 WHAT MAKES A GPU A GPU? David Black-Schaffer Uppsala University / Department of Informaon Technology 25/11/2011 | 14 GPU Characteris<cs • Architecture • Programming/Interface – Data parallel processing – Data parallel kernels – Hardware thread scheduling – Throughput-focused – High memory bandwidth – Limited synchronizaon – Graphics rasterizaon units – Limited OS interac<on – Limited caches (with texture filtering hardware) David Black-Schaffer Uppsala University / Department of Informaon Technology 25/11/2011 | 15 GPU Innovaons • SMT (for latency hiding) – Massive numbers of threads – Programming SMT is far easier than SIMD • SIMT (thread groups) – Amor<ze scheduling/control/data access – Warps, wavefronts, work-groups, gangs • Memory systems op/mized for graphics – Special storage formats – Texture filtering in the memory system – Bank op<mizaons across threads • Limited synchronizaon – Improves hardware scalability (They didn’t invent any of these, but they made them successful.) David Black-Schaffer Uppsala University / Department of Informaon Technology 25/11/2011 | 16 WHY ARE GPUS SCALING SO WELL? David Black-Schaffer Uppsala University / Department of Informaon Technology 25/11/2011 | 17 Lots of Room to Grow the Hardware Simple cores Simple control But, they do have a lot… – Short pipelines – Limited context switching – TLBs for VM – No branch predic<on – Limited processes – I-caches – In-order – (But do have to schedule – Complex hardware thread Simple memory system 1000s of threads…) schedulers – Limited caches* Lack of OS-level issues – No coherence – Memory allocaon Trading off simplicity – Split address space* – Preemp<on for features and programmability. 1600 200 1200 400 1200 150 900 300 800 100 600 200 FLOP/cycle GFLOPs (SP) 400 50 Bandwidth (GB/s) 300 100 FLOP/cycle/B Transistors 0 0 0 0 G80 GT200 GF100 G80 GT200 GF100 GFLOP (SP) Bandwidth Architecture Efficiency Design Efficiency David Black-Schaffer Uppsala University / Department of Informaon Technology 25/11/2011 | 18 “Nice” Programming Model void kernel calcSin(global float *data) { • All GPU programs have: int id = get_global_id(0); data[id] = sin(data[id]); – Explicit parallelism } – Hierarchical structure Synchronization OK.! – Restricted synchronizaon – Data locality No Synchronization.! • Inherent in graphics • Enforced in compute by performance – Latency tolerance Expensive • Easy to scale! Cheap David Black-Schaffer Uppsala University / Department of Informaon Technology 25/11/2011 | 19 Why are GPUs Scaling So Well? • Room in the hardware design • Scalable soVware They’re not burdened with 30 years of cru6 and legacy code… …lucky them. David Black-Schaffer Uppsala University / Department of Informaon Technology 25/11/2011 | 20 WHERE ARE THE PROBLEMS? David Black-Schaffer Uppsala University / Department of Informaon Technology 25/11/2011 | 21 Amdahl’s Law • Always have serial code – GPU single threaded performance is terrible • Soluon: Heterogeneity – A few fat latency-op/mized cores – Many thin throughput-opmized cores – Plus hard-coded accelerators • Nvidia Project Denver • ARM for latency 100 99% Parallel (91x) • GPU for throughput • AMD Fusion 10 90% Parallel (10x) • x86 for latency 75% Parallel (4x) • GPU for throughput Maximum Speedup • 1 Intel MIC 1 2 4 8 16 32 64 128 256 512 1024 • x86 for latency Number of Cores • X86-“light” for throughput Limits of Amdahl’s Law David Black-Schaffer Uppsala University / Department of Informaon Technology 25/11/2011 | 22 It’s an Accelerator… • Moving data to the GPU is slow… • Moving data from the GPU is slow… • Moving data to/from the GPU is really slow. • Limited data storage • Limited interac<on with OS 192GB/s GPU GB/s CPU 51GB/s GRAM 5 DRAM Nvidia GTX 580 Intel 3960X 1.5GB 16GB 529mm2 PCIe 3.0 435mm2 10GB/s David Black-Schaffer Uppsala University / Department of Informaon Technology 25/11/2011 | 23 Legacy Code • Code lives forever – Amdahl: Even op<mizing the 90% of hot code limits speedup to 10x – Many won’t invest in proprietary technology • Programming models are immature – CUDA mature low-level Nvidia, PGI – OpenCL immature low-level Nvidia, AMD, Intel, ARM, Altera, Apple – OpenHMPP mature high-level CAPS – OpenACC immature high-level CAPS, Nvidia, Cray, PGI David Black-Schaffer Uppsala University / Department of Informaon Technology 25/11/2011 | 24 Code that Doesn’t Look Like Graphics • If it’s not painfully data-parallel you have to redesign your algorithm – Example: scan-based techniques for zero coun<ng in JPEG – Why? It’s only 64 entries! • Single-threaded performance is terrible. Need to parallelize. • Overhead of transferring data to CPU is too high. • If it’s not accessing memory well you have to re-order your algorithm – Example: DCT in JPEG • Need to make sure your access to local memory has no bank conflicts across threads. • Libraries star/ng to help – Lack of composability – Example: Combining linear algebra operaons to keep data on the device • Most code is not purely data-parallel – Very expensive to synchronize with the CPU (data transfer) – No effec<ve support for task-based parallelism – No ability to launch kernels from within kernels David Black-Schaffer Uppsala University / Department of Informaon Technology 25/11/2011 | 25 Corollary: What are GPUs Good For? • Data parallel code – Lots of threads – Easy to express parallelism (no SIMD nas<ness) • High arithme/c intensity and simple control flow – Lots of FPUs – No branch predictors • High reuse of limited data sets – Very high bandwidth to memory (1-6GB) – Extremely high bandwidth to local memory (16-64kB) • Code with predictable access paerns – Small (or no) caches – User-controlled local memories David Black-Schaffer Uppsala University / Department of Informaon Technology 25/11/2011 | 26 WHAT’S THE FUTURE OF GPUS? ! big.LITTLE Task Migration Use Model In the big.LITTLE task migration use model the OS and applications only ever execute on Cortex-A15 or Cortex-A7 and never both processors at the same time. This use-model is a natural extension to the Dynamic Voltage and Frequency Scaling (DVFS), operating points provided by current mobile platforms with a single application processor to allow the OS to match the performance25/11/2011 | 27 of the platform to the David Black-Schaffer Uppsala University / Department of Informaon Technology performance required by the application. ! However, in a Cortex-A15-Cortex-A7 platform these operating points are applied both to Cortex-A15 and Cortex-A7. When Cortex-A7 is executing the OS can tune the operating points as it would for an existing platform with a single applications processor. Once Cortex-A7 is at its highest operating point if more performance is required a task migrationIntroduction can be invoked that picks up the OS and applications and ! moves them to Cortex-A15.
Recommended publications
  • Accelerating Applications with Pattern-Specific Optimizations On
    Accelerating Applications with Pattern-specific Optimizations on Accelerators and Coprocessors Dissertation Presented in Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy in the Graduate School of The Ohio State University By Linchuan Chen, B.S., M.S. Graduate Program in Computer Science and Engineering The Ohio State University 2015 Dissertation Committee: Dr. Gagan Agrawal, Advisor Dr. P. Sadayappan Dr. Feng Qin ⃝c Copyright by Linchuan Chen 2015 Abstract Because of the bottleneck in the increase of clock frequency, multi-cores emerged as a way of improving the overall performance of CPUs. In the recent decade, many-cores begin to play a more and more important role in scientific computing. The highly cost- effective nature of many-cores makes them extremely suitable for data-intensive computa- tions. Specifically, many-cores are in the forms of GPUs (e.g., NVIDIA or AMD GPUs) and more recently, coprocessers (Intel MIC). Even though these highly parallel architec- tures offer significant amount of computation power, it is very hard to program them, and harder to fully exploit the computation power of them. Combing the power of multi-cores and many-cores, i.e., making use of the heterogeneous cores is extremely complicated. Our efforts have been made on performing optimizations to important sets of appli- cations on such parallel systems. We address this issue from the perspective of commu- nication patterns. Scientific applications can be classified based on the properties (com- munication patterns), which have been specified in the Berkeley Dwarfs many years ago. By investigating the characteristics of each class, we are able to derive efficient execution strategies, across different levels of the parallelism.
    [Show full text]
  • NVIDIA Corp NVDA (XNAS)
    Morningstar Equity Analyst Report | Report as of 14 Sep 2020 04:02, UTC | Page 1 of 14 NVIDIA Corp NVDA (XNAS) Morningstar Rating Last Price Fair Value Estimate Price/Fair Value Trailing Dividend Yield % Forward Dividend Yield % Market Cap (Bil) Industry Stewardship Q 486.58 USD 250.00 USD 1.95 0.13 0.13 300.22 Semiconductors Exemplary 11 Sep 2020 11 Sep 2020 20 Aug 2020 11 Sep 2020 11 Sep 2020 11 Sep 2020 21:37, UTC 01:27, UTC Morningstar Pillars Analyst Quantitative Important Disclosure: Economic Moat Narrow Wide The conduct of Morningstar’s analysts is governed by Code of Ethics/Code of Conduct Policy, Personal Security Trading Policy (or an equivalent of), Valuation Q Overvalued and Investment Research Policy. For information regarding conflicts of interest, please visit http://global.morningstar.com/equitydisclosures Uncertainty Very High High Financial Health — Moderate Nvidia to Buy ARM in $40 Billion Deal with Eyes Set on Data Center Source: Morningstar Equity Research Dominance; Maintain FVE Quantitative Valuation NVDA Business Strategy and Outlook could limit Nvidia’s future growth. a USA Abhinav Davuluri, CFA, Analyst, 19 August 2020 Undervalued Fairly Valued Overvalued Nvidia is the leading designer of graphics processing units Analyst Note that enhance the visual experience on computing Abhinav Davuluri, CFA, Analyst, 13 September 2020 Current 5-Yr Avg Sector Country Price/Quant Fair Value 1.67 1.43 0.77 0.83 platforms. The firm's chips are used in a variety of end On Sept. 13, Nvidia announced it would acquire ARM from Price/Earnings 89.3 37.0 21.4 20.1 markets, including high-end PCs for gaming, data centers, the SoftBank Group in a transaction valued at $40 billion.
    [Show full text]
  • Massively Parallel Computation Using Graphics Processors with Application to Optimal Experimentation in Dynamic Control
    Munich Personal RePEc Archive Massively parallel computation using graphics processors with application to optimal experimentation in dynamic control Morozov, Sergei and Mathur, Sudhanshu Morgan Stanley 10 August 2009 Online at https://mpra.ub.uni-muenchen.de/30298/ MPRA Paper No. 30298, posted 03 May 2011 17:05 UTC MASSIVELY PARALLEL COMPUTATION USING GRAPHICS PROCESSORS WITH APPLICATION TO OPTIMAL EXPERIMENTATION IN DYNAMIC CONTROL SERGEI MOROZOV AND SUDHANSHU MATHUR Abstract. The rapid growth in the performance of graphics hardware, coupled with re- cent improvements in its programmability has lead to its adoption in many non-graphics applications, including a wide variety of scientific computing fields. At the same time, a number of important dynamic optimal policy problems in economics are athirst of computing power to help overcome dual curses of complexity and dimensionality. We investigate if computational economics may benefit from new tools on a case study of imperfect information dynamic programming problem with learning and experimenta- tion trade-off, that is, a choice between controlling the policy target and learning system parameters. Specifically, we use a model of active learning and control of a linear au- toregression with the unknown slope that appeared in a variety of macroeconomic policy and other contexts. The endogeneity of posterior beliefs makes the problem difficult in that the value function need not be convex and the policy function need not be con- tinuous. This complication makes the problem a suitable target for massively-parallel computation using graphics processors (GPUs). Our findings are cautiously optimistic in that new tools let us easily achieve a factor of 15 performance gain relative to an implementation targeting single-core processors.
    [Show full text]
  • Parallelization Schemes & GPU Acceleration
    Parallelization schemes & GPU Acceleration Erik Lindahl / Szilárd Páll GROMACS USA workshop September 13, 2013 Outline ● MD algorithmic overview ● Motivation: why parallelize/accelerate MD? ● Acceleration on CPUs ● Parallelization schemes ● Heterogeneous/GPU acceleration GROMACS USA workshop 2 Important technical terms ● Hardware: – CPU core: physical, logical, "Bulldozer" module – Node: compute machine (!= mdrun “node”) – Accelerators: GPUs, Intel MIC ● Algorithmic/parallelization: – Accelerated code, compute kernels: CPU SIMD: SSE, AVX; GPU SIMT: CUDA – multi-threading: OpenMP (thread-MPI) – SPMD, MPMD: MPI GROMACS USA workshop 3 Molecular dynamics: algorithm overview Neighbor search/DD step: every 10-50 iterations MD step NS, DD Bonded F Non-bonded F PME Integration Constraints ~ milliseconds GROMACS USA workshop 4 Why parallelize/accelerate? ● Need for speed: – MD is computationally demanding – but a fast* simulation needs: → short time-step → strong scaling Neighbor search/DD step: every 10-50 iterations MD step NS, DD Bonded F Non-bonded F PME Integration Constraints Goal: making it as short as possible currently at peak: ~100s of microsec. GROMACS USA workshop 5 Motivation: hardware evolution ● Hardware is increasingly: ● parallel on multiple levels ● heterogenous: accelerators ` + x2 x100-1000s SIMD & SIMT multicore, NUMA network: topology, memory & cache accelerator:GROMACS PCI-E, USA topologyworkshop bandwidth, latency 6 Motivation: need to keep up! ● Multiple levels of harware parallelism → need to address each level with suitable
    [Show full text]
  • The GPU Computing Revolution
    The GPU Computing Revolution From Multi-Core CPUs to Many-Core Graphics Processors A Knowledge Transfer Report from the London Mathematical Society and Knowledge Transfer Network for Industrial Mathematics By Simon McIntosh-Smith Copyright © 2011 by Simon McIntosh-Smith Front cover image credits: Top left: Umberto Shtanzman / Shutterstock.com Top right: godrick / Shutterstock.com Bottom left: Double Negative Visual Effects Bottom right: University of Bristol Background: Serg64 / Shutterstock.com THE GPU COMPUTING REVOLUTION From Multi-Core CPUs To Many-Core Graphics Processors By Simon McIntosh-Smith Contents Page Executive Summary 3 From Multi-Core to Many-Core: Background and Development 4 Success Stories 7 GPUs in Depth 11 Current Challenges 18 Next Steps 19 Appendix 1: Active Researchers and Practitioner Groups 21 Appendix 2: Software Applications Available on GPUs 23 References 24 September 2011 A Knowledge Transfer Report from the London Mathematical Society and the Knowledge Transfer Network for Industrial Mathematics Edited by Robert Leese and Tom Melham London Mathematical Society, De Morgan House, 57–58 Russell Square, London WC1B 4HS KTN for Industrial Mathematics, Surrey Technology Centre, Surrey Research Park, Guildford GU2 7YG 2 THE GPU COMPUTING REVOLUTION From Multi-Core CPUs To Many-Core Graphics Processors AUTHOR Simon McIntosh-Smith is head of the Microelectronics Research Group at the Univer- sity of Bristol and chair of the Many-Core and Reconfigurable Supercomputing Conference (MRSC), Europe’s largest conference dedicated to the use of massively parallel computer architectures. Prior to joining the university he spent fifteen years in industry where he designed massively parallel hardware and software at companies such as Inmos, STMicro- electronics and Pixelfusion, before co-founding ClearSpeed as Vice-President of Architec- ture and Applications.
    [Show full text]
  • Understanding Throughput- Oriented Architectures
    Understanding Throughput- Oriented Architectures Cedric Nugteren GPU Mini Symposium 25th of January, 2011 Contents • Motivation • GPUs in supercomputers • Performance per Watt • Example applications • Throughput-oriented architectures • Programming GPUs • Current and future architectures • Summary / GPU Mini Symposium 25-01-2011 PAGE 2 GPUs in supercomputers Taken from: Top500 Supercomputer Websites Found at ‘www.top500.org’, November 2010 / GPU Mini Symposium 25-01-2011 PAGE 3 Performance per Watt Taken from: Bill Dally In ‘GPU Computing: To Exascale and Beyond’, 2010 / GPU Mini Symposium 25-01-2011 PAGE 4 Performance per Watt NVIDIA GeForce 10000 ] GTX480 1000 GTX285 GTS250 GFLOPS GT220 100 G210M 10 Performance [ Performance 1 0,1 1 10 100 1000 Power [W] / GPU Mini Symposium 25-01-2011 PAGE 5 Performance per Watt NVIDIA GeForce AMD Radeon CPU 10000 ] HD5870 HD5770 GTX480 1000 GTX285 GTS250 GFLOPS GT220 100 Core i7-960 HD5430 G210M 10 Performance [ Performance Atom 330 1 0,1 1 10 100 1000 Power [W] / GPU Mini Symposium 25-01-2011 PAGE 6 Performance per Watt NVIDIA GeForce AMD Radeon PowerVR CPU 10000 ] HD5870 HD5770 GTX480 1000 GTX285 GTS250 GFLOPS GT220 100 Core i7-960 HD5430 G210M 543MP8 10 Performance [ Performance Atom 330 1 545 0,1 1 10 100 1000 Power [W] / GPU Mini Symposium 25-01-2011 PAGE 7 Example applications / GPU Mini Symposium 25-01-2011 PAGE 8 Contents • Motivation • Throughput-oriented architectures • Example: The NVIDIA Fermi GPU • Hardware multithreading • Many simple processing units • SIMD execution • Programming GPUs
    [Show full text]
  • Modern GPU Architectures
    4/22/12 Agenda/GPU Decoder Ring • Fermi / GF100 / GeForce GTX 480 – “Fermi Refined” / GF110 / GeForce GTX 580 – “LiPle Fermi” / GF104 / GeForce GTX 460 Modern GPU Architectures • Cypress / Evergreen / RV870 / Radeon HD 5870 – Cayman / Northern Islands / Radeon HD 6970 • TahiV / Southern Islands / GCN / Radeon HD 7970 Varun Sampath • Kepler / GK104 / GeForce GTX 680 University of Pennsylvania • Future CIS 565 - Spring 2012 – Project Denver – Heterogeneous System Architecture From G80/GT200 to Fermi Unified Address Space • GPU Compute becomes a driver for innovaon – Unified address space – Control flow advancements – ArithmeVc performance – Atomics performance – Caching – ECC (is this seriously a graphics card?) – Concurrent kernel execuVon & fast context switching • PTX 2.0 ISA supports 64-bit virtual addressing (40-bit in Fermi) • CUDA 4.0+: Address space shared with CPU • Advantages? Image from NVIDIA 1 4/22/12 Unified Address Space Control Flow Advancements cudaMemcpy(d_buf, h_buf, sizeof(h_buf), • Predicated instrucVons cudaMemcpyDefault) • RunVme manages where buffers live – avoid branching stalls (no branch predictor) • Enables copies between different devices (not • Indirect funcVon calls: only GPUs) via DMA call{.uni} fptr, flist; – Called GPUDirect • What does this enable support for? – Useful for HPC clusters • Pointers for global and shared memory are equivalent Control Flow Advancements ArithmeVc • Predicated instrucVons • Improved support for IEEE 754-2008 floang – avoid branching stalls (no branch predictor) point standards • Indirect
    [Show full text]
  • Trends in Heterogeneous Systems Architectures (And How They'll Affect Parallel Programming Models)
    Trends in Heterogeneous Systems Architectures (and how they'll affect parallel programming models) Simon McIntosh-Smith [email protected] Head of Microelectronics Research University of Bristol, UK 1 ! "Moore’s Law today Average Moore’s Law = 2x/2yrs 20-30B transistors 2x/3yrs 6-7B transistors 2x/2yrs ~2B transistors High-performance MPU, e.g. Intel Nehalem Cost-performance MPU, e.g. Nvidia Tegra http://www.itrs.net/Links/2011ITRS/2011Chapters/2011ExecSum.pdf 2 ! "Herb Sutter’s new outlook http://herbsutter.com/welcome-to-the-jungle/ “In the twilight of Moore’s Law, the transitions to multicore processors, GPU computing, and HaaS cloud computing are not separate trends, but aspects of a single trend – mainstream computers from desktops to ‘smartphones’ are being permanently transformed into heterogeneous supercomputer clusters. Henceforth, a single compute-intensive application will need to harness different kinds of cores, in immense numbers, to get its job done.” “The free lunch is over. Now welcome to the hardware jungle.” 3 ! "Four causes of heterogeneity •" Multiple types of programmable core •" CPU (lightweight, heavyweight) •" GPU •" Others (accelerators, …) •" Interconnect asymmetry •" Memory hierarchies •" Software (OS, middleware, tools, …) 4 ! "Heterogeneous Systems AMD Llano Fusion APUs Intel MIC FP7 Mont Blanc ARM + GPU NVIDIA Tegra, Project Denver 5 ! "Heterogeneity is mainstream Quad-core ARM Cortex A9 CPU Dual-core ARM 1.4GHz, ARMv7s CPU Quad-core SGX543MP4+ Imagination GPU Triple-core SGX554MP4 Imagination GPU Most
    [Show full text]
  • 3-1-11: Master Deck- Please Save to Your Desktop
    The Evolution of Modern Parallel Computing Sanford H. Russell Director of CUDA Marketing, NVIDIA Corporation Taipei | May 19 , 2011 GPU Computing Is not CPU vs. GPU It is CPU + GPU 2 GPU Computing Application Code Rest of Sequential Only Critical Functions CPU Code GPU Parallelize using CUDA CPU Programming Model + 3 GPU Computing Milestones 2002 2007 2007 GPGPU G80 NVIDIA First Parallel C Compiler Programming on Computing Architecture top of OGL (Single Precision) C SDK for GPU 4 GPU Computing Milestones 2009 2010 1st True HPC Class GPU Industry Standard IDE Fermi Architecture Parallel Nsight for DP, ECC and C++ support Microsoft Visual Studio 5 Tesla GPUs Power 3 of Top 5 Supercomputers #1 : Tianhe-1A #3 : Nebulae #4 : Tsubame 2.0 7168 Tesla GPU’s 2.5 PFLOPS 4650 Tesla GPU’s 1.2 PFLOPS 4224 Tesla GPU’s 1.194 PFLOPS 6 Tesla in 3 of Top 5 Supercomputers Performance 2500 2000 1500 Gigaflops 1000 500 0 Tianhe-1A Jaguar Nebulae Tsubame Hopper II 7 Tesla Best Performance/Watt 2500 8 Power 7 2000 6 1500 5 4 Gigaflops 1000 3 Megawatts 2 500 1 0 0 Tianhe-1A Jaguar Nebulae Tsubame Hopper II 8 World’s Fastest HPC Processor Tesla M2090: The 512 Core Fermi 512 CUDA Cores 665 GFlops 178 GB/s memory B/W 9 Industry and Research Partners Oil and gas Edu/Research Government Life Sciences Finance Manufacturing Reverse Time Astrophysics Signal Processing Bio-chemistry Risk Analytics Structural Migration Molecular Satellite Imaging Bio-informatics Monte Carlo Mechanics Kirchoff Time Dynamics Video Analytics Material Science Options Pricing Computational
    [Show full text]
  • Low Overhead Dynamic Binary Translation for ARM
    Low Overhead Dynamic Binary Translation for ARM A THESIS SUBMITTED TO THE UNIVERSITY OF MANCHESTER FOR THE DEGREE OF DOCTOR OF PHILOSOPHY IN THE FACULTY OF SCIENCE AND ENGINEERING. 2016 Bernard Amanieu d’Antras School of Computer Science 2 Contents Abstract 11 Declaration 12 Copyright 13 Acknowledgments 14 1 Introduction 15 1.1 Binary translation . 16 1.2 Contributions . 19 2 Dynamic Binary Translation 23 2.1 Code caches . 24 2.2 Multi-threading . 27 2.3 Environment . 28 2.4 Transparency . 30 2.5 MAMBO-X64 . 32 2.5.1 Binary translator . 34 2.5.2 System emulator . 36 2.6 Summary . 39 3 3 Optimizing indirect branches in dynamic binary translators 40 3.1 Hardware-assisted function returns . 43 3.1.1 Software return address stack . 44 3.1.2 Hardware return address prediction . 45 3.1.3 Return address stack elision . 46 3.1.4 Overflow and underflow handling . 50 3.1.5 Misprediction handling . 51 3.1.6 Unlinking . 54 3.2 Branch table inference . 55 3.2.1 Detecting branch tables . 56 3.2.2 Translating branch tables . 58 3.3 Fast atomic hash tables . 60 3.3.1 Hash table operations . 60 3.3.2 SPC and TPC packing . 64 3.4 Evaluation . 65 3.4.1 Experimental setup . 65 3.4.2 MAMBO-X64 . 67 3.4.3 Hardware-assisted function returns . 68 3.4.4 Branch table inference . 72 3.4.5 Fast atomic hash tables . 72 3.5 Related work . 76 3.5.1 Indirect branch handling . 76 3.5.2 Function return handling .
    [Show full text]
  • Msc Informatics Eng
    Computing Systems & Performance Beyond Vector/SIMD architectures • Vector/SIMD-extended architectures are hybrid approaches MSc Informatics Eng. – mix scalar + vector operation capabilities on a single device – highly pipelined approach to reduce memory access penalty – tightly-closed access to shared memory: lower latency 2011/12 • Evolution of Vector/SIMD-extended architectures – CPU cores with wider vectors and/or SIMD cores: A.J.Proença • DSP VLIW cores with vector capabilities: Texas Instrument • PPC cores coupled with SIMD cores: Cell Broadband Engine • ARM64 cores coupled with SIMD cores: project Denver (NVidia) • future x86 hybrid cores: Intel, AMD ... Data Parallelism 2 (Cell BE, GPU, ...) – devices with no scalar processor: accelerator devices • penalty on disjoint physical memories (most slides are borrowed) • based on the GPU architecture: SIMD—>SIMT to hide memory latency • ISA-free architecture, code compiled to silica: FPGA AJProença, Computer Systems & Performance, MEI, UMinho, 2011/12 1 AJProença, Computer Systems & Performance, MEI, UMinho, 2011/12 2 Texas Instruments: Keystone DSP architecture Cell Broadband Engine (1) AJProença, Computer Systems & Performance, MEI, UMinho, 2011/12 3 AJProença, Computer Systems & Performance, MEI, UMinho, 2011/12 4 Cell Broadband Engine (2) Cell Broadband Engine (3) AJProença, Computer Systems & Performance, MEI, UMinho, 2011/12 5 AJProença, Computer Systems & Performance, MEI, UMinho, 2011/12 6 Cell Broadband Engine (4) NVidia: Project Denver • Pick a successful SoC: Tegra 3 • Replace
    [Show full text]
  • ACORN RISC MACHINE Jitendra Marathe ARM Is a Reduced
    SRJIS / BIMONTHLY/JITENDRA MARATHE. (581-585) ACORN RISC MACHINE Jitendra Marathe ARM is a reduced instruction set computer (RISC) instruction set architecture (ISA) developed by ARM Holdings. It was named the Advanced RISC Machine and, before that, the Acorn RISC Machine. The ARM architecture is the most widely used 32-bit instruction set architecture in numbers produced. Originally conceived by Acorn Computers for use in its personal computers, the first ARM-based products were the co-processor modules for the BBC series of computers. Features and applications: In 2005 about 98% of the more than one billion mobile phones sold each year used at least one ARM processor. As of 2009 ARM processors accounted for approximately 90% of all embedded 32-bit RISC processors and were used extensively in consumer electronics, including personal digital assistants (PDAs), tablets, mobile phones, digital media and music players, hand-held game consoles, calculators and computer peripherals such as hard drives and routers. Licensees: The ARM architecture is licensable. Companies that are current or former ARM licensees include Alcatel-Lucent, Apple Inc., AppliedMicro, Atmel, Broadcom, Cirrus Logic, CSR_plc, Digital Equipment Corporation, Ember, Energy Micro, Freescale, Intel (through DEC), LG, Marvell Technology Group, Microsemi, Microsoft, NEC, Nintendo, Nuvoton, Nvidia, Sony, NXP (formerly Philips Semiconductor), Oki, ON Semiconductor, Psion, Qualcomm, Renesas, Samsung, Sharp, Silicon Labs, STMicroelectronics, Symbios Logic, Texas Instruments, VLSI Technology, Yamaha, Fuzhou Rockchip, and ZiiLABS. In addition to the abstract architecture, ARM offers several microprocessor core designs, including the ARM7, ARM9, ARM11, Cortex- A8, Cortex-A9, and Cortex-A15. Companies often license these designs from ARM to manufacture and integrate into their own system on a chip (SoC) with other components like RAM, GPUs, or radio basebands (for mobile phones).
    [Show full text]