Toucan-QM57
COM Express Computer-On-Module
Technical Manual
TME-TOUCANQM-R0V3.docx Revision 0.3 / June 11 © LIPPERT Embedded Computers GmbH Hans-Thoma-Str. 11 D-68163 Mannheim http://www.lippertembedded.com/ Technical Manual Toucan-QM57 LiPPERT Document: TME-TOUCANQM-R0V3.docx Revision 0.3 Copyright ©2011 LiPPERT Embedded Computers GmbH, All rights reserved
Trademarks MS-DOS, Windows, Windows 95, Windows 98, Windows NT and Windows XP are trademarks of Microsoft Corporation. PS/2 is a trademark of International Business Machines, Inc. Intel and Solid State Drive are trademarks of Intel Corporation. Geode is a trademark of Advanced Micro Devices. PC/104 is a registered trademark of PC/104 Consortium. All other trademarks appearing in this document are the property of their respective owners.
Disclaimer Contents and specifications within this technical manual are subject of change without notice. LiPPERT Embedded Computers GmbH provides no warranty with regard to this technical manual or any other information contained herein and hereby expressly disclaims any implied warranties of merchantability or fitness for any particular purpose with regard to any of the foregoing. LiPPERT Embedded Computers GmbH assumes no liability for any damages incurred directly or indirectly from any technical or typographical errors or omissions contained herein or for discrepancies between the product and the technical manual. In no event shall LiPPERT Embedded Computers GmbH be liable for any incidental, consequential, special, or exemplary damages, whether based on tort, contract or otherwise, arising out of or in connection with this user’s guide or any other information contained herein or the use thereof.
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Table of Contents
1 Overview 1
1.1 Introduction ...... 1 Features ...... 1 Block Diagram ...... 2
1.2 Ordering Information ...... 3 Toucan-QM57 Models ...... 3
1.3 Specifications ...... 4 Electrical Specifications ...... 4 Environmental Specifications ...... 4 Mean Time Between Failures ...... 4
1.4 Mechanical ...... 5
2 Getting Started 6
2.1 Connector Locations ...... 6 Top ...... 6 Bottom ...... 7
2.2 Jumper Locations ...... 8
2.3 LED indicators ...... 9
2.4 COM Express Specification ...... 10 Carrier Board connector and mounting positions ...... 10 Carrier Board Considerations ...... 10
2.5 Hardware Setup ...... 11
3 Module Description 12
3.1 Processor ...... 12
3.2 Platform Controller Hub (PCH) ...... 12
3.3 XR-DIMM™ Socket ...... 13
3.4 Graphics-Controller ...... 13 Analog Display Port (VGA) ...... 14 DisplayPort (DP) ...... 14 Serial Digital Video Out (SDVO) ...... 14 LVDS ...... 14
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3.5 PCI Express x16 (PEG) ...... 16 PEG Signal Description ...... 16
3.6 Gigabit Ethernet Controller ...... 17
3.7 USB 2.0 Ports ...... 17
3.8 Serial ATA Ports ...... 18
3.9 PATA ...... 18
3.10 Audio ...... 18
3.11 PCI ...... 18
3.12 PCI Express x1 ...... 19
3.13 Low Pin Count (LPC) ...... 19
3.14 Serial Peripheral Interface (SPI) ...... 19
3.15 System Management Bus (SMB) ...... 19
3.16 Power and System Management ...... 19 On Board Power Supply ...... 19 System State Indicators ...... 19 External Power Button ...... 20 Reset-In Signal ...... 20
3.17 External Battery ...... 20
3.18 Com Express Bus Interface ...... 21 Com Express Connector (X2) ...... 21
3.19 Watchdog ...... 24
3.20 LEMT function ...... 24 Board Specific LEMT functions...... 25 Voltages ...... 25 TS#-Events ...... 25 Exception Codes ...... 26
3.21 CPU Fan Connector (X6) ...... 26
4 Using the Module 27
4.1 BIOS ...... 27 Configuring the Phoenix BIOS ...... 27 Initialize BIOS at first startup ...... 27 Booting from alternative device ...... 27
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EFI Shell ...... 28 Jumper BIOS Defaults ...... 28 BIOS Screens ...... 29 Phoenix – SecureCore BIOS - Main 29 Phoenix – SecureCore BIOS – Main – System Information 29 Advanced 30 Advanced – Boot Configuration 30 Advanced – ACPI Configuration 31 Advanced – Processor Configuration 31 Advanced – Processor Configuration – Processor Power Management 32 Advanced – Peripheral Configuration 32 Advanced – HDD Configuration 33 Advanced – IMC Configuration 33 Advanced – IMC Configuration – NB Common Configuration 34 Advanced – IMC Configuration – NB Common Configuration – VT for Directed I/O 34 Advanced – IMC Configuration – NB Common Configuration – Video Configuration 35 Advanced – IMC Configuration – Arrandale Config 35 Advanced – IMC Configuration – Arrandale Config – PEG Configuration 36 Advanced – IMC Configuration – Arrandale Config – IGD Config 36 Advanced – IMC Configuration – Arrandale Config – IGD Config – Boot Type 37 Advanced – IMC Configuration – Arrandale Config – IGD Config – Panel Type 37 Advanced – South Bridge Config 38 Advanced – South Bridge Config – SB PCI Express Config 38 Advanced – South Bridge Config – SB PCI Express Config – PCI Express Root Port1 39 Advanced – Network Configuration 39 Advanced – SMBIOS Event Log 40 Advanced – ME Configuration 40 Advanced – Thermal Configuration 41 Advanced – Thermal Configuration – Processor Thermal Management Submenu 41 Advanced – Thermal Configuration – Intelligent Power Sharing 42 Advanced – Thermal Configuration – Platform Thermal Configuration 42 Security 43 Boot 43 Exit 44
4.2 Drivers ...... 44
5 Address Maps 45
5.1 Memory Address Map ...... 45
5.2 I/O Address Map ...... 46
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5.3 Interrupts ...... 48
5.4 DMA Channels...... 48
6 Troubleshooting 49
Contact Information A
Getting Help B
Additional Information C
Revision History D
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1 Overview
1.1 Introduction
The Toucan-QM57 offers a high performance COM Express board with the i7-620UE and i7-610E Processor Series from Intel® Core™. This processor is a next generation of 64-bit, multi-core mobile processor built on 32- nanometer process technology. Based on the low-power/high-performance Nehalem micro-architecture, the Arrandale processor is designed for a two-chip platform as opposed to the traditional three-chip platforms (processor, GMCH, and ICH). The two-chip platform consists of a processor and the Platform Controller Hub (PCH) and enables higher performance, lower cost and easier validation. In this case the PCH is Intel’s Ibex Peak- M (Mobile Intel® 5 Series Chipset). Two Ethernet GbE ports, six USB 2.0 host ports and two Power-USB 2.0 host ports handle the communication with external devices. Four SATA ports allows connection of hard disk or CD drives. System expansion can easily be realized over PCI/104-Express, PC/104-Plus, I²C bus and Mini-PCI connectors. The Toucan-QM57 runs DOS, Windows and Linux operating systems.
Features
CPU Interfaces · Intel® Arrandale™ · 4 x SATA · Cache Memory with: · PATA · 32 KB/32 KB level 1 I/D caches · 8 x USB 2.0 ports · 256 KB level 2 I/D cache · 6 x PCIe x1 · Up to 4 MB level 3 I/D cache · PCIe x16 · PCI Chipset · Ethernet GbE · HD Audio · Intel® 5 Series Chipset (formerly Ibex Peak-M) · SPI
· LPC Graphics & Display · SMB · DisplayPort · 18/24 Bit LVDS Lippert Enhanced Management Technology (LEMT) · VGA · SDVO
Main Memory Memory extension · soldered 2GB DDR3 RAM with ECC, 1066 MHz · XR-DIMM™ socket for ECC memory modules
Other configurations are possible. Please contact your local LiPPERT representative to discuss requirements.
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Block Diagram
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1.2 Ordering Information
Toucan-QM57 Models
Order number Description 709-0015-10 Toucan-QM57 with Intel i7-620UE, 1.06 GHz, low power consumption, 2 GB ECC DDR3 RAM onboard, 8x USB2.0, HD Audio, 4x SATA, PATA, SMC, DisplayPort, LVDS Interface, VGA, SDVO, Ethernet GbE, PCI, 6x PCIe x1, PCIe x16, LPC, SMB, SPI. Operating temp. range: -0°C…+60°C 809-0015-10 Toucan -QM57 with Intel i7-620UE, 1.06 GHz, low power consumption, 2 GB ECC DDR3 RAM onboard, 8x USB2.0, HD Audio, 4x SATA, PATA, SMC, DisplayPort, LVDS Interface, VGA, SDVO, Ethernet GbE, PCI, 6x PCIe x1, PCIe x16, LPC, SMB, SPI. Operating temp. range: -20°C…+60°C 909-00015-10 Toucan -QM57 with Intel i7-620UE, 1.06 GHz, low power consumption, 2 GB ECC DDR3 RAM onboard, 8x USB2.0, HD Audio, 4x SATA, PATA, SMC, DisplayPort, LVDS Interface, VGA, SDVO, Ethernet GbE, PCI, 6x PCIe x1, PCIe x16, LPC, SMB, SPI. Operating temp. range: -40°C…+85°C 709-0014-10 Toucan -QM57 with Intel i7-610E, 2.53 GHz, low power consumption, 2 GB ECC DDR3 RAM onboard, 8x USB2.0, HD Audio, 4x SATA, PATA, SMC, DisplayPort, LVDS Interface, VGA, SDVO, Ethernet GbE, PCI, 6x PCIe x1, PCIe x16, LPC, SMB, SPI. Operating temp. range: 0°C…+60°C 809-0014-10 Toucan -QM57 with Intel i7-610E, 2.53 GHz, low power consumption, 2 GB ECC DDR3 RAM onboard, 8x USB2.0, HD Audio, 4x SATA, PATA, SMC, DisplayPort, LVDS Interface, VGA, SDVO, Ethernet GbE, PCI, 6x PCIe x1, PCIe x16, LPC, SMB, SPI. Operating temp. range: -20°C…+60°C 909-0014-10 Toucan -QM57 with Intel i7-610E, 2.53 GHz, low power consumption, 2 GB ECC DDR3 RAM onboard, 8x USB2.0, HD Audio, 4x SATA, PATA, SMC, DisplayPort, LVDS Interface, VGA, SDVO, Ethernet GbE, PCI, 6x PCIe x1, PCIe x16, LPC, SMB, SPI. Operating temp. range: -40°C…+85°C
Note: Custom combinations of processor and memory are possible. Minimum order quantities are required. Contact LiPPERT’s Sales Team at [email protected]
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1.3 Specifications
Electrical Specifications Supply voltage 12VDC nominal (5VDC – 12VDC) Rise time < 10 ms Supply voltage tolerance ± 5% * Inrush current +12V: t.b.d. A Supply current peak** typical idle S3 (STR) +12V 5.0 A 2.0 A 0.72 A 0.12 A
* With that tolerance it is not mentioned that all plugged devices are running with. ** That rate of current is possible when only monitor, mouse and keyboard are plugged. If there are connected additional peripheral devises the current rises up.
Environmental Specifications Operating: Temperature range 0 … 60 °C (standard version) -20 … 60 °C (industrial version) -40 … 85 °C (extended version) Temperature change max. 10K / 30 minutes Humidity (relative) 10 … 90 % (non-condensing) Pressure 450 … 1100 hPa
Non-Operating/Storage/Transport: Temperature range -40 … 85 °C Temperature change max. 10K / 30 minutes Humidity (relative) 5 … 95 % (non-condensing) Pressure 450 … 1100 hPa
Mean Time Between Failures MTBF at 25°C t.b.d. hours
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1.4 Mechanical
Dimensions (L x W) 95 mm x 125 mm
Height 18 mm (5 mm standoff) or 21 mm (8 mm standoff) measured from topside of the carrier PCB (with heatspreader). See Figure 1. Weight 97,2 g (without XR-DIMM) 115 g (with XR-DIMM)
Mounting 6 mounting holes for PCB
Figure 1: COM Express stack.
Note It is strongly recommend using plastic spacers instead of metal spacers to mount the board. With metal spacers, there is a possible danger to create a short circuit with the components located around the mounting holes. This can damage the board!
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2 Getting Started
2.1 Connector Locations
Top
SMC-Service Connector X1
CPU-Fan X6
ISP Connector for SF-100 X4
XR-DIMM Connector X5
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Bottom
COM Express Connector X2
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Jumper X5
2.2 Jumper Locations
Jumper Board Settings X3
This four pin Connector X3 has two jumper options: Use a 2mm jumper between 1-2 select the BIOS defaults during startup. Use a 2mm jumper between 3-4 forces the PEG signals at the multiplexed PEG signals. If the jumper is not set, then the SDVO & DisplayPort signals are selected at the multiplexed PEG signals.
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2.3 LED indicators
To facilitate problem solving, the Toucan-QM57 provides LED indicators for the following conditions:
LED Name Function 1 SMC SMC Activity (Status and Error Codes) 2 POW Power Mode 3 MP Main Power Supply 4 WD Watchdog activated 5 SATA SATA Activity
5
1
2
3
4
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2.4 COM Express Specification
The Toucan-QM57 complies with the COM Express Specification 2.0, specified by PICMG. See http://www.picmg.org/ for details.
Carrier Board connector and mounting positions
Figure 2: Carrier Board Form Factors (all dimensions in millimeters).
Carrier Board Considerations The COM Express specification defines two types of connectors for the carrier board, one with a height of 5 mm, the other with a height of 8 mm. See the specification for the connector definition and recommended vendors. LiPPERT recommends using the 8 mm type, since it gives more freedom for components on top of the carrier board and allows for greater distance between the two PCB's, which is important for applications requiring higher vibration tolerance. When using the 8 mm connectors, the maximum component height on the carrier board (below the Toucan-QM57) can be up to 4 mm. Figure 3 shows the details.
Figure 3: Maximum component height.
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2.5 Hardware Setup
Installing the Toucan-QM57 is very straightforward. First, unpack the board observing the usual electrostatic discharge (ESD) precautions.
Caution Before you touch the board, make sure that you have discharged yourself and your gear towards a grounded terminal. Damages due to ESD are usually not immediately visible and will only show up later as failures in the field.
Mount the cooling device.
Caution Never operate the Toucan-QM57 without suitable cooling devices. Failing this can destroy the module.
Caution Never connect or disconnect peripherals like hard drives while the board's power supply is connected and switched on!
Plug the Toucan-QM57 into your baseboard. Connect all necessary peripherals, such as keyboard, mouse, monitor, etc. to the system. If you plan to use additional other peripherals, now is the time to connect them, too. Switch the power on.
Note The ampere values in chapter 1.3 are the minimum you should have for the standard peripherals mentioned. If you want to use more and/or others, please plan your power budget first! The system will not work if there is not enough supply current for all your devices.
The display shows the BIOS messages. If you want to change the standard BIOS settings, press the
Note Not all USB devices are suitable to boot the Toucan-QM57. If there are problems, please try to use another device from another manufacturer.
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3 Module Description
3.1 Processor
Intel Core i7-620UE and i7-610E Processor Series is the next generation of 64-bit, multi-core mobile processor built on a 32- nanometer process technology. Throughout this document, Intel® CoreTM i7-620UE and i7-610E Processor Series may be referred to as simply the processor. The processor is designed for a two-chip platform as opposed to the traditional three-chip platforms (processor, GMCH, and ICH). The two-chip platform consists of a processor and the Platform Controller Hub (PCH) and enables higher performance, lower cost, easier validation, and improved x-y footprint. The PCH may also be referred to as Mobile Intel® 5 Series Chipset (formerly Ibex Peak-M). Intel® CoreTM i7-620UE and i7-610E Processor Series is designed for the Intel® CoreTM i7 processor based low-power platform and is offered in a BGA1288 package. Included in this family of processors is an integrated graphics and memory controller die on the same package as the processor core die. This two-chip solution of a processor core die with an integrated graphics and memory controller die is known as a multi-chip package (MCP) processor. Processor feature details: • Two execution cores • A 32-KB instruction and 32-KB data first-level cache (L1) for each core • A 256-KB shared instruction/data second-level cache (L2) for each core • Up to 4-MB shared instruction/data third-level cache (L3), shared among all cores Interfaces: • System Memory Support • dual-channel memory organization mode • Memory DDR3 data transfer rate of 1066 MT/s • 1-Gb, and 2-Gb DDR3 DRAM technologies for x16 devices • PCI Express* • The CPU PCI Express* port(s) are fully compliant to the PCI Express Base Spec., Rev. 2.0 at 2.5GT/s. • The processor supports: - One 16-lane PCI Express port for graphics or I/O. - Two 8-lane PCI Express ports for graphics or I/O. • PCI Express Port 0 is mapped to PCI Device 1. • PCI Express Port 1 is mapped to PCI Device 6.
For further information, please refer to the data book of the Intel® CoreTM i7-620UE and i7-610E Processor Series.
3.2 Platform Controller Hub (PCH)
The PCH provides extensive I/O support. Functions and capabilities include: • PCI Express* Base Specification, Revision 2.0 support for seven ports • PCI Local Bus Specification, Revision 2.3 support for 33MHz PCI operations (supports up to 4 Req/Gnt pairs) • ACPI Power Management Logic Support, Revision 3.0b • Enhanced DMA controller, interrupt controller, and timer functions • Integrated Serial ATA host controllers with independent DMA operation on four ports • USB host interface with support for thirteen USB ports; two EHCI high-speed USB 2.0 Host controllers and 2 rate matching hubs • Integrated 10/100/1000 Gigabit Ethernet MAC with System Defense • System Management Bus (SMBus) Specification, Version 2.0 with additional support for I2C devices • Supports Intel® High Definition Audio • Supports Intel® Rapid Storage Technology • Supports Intel® Active Management Technology • Supports Intel® Virtualization Technology for Directed I/O • Supports Intel® Trusted Execution Technology • Supports buffered mode generating extra clocks from a clock chip • Analog and Digital Display ports - VGA - DisplayPort 1.1 - SDVO - LVDS • Low Pin Count (LPC) interface
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3.3 XR-DIMM™ Socket
The Toucan-QM57 has a XR-DIMM™ socket to extend the main memory with an ECC memory module according to the XR-DIMM™ standard by SFF-SIG. The memory module can be securely mounted with two metric screws M2x4.
XR-DIMM™ is a new multi-sourced rugged memory module standard for the embedded systems market. XR- DIMM™ was originally announced as RS-DIMM™, but the name has been changed to emphasize the eXtreme Rugged aspects. The specification defines both unbuffered and registered versions which are analogous to their SO-DIMM counterparts. The module is narrower than the SO-DIMM module, allowing it to fit better on narrow processor boards and modules. Upgrading memory capacity is as simple as swapping memory modules. Enhanced ruggedness is obtained through the use of a high-performance, 240-pin socket connector system and the use of standoffs with screw attachment firmly holding the CPU and memory module together.
XR-DIMM™ modules are available from different memory modules vendors with different capacities. As the memory module is mounted underneath the heat spreader on the Top-Side of the Toucan-QM57, the needed memory module should be ordered together with the board. Please ask our sales department regarding pricing and availability.
3.4 Graphics-Controller
The integrated graphics controller contains a refresh of the fifth generation graphics core • Intel® Dynamic Video Memory Technology (Intel® DVMT) support • Intel® Graphics Performance Modulation Technology (Intel® GPMT) • Intel® Smart 2D Display Technology (Intel® S2DDT) • Intel® Clear Video Technology — MPEG2 Hardware Acceleration — WMV9/VC1 Hardware Acceleration — AVC Hardware Acceleration — ProcAmp — Advanced Pixel Adaptive De-interlacing — Sharpness Enhancement — De-noise Filter — High Quality Scaling — Film Mode Detection (3:2 pull-down) and Correction — Intel® TV Wizard
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Analog Display Port (VGA) The analog display port provides a RGB signal output along with a HSYNC and VSYNC signal. There is an associated DDC signal pair that is implemented using GPIO pins dedicated to the analog port. The intended target device is for a CRT based monitor with a VGA connector. Display devices such as LCD panels with analog inputs may work satisfactory but no functionality added to the signals to enhance that capability. [Location at the COM Express BUS: B89-96]
DisplayPort (DP) DisplayPort is a digital communication interface that uses differential signaling to achieve a high bandwidth bus interface designed to support connections between PCs and monitors, projectors, and TV displays. DisplayPort is also suitable for display connections between consumer electronics devices such as high definition optical disc players, set top boxes, and TV displays. A DisplayPort consists of a Main Link, Auxiliary channel, and a Hot Plug Detect signal. The Main Link is a uni- directional, high-bandwidth, and low latency channel used for transport of isochronous data streams such as uncompressed video and audio. The Auxiliary Channel (AUX CH) is a half-duplex bi-directional channel used for link management and device control. The Hot Plug Detect (HPD) signal serves as an interrupt request for the sink device. [Location at the COM Express BUS: C71-74 & D65-D75]
Serial Digital Video Out (SDVO) Serial Digital Video Out supports SDVO-LVDS only on the PCH (digital Port B). Though the SDVO electrical interface is based on the PCI Express interface, the protocol and timings are completely unique. The PCH uses an external SDVO device to translate from SDVO protocol and timings to the desired display format and timings. [Location at the COM Express BUS: C52-66, C73 & D52-D62, D73]
Figure 4: SDVO Conceptual Block Diagram.
LVDS The LVDS interface for flat panel is compatible with the ANSI/TIA/EIA-644 specification. There are two LVDS transmitter channels (Channel A and Channel B) in the LVDS interface. Channel A and Channel B consist of 4-data pairs and a clock pair each. Each channel supports transmit clock frequency ranges from 25 MHz to 112 MHz, which provides a throughput of up to 784 Mbps on each data output and up to 112 MP/s on the input. When using both channels, each carry a portion of the data; thus, doubling the throughput to a maximum theoretical pixel rate of 224 MP/s. The Toucan-QM57 supports 3,3V and 5V LVDS displays with 18/24bit interfaces and unconventional signal configuration.
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The display type and resolution can be selected in BIOS setup: Advanced à IMC Configuration à Arrandale Configuration à IGD Configuration à Panel Type. The display options of LVDS are shown in the table:
Setting Possible Values Flat Panel Type LVDS Resolution 640x480, 800x600, 1024x768, 1280x1024, 1400x1050, 1600x1200, 1200x768, 1600x1050, 1920x1200 Data Bus Type 18/24 Bits, 2ppc Refresh Rate 60 70, 72, 75, 85, 90, 100 Hz HSYNC Polarity High, Low VSYNC Polarity High, Low LP Active Period Active Only à only active during SYNC Free Running à always active SHFCLK Active Period Active Only à only active during SYNC Free Running à always active
[Location at the COM Express BUS: A71-84 & B71-83]
LVDS Color Mapping
1 2 3 4 5 6 7
CLKA 1 1 0 0 0 1 1
A0 G2 R7 R6 R5 R4 R3 R2 A1 B3 B2 G7 G6 G5 G4 G3 A2 DE VS HS B7 B6 B5 B4 A3 0/B1 B1 B0 G1 G0 R1 R0 CLKB 1 1 0 0 0 1 1
B0 G2 R7 R6 R5 R4 R3 R2 B1 B3 B2 G7 G6 G5 G4 G3 B2 DE VS HS B7 B6 B5 B4 B3 0/B1 B1 B0 G1 G0 R1 R0
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3.5 PCI Express x16 (PEG)
The processor has one PCI Express controller that can support one external x16 PCI Express Graphics (PEG) Device or two external x8 PCI Express Graphics Devices. The primary PCI Express Graphics port is referred to as PEG 0 and the secondary PCI Express Graphics port is referred to as PEG 1. The Processor PCI Express* ports are fully compliant to the PCI Express Base Specification Revision 2.0. - One 16-lane PCI Express* port intended for graphics attach. - Two 8-lane PCI Express* ports intended for graphics attach. PCI Express Port 0 is mapped to PCI Device 1 (PEG 0). PCI Express Port 1 is mapped to PCI Device 6 (PEG 1). [Location at the COM Express BUS: C/D52-102]
PEG Signal Description The first eight lanes at the PEG Bus are multiplexed with the signals PICe x16 (lanes 0 to 7), SDVO and DisplayPort. The following two tables describes the signal configuration at the COM Express Bus (PEG_RX0± to PEG_RX7± and PEG_TX0± to PEG_TX7±) when the jumper “Board Settings” pin 3-4 is set or not.
Signal Pin Multiplexed signals Jumper set (PEG) Jumper not set (SDVO & DP) PEG_RX0+ C52 PEG_RX0+ SDVO_TVCLKIN- PEG_RX0- C53 PEG_RX0- SDVO_TVCLKIN- PEG_RX1+ C55 PEG_RX1+ SDVO_INT+ PEG_RX1- C56 PEG_RX1- SDVO_INT- PEG_RX2+ C58 PEG_RX2+ SDVO_STALL+ PEG_RX2- C59 PEG_RX2- SDVO_STALL- PEG_RX3+ C61 PEG_RX3+ DPB_HPD PEG_RX3- C62 PEG_RX3- NC PEG_RX4+ C65 PEG_RX4+ DPB_AUX+ PEG_RX4- C66 PEG_RX4- DPB_AUX- PEG_RX5+ C68 PEG_RX5+ NC PEG_RX5- C69 PEG_RX5- NC PEG_RX6+ C71 PEG_RX6+ DPC_AUX+ PEG_RX6- C72 PEG_RX6- DPC_AUX- PEG_RX7+ C74 PEG_RX7+ DPC_HPD PEG_RX7- C75 PEG_RX7- NC
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Signal Pin Multiplexed signals Jumper set (PEG) Jumper not set (SDVO & DP) PEG_TX0+ D52 PEG_TX0+ SDVO_DPB_LANE0+ PEG_TX0- D53 PEG_TX0- SDVO_DPB_LANE0- PEG_TX1+ D55 PEG_TX1+ SDVO_DPB_LANE1+ PEG_TX1- D56 PEG_TX1- SDVO_DPB_LANE1- PEG_TX2+ D58 PEG_TX2+ SDVO_DPB_LANE2+ PEG_TX2- D59 PEG_TX2- SDVO_DPB_LANE2- PEG_TX3+ D61 PEG_TX3+ SDVO_DPB_CLK+ PEG_TX3- D62 PEG_TX3- SDVO_DPB_CLK- PEG_TX4+ D65 PEG_TX4+ DPC_LANE0+ PEG_TX4- D66 PEG_TX4- DPC_LANE0- PEG_TX5+ D68 PEG_TX5+ DPC_LANE1+ PEG_TX5- D69 PEG_TX5- DPC_LANE1- PEG_TX6+ D71 PEG_TX6+ DPC_LANE2+ PEG_TX6- D72 PEG_TX6- DPC_LANE2- PEG_TX7+ D74 PEG_TX7+ DPC_LANE3+ PEG_TX7- D75 PEG_TX7- DPC_LANE3-
3.6 Gigabit Ethernet Controller
The PCH chipset integrates a Gigabit Ethernet (GbE) controller. The integrated GbE controller is compatible with the Intel® 82577 (Hanksville) Platform LAN Connect device.
Intel® 82577 Gigabit Ethernet PHY The 82577 is a single port Gigabit Ethernet Physical Layer Transceiver (PHY). It connects to the Ibex Peak-M chipset’s integrated Media Access Controller (MAC) through a dedicated interconnect. The 82577 supports operation at 1000/100/10 Mb/s data rates. The PHY circuitry provides a standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE-TX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab). The 82577 interfaces with its MAC through two interfaces: PCIe-based and SMBus. The PCIe (main) interface is used for all link speeds when the system is in an active state (S0) while the SMBus is used only when the system is in a low power state (Sx). In SMBus mode, the link speed is reduced to 10 Mb/s (dependent on low power options). The PCIe interface incorporates two aspects: a PCIe SerDes (electrically) and a custom logic protocol. [Location at the COM Express BUS: A2-14 & B2]
3.7 USB 2.0 Ports
The Ibex Peak contains two Enhanced Host Controller Interface (EHCI) host controllers which support up to fourteen USB 2.0 high-speed root ports. USB 2.0 allows data transfers up to 480Mb/s. USB 2.0 based Debug Port is also implemented in the Ibex Peak. Eight USB 2.0 host ports are provided with the Toucan-QM57. [Location at the COM Express BUS: A/B36-46]
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3.8 Serial ATA Ports
The Ibex Peak has two integrated SATA host controllers that support independent DMA operation on up to six ports and supports data transfer rates of up to 3.0Gb/s (300 MB/s). The SATA controller contains two modes of operation – a legacy mode using I/O space, and an AHCI mode using memory space. Software that uses legacy mode will not have AHCI capabilities. The Ibex Peak supports the Serial ATA Specification, Revision 1.0a. The Ibex Peak also supports several optional sections of the Serial ATA II: Extensions to Serial ATA 1.0 Specification, Revision 1.0 (AHCI support is required for some elements). The Ibex Peak provides hardware support for Advanced Host Controller Interface (AHCI), a new programming interface for SATA host controllers. Platforms supporting AHCI may take advantage of performance features such as no master/slave designation for SATA devices—each device is treated as a master—and hardware-assisted native command queuing. AHCI also provides usability enhancements such as Hot-Plug. AHCI requires appropriate software support (e.g., an AHCI driver) and for some features, hardware support in the SATA device or additional platform hardware. There are four SATA ports available at the COM Express Bus. [Location at the COM Express BUS: A16-26]
3.9 PATA
The PATA signals are generated by a PCI Express to PATA Host Controller (JMB368). This single chip is a 1 lane PCI Express to 1 port PATA Host Controller. This PATA interface supports: • Native Mode operation • up to 2 storage devices connection • PIO Mode 0, 1, 2, 3, 4 • Multiword DMA Mode 0, 1, 2 • Ultra DMA 33/66/100/133 • ATA/ATAPI command • 48-bit logical block addressing • automatically interface timing setting [Location at the COM Express BUS: C2-14 & D2-18]
3.10 Audio
The Ibex Peak’s High Definition Audio (HDA) controller communicates with the external codecs over the Intel High Definition Audio serial link. The controller consists of a set of DMA engines that are used to move samples of digitally encoded data between system memory and an external codec(s). The Ibex Peak implements four output DMA engines and 4 input DMA engines. The output DMA engines move digital data from system memory to a D-A converter in a codec. Ibex Peak implements a single Serial Data Output signal (HDA_SDOUT) that is connected to all external codecs. The input DMA engines move digital data from the A-D converter in the codec to system memory. The Ibex Peak implements four Serial Digital Input signals (HDA_SDI[3:0]) supporting up to four codecs. [Location at the COM Express BUS: A29, A30, A32, A33, B28, B29, B30 & B32]
3.11 PCI
The PCH PCI interface supports PCI Local Bus Specification, Revision 2.3, at 33 MHz. The PCH integrates a PCI arbiter that supports up to four external PCI bus masters in addition to the internal PCH requests. [Location at the COM Express BUS: C15-50 & D19-50]
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3.12 PCI Express x1
There are eight root ports available in the PCH. The root ports are compliant to the PCI Express 2.0 specification running at 2.5 GT/s. The ports all reside in device 28, and take function 0 – 7. PCI Express Root Ports 1-4, which are connected to the COM Express Bus, can independently be configured as four x1, two x2, one x2 and 2 x1, or one x4 port widths. The port configuration is set by soft straps in the Flash Descriptor. [Location at the COM Express BUS: A/B52-69]
3.13 Low Pin Count (LPC)
The PCH implements an LPC interface as described in the Low Pin Count Interface Specification, Revision 1.1. [Location at the COM Express BUS: B3-10]
3.14 Serial Peripheral Interface (SPI)
The Serial Peripheral Interface (SPI) is a 4-pin interface. Consists of clock (CLK), master data out (Master Out Slave In (MOSI)), master data in (Master In Slave Out (MISO)) and an active low chip select (SPI_CS[1:0]#). The PCH supports up to two SPI flash devices using two separate Chip Select pins. Each SPI flash device can be up to 16 MBytes. The PCH SPI interface supports 20 MHz, 33MHz, and 50 MHz SPI devices. Communication on the SPI bus is done with a Master – Slave protocol. The Slave is connected to the PCH and is implemented as a tri-state bus. The Toucan-QM57 have included two SPI flash devices, but only used one device. The customer have the possibility to work with it’s own SPI flash device at the Carrier Board via the COM Express Bus. [Location at the COM Express BUS: A91, A92, A94, A95 & B97]
3.15 System Management Bus (SMB)
The PCH provides an System Management Bus (SMB) 2.0 host controller as well as an SMB Slave Interface. The host controller provides a mechanism for the processor to initiate communications with SMB peripherals (slaves). The PCH is also capable of operating in a mode in which it can communicate with I²C compatible devices. The Slave Interface allows an external master to read from or write to the PCH. Write cycles can be used to cause certain events or pass messages, and the read cycles can be used to determine the state of various status bits. The PCH’s internal host controller cannot access the PCH’s internal Slave Interface. [Location at the COM Express BUS: for SMB B13-15] [Location at the COM Express BUS: for I²C B33 & B34]
3.16 Power and System Management
On Board Power Supply The on board power supply generates all necessary voltages from the single supply voltage of 12 volts DC. But it’s also possible to use +5V Standby from external and not the on board generated +5V Standby voltage. [Location at the COM Express BUS: for VCC_12V A/B/C/D104-109] [Location at the COM Express BUS: for VCC_5V_SBY B84-87]
System State Indicators The signals SUS_S3#, SUS_S4# and SUS_S5# defines the signaling to indicate that the Module has entered the ACPI power-saving mode S3 (Suspend to RAM or STR), S4 (Suspend to Disk or STD) or S5 (Soft Off). The Signal SUS_STAT# indicates imminent suspend operation.
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[Location at the COM Express BUS: A15, A18, A24 & B18]
External Power Button The board has a power button support to initiate transition from S4/S5 to S0. [Location at the COM Express BUS: B12]
Reset-In Signal The Toucan-QM57 has a reset button support to restart the system. [Location at the COM Express BUS: B49]
3.17 External Battery
The board supports a RTC that provides a battery. A typical battery current in suspend mode is for the latest CPU defined as approx. 5 µA. In S0 mode the RTC is powered by the power supply. [Location at the COM Express BUS: A47]
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3.18 Com Express Bus Interface
Com Express Connector (X2) COM Express Type 2 Rev.2.0, design compatible to latest PICMG design guide Connector Type : Tyco PN : 3-1827231-6
Row A Row B Row C Row D
A1 GND B1 GND C1 GND D1 GND A2 GBE0_MDI3- B2 GBE0_ACT# C2 IDE_D7 D2 IDE_D5 A3 GBE0_MDI3+ B3 LPC_FRAME# C3 IDE_D6 D3 IDE_D10 A4 GBE0_LINK100# B4 LPC_AD0 C4 IDE_D3 D4 IDE_D11 A5 GBE0_LINK1000# B5 LPC_AD1 C5 IDE_D15 D5 IDE_D12 A6 GBE0_MDI2- B6 LPC_AD2 C6 IDE_D8 D6 IDE_D4 A7 GBE0_MDI2+ B7 LPC_AD3 C7 IDE_D9 D7 IDE_D0 A8 GBE0_LINK# B8 LPC_DRQ0# C8 IDE_D2 D8 IDE_REQ A9 GBE0_MDI1- B9 LPC_DRQ1# C9 IDE_D13 D9 IDE_IOW# A10 GBE0_MDI1+ B10 LPC_CLK C10 IDE_D1 D10 IDE_ACK# A11 GND B11 GND C11 GND D11 GND A12 GBE0_MDI0- B12 PWRBTN# C12 IDE_D14 D12 IDE_IRQ A13 GBE0_MDI0+ B13 SMB_CK C13 IDE_IORDY D13 IDE_A0 A14 GBE0_CTREF B14 SMB_DAT C14 IDE_IOR# D14 IDE_A1 A15 SUS_S3# B15 SMB_ALERT# C15 PCI_PME# D15 IDE_A2 A16 SATA0_TX+ B16 SATA1_TX+ C16 PCI_GNT2# D16 IDE_CS1# A17 SATA0_TX- B17 SATA1_TX- C17 PCI_REQ2# D17 IDE_CS3# A18 SUS_S4# B18 SUS_STAT# C18 PCI_GNT1# D18 IDE_RESET# A19 SATA0_RX+ B19 SATA1_RX+ C19 PCI_REQ1# D19 PCI_GNT3# A20 SATA0_RX- B20 SATA1_RX- C20 PCI_GNT0# D20 PCI_REQ3# A21 GND B21 GND C21 GND D21 GND A22 SATA2_TX+ B22 SATA3_TX+ C22 PCI_REQ0# D22 PCI_AD1 A23 SATA2_TX- B23 SATA3_TX- C23 PCI_RE SET# D23 PCI_AD3 A24 SUS_S5# B24 PWR_OK C24 PCI_AD0 D24 PCI_AD5 A25 SATA2_RX+ B25 SATA3_RX+ C25 PCI_AD2 D25 PCI_AD7 A26 SATA2_RX- B26 SATA3_RX- C26 PCI_AD4 D26 PCI_C/BE0# A27 BATLOW# B27 WDT C27 PCI_AD6 D27 PCI_AD9 A28 SATA_ACT# B28 AC/HDA_SDIN2 C28 PCI_AD8 D28 PCI_AD11 A29 AC/HDA_SYNC B29 AC/HDA_SDIN1 C29 PCI_AD10 D29 PCI_AD13 A30 AC/HDA_RST# B30 AC/HDA_SDIN0 C30 PCI_AD12 D30 PCI_AD15 A31 GND B31 GND C31 GND D31 GND A32 AC/HDA_BITCLK B32 SPKR C32 PCI_AD14 D32 PCI_PAR A33 AC/HDA_SDOUT B33 I2C_CK C33 PCI_C/BE1# D33 PCI_SERR# A34 BIOS_DIS0# B34 I2C_DAT C34 PCI_PERR# D34 PCI_STOP# A35 THRMTRIP# B35 THRM# C35 PCI_LOCK# D35 PCI_TRDY# A36 USB6- B36 USB7- C36 PCI_DEVSEL# D36 PCI_FRAME# A37 USB6+ B37 USB7+ C37 PCI_IRDY# D37 PCI_AD16 A38 USB_6_7_OC# B38 USB_4_5_OC# C38 PCI_C/BE2# D38 PCI_AD18
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Row A Row B Row C Row D
A39 USB4- B39 USB5- C39 PCI_AD17 D39 PCI_AD20 A40 USB4+ B40 USB5+ C40 PCI_AD19 D40 PCI_AD22 A41 GND B41 GND C41 GND D41 GND A42 USB2- B42 USB3- C42 PCI_AD21 D42 PCI_AD24 A43 USB2+ B43 USB3+ C43 PCI_AD23 D43 PCI_AD26 A44 USB_2_3_OC# B44 USB_0_1_OC# C44 PCI_C/BE3# D44 PCI_AD28 A45 USB0- B45 USB1- C45 PCI_AD25 D45 PCI_AD30 A46 USB0+ B46 USB1+ C46 PCI_AD27 D46 PCI_IRQC# A47 VCC_RTC B47 EXCD1_PERST# C47 PCI_AD29 D47 PCI_IRQD# A48 EXCD0_PERST# B48 EXCD1_CPPE# C48 PCI_AD31 D48 PCI_CLKRUN# A49 EXCD0_CPPE# B49 SYS_RESET# C49 PCI_IRQA# D49 PCI_M66EN (NC) A50 LPC_SERIRQ B50 CB_RESET# C50 PCI_IRQB# D50 PCI_CLK A51 GND B51 GND C51 GND D51 GND A52 PCIE_TX5+ B52 PCIE_RX5+ C52 PEG_RX0+ * D52 PEG_TX0+ * A53 PCIE_TX5- B53 PCIE_RX5- C53 PEG_RX0- * D53 PEG_TX0- * A54 GPI0 B54 GPO1 C54 TYPE0# (NC) D54 PEG_LANE_RV# A55 PCIE_TX4+ B55 PCIE_RX4+ C55 PEG_RX1+ * D55 PEG_TX1+ * A56 PCIE_TX4- B56 PCIE_RX4- C56 PEG_RX1- * D56 PEG_TX1- * A57 GND B57 GPO2 C57 TYPE1# (NC) D57 TYPE2# A58 PCIE_TX3+ B58 PCIE_RX3+ C58 PEG_RX2+ * D58 PEG_TX2+ * A59 PCIE_TX3- B59 PCIE_RX3- C59 PEG_RX2- * D59 PEG_TX2- * A60 GND B60 GND C60 GND D60 GND A61 PCIE_TX2+ B61 PCIE_RX2+ C61 PEG_RX3+ * D61 PEG_TX3+ * A62 PCIE_TX2- B62 PCIE_RX2- C62 PEG_RX3- * D62 PEG_TX3- * A63 GPI1 B63 GPO3 C63 Reserved (NC) D63 DPC_CTRLCLK A64 PCIE_TX1+ B64 PCIE_RX1+ C64 Reserved (NC) D64 DPC_CTRLDATA A65 PCIE_TX1- B65 PCIE_RX1- C65 PEG_RX4+ * D65 PEG_TX4+ * A66 GND B66 WAKE0# C66 PEG_RX4- * D66 PEG_TX4- * A67 GPI2 B67 WAKE1# C67 Reserved (NC) D67 GND A68 PCIE_TX0+ B68 PCIE_RX0+ C68 PEG_RX5+ * D68 PEG_TX5+ * A69 PCIE_TX0- B69 PCIE_RX0- C69 PEG_RX5- * D69 PEG_TX5- * A70 GND B70 GND C70 GND D70 GND A71 LVDS_A0+ B71 LVDS_B0+ C71 PEG_RX6+ * D71 PEG_TX6+ * A72 LVDS_A0- B72 LVDS_B0- C72 PEG_RX6- * D72 PEG_TX6- * A73 LVDS_A1+ B73 LVDS_B1+ C73 SDVO_DATA D73 SDVO_CLK A74 LVDS_A1- B74 LVDS_B1- C74 PEG_RX7+ * D74 PEG_TX7+ * A75 LVDS_A2+ B75 LVDS_B2+ C75 PEG_RX7- * D75 PEG_TX7- * A76 LVDS_A2- B76 LVDS_B2- C76 GND D76 GND A77 LVDS_VDD_EN B77 LVDS_B3+ C77 Reserved (NC) D77 IDE_CBLID# A78 LVDS_A3+ B78 LVDS_B3- C78 PEG_RX8+ D78 PEG_TX8+ A79 LVDS_A3- B79 LVDS_BKLT_EN C79 PEG_RX8- D79 PEG_TX8- A80 GND B80 GND C80 GND D80 GND A81 LVDS_A_CK+ B81 LVDS_B_CK+ C81 PEG_RX9+ D81 PEG_TX9+
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Row A Row B Row C Row D
A82 LVDS_A_CK- B82 LVDS_B_CK- C82 PEG_RX9- D82 PEG_TX9- A83 LVDS_I2C_CK B83 LVDS_BKLT_CTRL C83 Reserved (NC) D83 Reserved (NC) A84 LVDS_I2C_DAT B84 VCC_5V_SBY C84 GND D84 GND A85 GPI3 B85 VCC_5V_SBY C85 PEG_RX10+ D85 PEG_TX10+ A86 KBD_RST# B86 VCC_5V_SBY C86 PEG_RX10- D86 PEG_TX10- A87 KBD_A20GATE B87 VCC_5V_SBY C87 GND D87 GND A88 PCI0_CK_REF+ B88 BIOS_DIS1# C88 PEG_RX11+ D88 PEG_TX11+ A89 PCI0_CK_REF- B89 VGA_RED C89 PEG_RX11- D89 PEG_TX11- A90 GND B90 GND C90 GND D90 GND A91 SPI_POWER B91 VGA_GRN C91 PEG_RX12+ D91 PEG_TX12+ A92 SPI_MISO B92 VGA_BLU C92 PEG_RX12- D92 PEG_TX12- A93 GPO0 B93 VGA_HSYNC C93 Reserved D93 GND A94 SPI_CLK B94 VGA_VSYNC C94 PEG_RX13+ D94 PEG_TX13+ A95 SPI_MOSI B95 VGA_I2C_CK C95 PEG_RX13- D95 PEG_TX13- A96 GND B96 VGA_I2C_DAT C96 GND D96 GND A97 TYPE10# (NC) B97 SPI_CS# C97 Reserved (NC) D97 PEG_ENABLE# A98 Reserved (NC) B98 Reserved (NC) C98 PEG_RX14+ D98 PEG_TX14+ A99 Reserved (NC) B99 Reserved (NC) C99 PEG_RX14- D99 PEG_TX14- A100 GND B100 GND C100 GND D100 GND A101 Reserved (NC) B101 Reserved (NC) C101 PEG_RX15+ D101 PEG_TX15+ A102 Reserved (NC) B102 Reserved (NC) C102 PEG_RX15- D102 PEG_TX15- A103 Reserved (NC) B103 Reserved (NC) C103 GND D103 GND A104 VCC_12V B104 VCC_12V C104 VCC_12V D104 VCC_12V A105 VCC_12V B105 VCC_12V C105 VCC_12V D105 VCC_12V A106 VCC_12V B106 VCC_12V C106 VCC_12V D106 VCC_12V A107 VCC_12V B107 VCC_12V C107 VCC_12V D107 VCC_12V A108 VCC_12V B108 VCC_12V C108 VCC_12V D108 VCC_12V A109 VCC_12V B109 VCC_12V C109 VCC_12V D109 VCC_12V A110 GND B110 GND C110 GND D110 GND
(NC): not connected *: multiplexed signal
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3.19 Watchdog
The Toucan-QM57 supports a watchdog function. This function can be configured by the LEMT tool and let the SMC send a watchdog signal out when the configured time is reached. The watchdog signal, which is available on COM-Express pin B27, has no access to the module but it could be used on the carrier e.g. to reset the module.
3.20 LEMT function
The onboard Microcontroller implements power sequencing and LEMT (LiPPERT Enhanced Management Technology) functionality. The microcontroller communicates via the System Management Bus with the CPU/Chipset. The following functions are implemented: · Total operating hours counter Counts the number of hours the module has been run in minutes. · On-time minutes counter Counts the seconds since last system start. · Temperature monitoring of CPU and Board temperature Minimum and maximum temperature values of CPU and board are stored in flash.
· Power cycles counter · Boot counter Counts the number of Boot attempts. · Watchdog Timer (Type-II) Set / Reset / Disable Watchdog Timer. Features auto-reload at power-up. · System Restart Cause Power loss / BIOS Fail / Watchdog / Internal Reset / External Reset. · Fail-Safe-BIOS Support In case of a Boot failure, hardware signals tells external logic to boot from Fail-Safe-BIOS. · Flash area 1kB Flash area for customer data
· 128 Bytes Protected Flash area Keys, ID's, etc. can stored in a write- and clear-protectable region.
· Board Identify Vendor / Board / Serial number / Production Date.
· Main-current & Voltages Monitors drawn current and main voltages
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Board Specific LEMT functions
Voltages The SMC of the Toucan-QM57 implements a Voltage Monitor and samples several Voltages. The Voltages can be ready by calling the LEMT function “Get Voltages”. The function returns a 16 Bit value divided in Hi-Byte (MSB) and Lo-Byte (LSB).
ADC Channel Voltage Voltage Name Formula [V] 0 ------1 ------2 ------3 +V1.05S_VTT (MSB<<8 + LSB) * 3.3 / 1024 4 +V1.05M (MSB<<8 + LSB) * 3.3 / 1024 5 +V5SBY (MSB<<8 + LSB) * 1.833 * 3.3 / 1024 6 +VIN (MSB<<8 + LSB) * 4.133 * 3.3 / 1024 7 (MAINCURRENT) Use Main Current Function
Main Current The SMC of the Toucan-QM57 implements a Current Monitor. The current can be read by calling the LEMT function “Get Main Current”. The function returns 4 16Bit values divided in Hi-Byte (MSB) and Lo-Byte (LSB). These 4 values represent the last 4 currents drawn by the board. The values are sampled every 250ms. The order of the 4 values is NOT in relationship to the time. The access to the SMC may increase the drawn current of the whole system. In this case, you still have 3 samples without the influence of the read access. Main Current = (MSB_n<<8 + LSB_n) * 8.06mA
TS#-Events TS# is activated by a Temperature sensor when a device reaches its critical temperature and released when the device is back into its normal temperature range. This counter gives the User information of Temperature/Cooling problems. This counter is cleared when the system is removed from power. The Toucan-QM57 monitors the CPU- and Board-temperature and does not support TS#-Events.
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Exception Codes In case of an error the SMC shows a blink code on the STATUS-LED. This error code is also reported by the SMC Flags register. The Exception Code is not stored in the Flash Storage and is cleared when the power is removed. Therefore the “Clear Exception Code”-Command is not supported.
Exception Error Message Code 0 NOERROR 2 NO_SUSCLK 3 NO_SLP_S5 4 NO_SLP_S3 5 NO_PWRGD_VIN 6 NO_PWRGD_3V3A 7 NO_PWRGD_IMVP 8 NO_PWRGD_ALL_SYS 9 NO_PWRGD_DDR3 13 +V1.05S_VTT 14 +V1.05M 15 +V5SBY 16 +VIN 18 BIOS_FAIL 19 NO_PWRGD_VGFX 20 LOW_VIN
SMC Flags The SMC Flags return the last detected Exception Code since Power-up. The upper 3 bits of the SMC Flags register are reserved for future use.
SMC Status This register show of the status of SMC controlled signals on the Toucan-QM57.
Status Bit Signal 0 SMC_WDACTIVE 1 BIOS_EN_SPI0 2 BIOS_EN_SPI1 3 SPI_WP# 4 SEL_PEG# 5 PCIE_2X8CONF 6 SMC_BKLT_EN 7 SMC_VDD_EN
3.21 CPU Fan Connector (X6)
The Toucan-QM57 provides a connector to power a CPU fan, if the module is actively cooled. Connector Type: HIROSE-DF13-3PIN-1M25-S Pin Signal 1 Speed Signal from fan (yellow) 2 +12VDC, regulated (red) 3 GND (black)
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4 Using the Module
4.1 BIOS
The Toucan-QM57 is delivered with a Phoenix Technology BIOS. The default settings guarantee a "ready to run" system, even without a BIOS setup backup battery. All setup changes of the BIOS are stored in the CMOS RAM. A copy of the CMOS RAM, excluding date and time, is stored in the flash memory. This means that even if the backup battery runs out of power, the BIOS settings are not lost. Only date and time will be reset to their default value. The battery will keep that information over 2 years without any activation of the board. That depends on the use of the board. When power is up, the battery does not lose capacity. The BIOS revision can be easily updated on-board with software under DOS.
Configuring the Phoenix BIOS Pressing
Initialize BIOS at first startup It is important to initialize the BIOS setting at first startup of the board. Call setup by pressing
Booting from alternative device Pressing the
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EFI Shell To start the EFI Shell you have to pressing the
Jumper BIOS Defaults To reload the default values automatically at power up the jumper “BIOS Settings” pin 1-2 on connector X3 must be plugged before power up. On power up the BIOS will recognize plugged jumper and load the setup defaults.
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BIOS Screens The BIOS setup utility allows setting of various board parameters. The following pictures show the different setup menus. The Toucan-QM57 specific settings are explained here.
Phoenix – SecureCore BIOS - Main
Phoenix – SecureCore BIOS – Main – System Information
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Advanced
Advanced – Boot Configuration
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Advanced – ACPI Configuration
Advanced – Processor Configuration
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Advanced – Processor Configuration – Processor Power Management
Advanced – Peripheral Configuration
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Advanced – HDD Configuration
Advanced – IMC Configuration
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Advanced – IMC Configuration – NB Common Configuration
Advanced – IMC Configuration – NB Common Configuration – VT for Directed I/O
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Advanced – IMC Configuration – NB Common Configuration – Video Configuration
Advanced – IMC Configuration – Arrandale Config
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Advanced – IMC Configuration – Arrandale Config – PEG Configuration
Advanced – IMC Configuration – Arrandale Config – IGD Config
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Advanced – IMC Configuration – Arrandale Config – IGD Config – Boot Type
Advanced – IMC Configuration – Arrandale Config – IGD Config – Panel Type
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Advanced – South Bridge Config
Advanced – South Bridge Config – SB PCI Express Config
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Advanced – South Bridge Config – SB PCI Express Config – PCI Express Root Port1
Advanced – Network Configuration
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Advanced – SMBIOS Event Log
Advanced – ME Configuration
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Advanced – Thermal Configuration
Advanced – Thermal Configuration – Processor Thermal Management Submenu
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Advanced – Thermal Configuration – Intelligent Power Sharing
Advanced – Thermal Configuration – Platform Thermal Configuration
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Security
Boot
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Exit
4.2 Drivers
Software drivers for Chipset, Ethernet and graphics adapter are available for the Toucan-QM57. These drivers can be downloaded from LiPPERT's website http://www.lippertembedded.com. Follow the installation instructions that come with the drivers.
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5 Address Maps
This section describes the mapping of the CPU memory and I/O address spaces.
Note: Depending on enabled or disabled functions in the BIOS, other or more resources may be used
5.1 Memory Address Map
Address Range (Hex) Description
000A0000-000BFFFF PCI-Bus
000A0000-000BFFFF VGASave
000D0000-000D3FFF PCI-Bus
000D4000-000D7FFF PCI-Bus
000D8000-000DBFFF PCI-Bus
3C000000-3C000FFF Resources
3C000000-FEAFFFFF PCI-Bus
D0000000-DFFFFFFF Graphics Controller
E0000000-EFFFFFFF Resources
F0000000-F03FFFFF Graphics Controller
F0400000-F041FFFF Ethernet Controller 82574L
F0400000-F04FFFFF PCI Express – 3B4A
F0420000-F0423FFF Ethernet Controller 82574L
F0700000-F071FFFF Ethernet Controller 82577LM
F0720000-F0723FFF PCI Device
F0724000-F072400F AMT
F0726000-F0726FFF PCI
F0727000-F0727FFF Ethernet Controller 82577LM
F0728000-F07283FF USB Enhanced Host Controller – 3B3C
F0729000-F07293FF USB Enhanced Host Controller – 3B34
F072A000-F072A0FF SMBus Controller – 3B30
F072B000-F072BFFF Resources
FED00000-FED003FF Timer
FED10000-FED13FFF Resources
FED18000-FED18FFF Resources
FED19000-FED19FFF Resources
FED1C000-FED1FFFF Resources
FED20000-FED3FFFF Resources
FED40000-FED44FFF Resources
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Address Range (Hex) Description
FED45000-FED8FFFF Resources
FEE00000-FEEFFFFF Resources
FF000000-FFFFFFFF Resources
FF000000-FFFFFFFF Firmware Hub
5.2 I/O Address Map
The system chipset implements a number of registers in I/O address space. These registers occupy the following map in the I/O space (depending on enabled or disabled functions in the BIOS other or more resources may be used).
Address Range (Hex) Description 0000-001F DMA Controller 0000-0CF7 PCI-Bus 0020-0021 Interrupt Controller 0024-0025 Interrupt Controller 0028-0029 Interrupt Controller 002C-002D Interrupt Controller 002E-002F Resources 0030-0031 Interrupt Controller 0034-0035 Interrupt Controller 0038-0039 Interrupt Controller 003C-003D Interrupt Controller 0040-0043 Timer Controller 004E-005F Resources 0050-0053 Timer Controller 0060-0060 Resources 0061-0061 Resources 0063-0063 Resources 0064-0064 Resources 0065-0065 Resources 0067-0067 Resources 0070-0070 Resources 0070-0077 CMOS / Real Time Clock 0080-0080 Resources 0081-0091 DMA Controller 0092-0092 Resources 0093-009F DMA Controller 00A0-00A1 Interrupt Controller 00A4-00A5 Interrupt Controller
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Address Range (Hex) Description 00A8-00A9 Interrupt Controller 00AC-00AD Interrupt Controller 00B0-00B1 Interrupt Controller 00B2-00B3 Resources 00B4-00B5 Interrupt Controller 00B8-00B9 Interrupt Controller 00BC-00BD Interrupt Controller 00C0-00DF DMA Controller 00F0-00F0 Math Coprocessor 01CE-01CF VGASave 0274-0277 ISAPnP Data port 0279-0279 ISAPnP Data port 02E8-02EF VGASave 03B0-03BB VGASave 03C0-03DF VGASave 0400-047F Resources 04D0-04D1 Interrupt Controller 0500-050F Resources 0600-0603 Resources 0680-069F Resources 0A79-0A79 ISAPnP Data port 0D00-FFFF PCI Bus 1180-11FF Resources 164E-164F Resources 1800-1807 Graphics Controller 1808-180F PCI 1810-181F SATA Controller – 3B2E 1820-183F Ethernet Controller 82577LM 1840-184F SATA Controller – 3B2E 1850-1853 SATA Controller – 3B2E 1854-1857 SATA Controller – 3B2E 1858-185F SATA Controller – 3B2E 1860-1867 SATA Controller – 3B2E 1868-186B SATA Controller – 3B2D 186C-186F SATA Controller – 3B2D 1870-187F SATA Controller – 3B2D 1880-189F SMBus Controller – 3B30 18A0-18AF SATA Controller – 3B2D
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Address Range (Hex) Description 18B0-18B7 SATA Controller – 3B2D 18B8-18BF SATA Controller – 3B2D 2000-201F Ethernet Controller 82574L 2000-2FFF PCI Express – 3B4A FE00-FE00 Resources FFFF-FFFF Resources
5.3 Interrupts
IRQ (Bus) System Resource
0 (ISA) Timer
8 (ISA) Timer
9 (ISA) ACPI-conform System
13 (ISA) Math coprocessor
7 (PCI) Graphic Controller
7 (PCI) AMT
12 (PCI) AMT
16 (PCI) PCI Express – 3B42
16 (PCI) PCI Express – 3B4A
16 (PCI) USB Enhanced Host Controller – 3B3C
16 (PCI) Ethernet Controller 82574L
19 (PCI) SATA Controller – 3B2D
19 (PCI) SATA Controller – 3B2E
20 (PCI) Ethernet Controller 82577LM
23 (PCI) USB Enhanced Host Controller – 3B34
5.4 DMA Channels
DMA System Resource
4 DMA Controller
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6 Troubleshooting
First steps if the board does not boot:
· Check the status LEDs on the board. Are all voltages properly available? · Check the power connectors to the board, monitor and additional devices. · Are all cables plugged on the correct connector and in the correct orientation? The board may not boot if some of the cables are not plugged in correctly!
· Check the power supply. Is the supply voltage correct for the board? If you are not sure, read the manual. Try plugging in a different power supply or multi-meter to check the power a wrong supply voltage can easily FRY a computer and other electrical devices.
· Is your display ok? Is the monitor powered on? Is the monitor's video cable plugged into the video connector? Double-check the brightness and contrast settings. Plug the monitor into another computer if possible to verify the monitor is not the problem. · Remove all additional devices from the system. Only the processor board, power supply, monitors and the keyboard should remain in the system. · Assure your cooling measures work correctly and keep the processor at a reasonable temperature. · If all else has failed, replace the CPU Board itself. · If system comes up then load at first the OPTIMIZED DEFAULTS in the BIOS setup and reboot.
If you need to send the board to LiPPERT for repair, be sure you get a Return Material Authorization number (RMA) first. Check also Appendix B (Getting Help).
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Contact Information
Headquarters LiPPERT Embedded Computers GmbH Hans-Thoma-Straße 11 68163 Mannheim Germany
Phone +49 621 432140 Fax +49 621 4321430 E-mail [email protected] [email protected] Website www.lippertembedded.com
US Office LiPPERT Embedded Computers, Inc. 2220 Northmont Parkway, Suite 250 Duluth, GA 30096 USA
Phone +1 (770) 295 0031 Fax +1 (678) 417 6273 E-mail [email protected] [email protected] Website www.lippertembedded.com
TME-TOUCANQM-R0V3.docx Revision 0.3 Appendix A
Getting Help
Should you have technical questions that are not covered by the respective manuals, please contact our support department at [email protected].
Please allow one working day for an answer!
Technical manuals as well as other literature for all LiPPERT products can be found in the Products section of LiPPERT's website www.lippertembedded.com. Simply locate the product in question and follow the link to its manual.
Returning Products for Repair To return a product to LiPPERT for repair, you need to get a Return Material Authorization (RMA) number first. Please fill in the RMA Request Form at http://www.lippertembedded.com/service/repairs.html and send it to us. We'll return it to you with the RMA number.
Deliveries without a valid RMA number are returned to sender at his own cost!
LiPPERT has a written Warranty and Repair Policy, which can be retrieved from http://www.lippertembedded.com/media/downloads/General/BM14007_1V6.pdf It describes how defective products are handled and what the related costs are. Please read this document carefully before returning a product.
TME-TOUCANQM-R0V3.docx Revision 0.3 Appendix B
Additional Information
www.lippertembedded.com Where Toucan-QM57 comes from.
www.intel.com Manufacturer of the used CPU, Chipset and Ethernet-Controller.
www.pcisig.com Where PCI Express specification was defined.
www.picmg.org Where COM Express specification was defined.
www.usb.org Universal Serial Bus (USB) connects computers, peripherals and more.
www.smbus.org SMBus is the System Management Bus defined by Intel.
www.sata-io.org All about Serial ATA.
http://www.phoenix.com Additional BIOS information.
TME-TOUCANQM-R0V3.docx Revision 0.3 Appendix C
Revision History
Filename Date Edited Change by TME-TOUCANQM-R0V0.doc 2011-04-04 UW Draft TME-TOUCANQM-R0V1.doc 2011-05-31 JS Extended Input Voltage to 5-12V, Power Consumption defined, SATA-LED added, LEMT functions TME-TOUCANQM-R0V2.doc 2011-06-09 MF Added chapter RS DIMM socket TME-TOUCANQM-R0V3.doc 2011-06-14 MF Name change RS-DIMM to XR-DIMM
TME-TOUCANQM-R0V3.docx Revision 0.3 Appendix D