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Intel® 3 Series Express Chipset Family

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Intel® 3 Series Express Chipset Family Intel® 3 Series Express Chipset Family Datasheet - For the Intel® 82Q35, 82Q33, 82G33 Graphics and Memory Controller Hub (GMCH) and Intel® 82P35 Memory Controller Hub (MCH) August 2007 Document Number: 316966-002 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel® 82Q35 GMCH, 82Q33 GMCH, 82G33 GMCH, and 82P35 MCH may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel. Implementations of the I2C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation. Intel, Pentium, Intel Core, Intel Inside, and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2007, Intel Corporation. All rights reserved. 2 Datasheet Contents 1 Introduction ...................................................................................................19 1.1 Terminology ........................................................................................24 1.2 Reference Documents ...........................................................................26 1.3 (G)MCH Overview.................................................................................27 1.3.1 Host Interface.........................................................................27 1.3.2 System Memory Interface.........................................................28 1.3.3 Direct Media Interface (DMI).....................................................29 1.3.4 PCI Express* Interface.............................................................29 ® 1.3.5 Graphics Features (Intel 82Q35, 82Q33, 82G33 GMCH Only) .......30 ® 1.3.6 SDVO and Analog Display Features (Intel 82Q35, 82Q33, 82G33 GMCH Only) .................................................................30 1.3.7 (G)MCH Clocking.....................................................................31 1.3.8 Thermal Sensor ......................................................................31 1.3.9 Power Management .................................................................32 ® ® 1.3.10 Intel Active Management Technology (Intel AMT)/ Controller ® Link (Intel 82Q35 GMCH Only) ................................................32 ® ® 1.3.11 Intel Trusted Execution Technology (Intel 82Q35 GMCH Only) ....33 ® ® 1.3.12 Intel Virtualization Technology for Directed I/O (Intel VT-d) ® (Intel 82Q35 GMCH Only) .......................................................33 2 Signal Description ...........................................................................................35 2.1 Host Interface Signals...........................................................................36 2.2 System Memory (DDR2/DDR3) Channel A Interface Signals........................40 2.3 System Memory (DDR2/DDR3) Channel B Interface Signals........................41 2.4 System Memory DDR2/DDR3 Miscellaneous Signals ..................................42 2.5 PCI Express* Interface Signals ...............................................................43 2.6 Controller Link Interface Signals .............................................................43 ® 2.7 Analog Display Signals (Intel 82Q33, GMCH, 82Q33 GMCH, and 82G33 GMCH Only) ........................................................................................44 2.8 Clocks, Reset, and Miscellaneous ............................................................45 2.9 Direct Media Interface...........................................................................46 ® 2.10 Serial DVO Interface (Intel 82Q35, 82Q33, 82G33 GMCH Only).................47 2.11 Power and Grounds ..............................................................................50 3 System Address Map .......................................................................................51 3.1 Legacy Address Range ..........................................................................55 3.1.1 DOS Range (0h – 9_FFFFh).......................................................56 3.1.2 Legacy Video Area (A_0000h – B_FFFFh) ....................................56 3.1.3 Expansion Area (C_0000h – D_FFFFh)........................................57 3.1.4 Extended System BIOS Area (E_0000h-E_FFFFh).........................57 3.1.5 System BIOS Area (F_0000h-F_FFFFh).......................................58 3.1.6 PAM Memory Area Details.........................................................58 3.2 Main Memory Address Range (1MB – TOLUD) ...........................................59 3.2.1 ISA Hole (15 MB-16 MB) ..........................................................60 3.2.2 TSEG.....................................................................................60 3.2.3 Pre-allocated Memory ..............................................................60 Datasheet 3 3.3 PCI Memory Address Range (TOLUD – 4GB) .............................................61 3.3.1 APIC Configuration Space (FEC0_0000h–FECF_FFFFh) ..................63 3.3.2 HSEG (FEDA_0000h–FEDB_FFFFh).............................................63 3.3.3 FSB Interrupt Memory Space (FEE0_0000–FEEF_FFFF) .................63 3.3.4 High BIOS Area.......................................................................63 3.4 Main Memory Address Space (4 GB to TOUUD) .........................................64 3.4.1 Memory Re-claim Background ...................................................65 3.4.2 Memory Reclaiming .................................................................65 3.5 PCI Express* Configuration Address Space...............................................65 3.6 PCI Express* Graphics Attach (PEG)........................................................66 ® 3.7 Graphics Memory Address Ranges (Intel 82Q35, 82Q33, and 82G33 (G)MCH Only) ......................................................................................67 3.8 System Management Mode (SMM) ..........................................................67 3.8.1 SMM Space Definition ..............................................................68 3.8.2 SMM Space Restrictions............................................................68 3.8.3 SMM Space Combinations.........................................................69 3.8.4 SMM Control Combinations .......................................................69 3.8.5 SMM Space Decode and Transaction Handling..............................69 3.8.6 Processor WB Transaction to an Enabled SMM Address Space ........69 ® 3.8.7 SMM Access through GTT TLB (Intel 82Q35, 82Q33, 82G33 GMCH Only) ...........................................................................70 3.9 Memory Shadowing ..............................................................................70 3.10 I/O Address Space................................................................................70 3.10.1 PCI Express* I/O Address Mapping ............................................71 3.11 (G)MCH Decode Rules and Cross-Bridge Address Mapping ..........................72 3.11.1 Legacy VGA and I/O Range Decode Rules ...................................72 4 (G)MCH Register Description ............................................................................73 4.1 Register Terminology ............................................................................74 4.2 Configuration Process and Registers........................................................76 4.2.1 Platform Configuration Structure ...............................................76 4.3 Configuration Mechanisms .....................................................................77 4.3.1 Standard PCI Configuration Mechanism ......................................77 4.3.2 PCI Express* Enhanced Configuration Mechanism ........................77 4.4 Routing Configuration Accesses ..............................................................79 4.4.1 Internal Device Configuration Accesses.......................................80 4.4.2 Bridge Related Configuration Accesses........................................80 4.4.2.1 PCI Express* Configuration Accesses ...........................80 4.4.2.2 DMI Configuration Accesses .......................................81
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