PEX 8114RDK-F Hardware Reference Manual for Board Rev 300

PEX 8114RDK-F Hardware Reference Manual For Board Revision 300

Version 4.2

February 2008

Website: www.plxtech.com Technical Support: www.plxtech.com/support

© 2008 PLX Technology, Inc. All Rights Reserved. PLX Technology, Inc. retains the right to make changes to this product at any time, without notice. Products may have minor variations to this publication, known as errata. PLX assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of PLX products. PLX Technology and the PLX logo are registered trademarks and ExpressLane is a trademark of PLX Technology, Inc. Other brands and names are the property of their respective owners. Order Number: PEX 8114-RDK/F-HRM-P1-4.2

PEX 8114RDK-F Hardware Reference Manual, Version 4.2 ii © 2008 PLX Technology, Inc. All Rights Reserved. Contents 1 General Information ...... 1 1.1 PEX 8114 Features ...... 2 1.2 PEX 8114RDK-F Features ...... 2 2 System Architecture...... 3 3 Hardware Architecture ...... 5 3.1 PEX 8114 Bridge Device...... 5 3.2 JTAG Interface ...... 5 3.3 Serial EEPROM Interface...... 5 3.3.1 Serial EEPROM Contents...... 5 3.4 Strapping Switches – SW9 and SW10 ...... 6 3.5 PCI/PCI-X Interface ...... 7 3.5.1 Slot Connectors...... 7 3.5.2 PCI Terminations ...... 8 3.5.3 PCI CLK ...... 8 3.5.4 Probing Points...... 8 3.6 PCI Express Interface...... 8 3.6.1 RefClk ...... 8 3.6.2 PERST# ...... 8 3.6.3 Lane Status LED Indicators ...... 8 3.6.4 Hot Plug ...... 8 3.7 Power...... 9 3.7.1 Board Power ...... 9 3.7.2 PEX 8114 Bridge Device Power ...... 9 3.7.2.1 PEX 8114 Voltage Generation ...... 9 3.7.2.2 PEX 8114 Voltage Sequencing ...... 9 3.7.3 PCI/PCI-X Bus Power ...... 10 4 Mechanical Architecture...... 11 4.1 Monitoring Point, LED Indicator, and Control Summary ...... 12 4.1.1 Monitoring Points ...... 12 4.1.2 LED Indicators...... 13 4.1.3 Controls...... 14 4.2 Layout Information...... 15 4.2.1 Trace Routing Design Rules ...... 15 4.2.2 Power Decoupling...... 15 4.2.3 PCB Layer Stackup...... 16 5 Netlengths ...... 17 6 Frequently Asked Questions...... 21 7 References...... 22 8 Bill of Materials and Schematics ...... 23

PEX 8114RDK-F Hardware Reference Manual, Version 4.2 © 2008 PLX Technology, Inc. All Rights Reserved. iii Figures Figure 1. PEX 8114RDK-F – Component Side View ...... 1 Figure 2. PEX 8114RDK-F Functional Block Diagram...... 4 Figure 3. JTAG (JP1) Header (Viewed from Top) ...... 5 Figure 4. Strapping (SW9) and PCI/PCI-X Clock Frequency (SW10) Control Circuitry...... 6 Figure 5. PCI/PCI-X Bus Arrangement Slots Diagram...... 7 Figure 6. PEX 8114RDK-F Component Placement (Primary Component Side) ...... 11 Figure 7. Decoupling Capacitor Footprints...... 15 Figure 8. PEX 8114RDK-F 10-Layer PCB Stackup ...... 16

Tables Table 1. Clock Frequency and Slot Usage...... 3 Table 2. Supported Clock Frequencies, by Slot ...... 7 Table 3. PEX 8114RDK-F Monitoring Points ...... 12 Table 4. PEX 8114RDK-F LED Indicators...... 13 Table 5. PEX 8114RDK-F Controls...... 14 Table 6. PCI/PCI-X Signal Trace Netlengths ...... 17 Table 7. PCI Express Signal Trace Netlengths ...... 20

PEX 8114RDK-F Hardware Reference Manual, Version 4.2 iv © 2008 PLX Technology, Inc. All Rights Reserved. Preface Notice This manual contains PLX Confidential and Proprietary information. The contents of this manual may not be copied nor duplicated in any form, in whole or in part, without prior written consent from PLX Technology, Inc. PLX provides the information and data included in this manual for your benefit, but it is not possible to entirely verify and test all the information, in all circumstances, particularly information relating to non-PLX manufactured products. PLX makes neither warranty nor representation relating to the quality, content, or adequacy of this information. The information in this manual is subject to change without notice. Although every effort has been made to ensure the accuracy of this manual, PLX shall not be liable for any errors, incidental or consequential damages in connection with the furnishing, performance, or use of this manual or examples herein. PLX assumes no responsibility for damage or loss resulting from the use of this manual, for loss or claims by third parties, which may arise through the use of the PEX 8114RDK-F, or for any damage or loss caused by deletion of data as a result of malfunction or repair.

About This Manual This manual describes the PLX PEX 8114RDK-F, the PEX 8114 Forward Bridge RDK Board Rapid Development Kit, from a hardware perspective. It contains a description of all major functional circuit blocks on the PEX 8114RDK-F and also is a reference for the creation of software for this product. This manual also includes a complete Bill of Materials and Schematics.

Revision History

Date Version Comments April 2005 1.0 Initial release. Supports Board Revision 001. April 2005 1.1 Update to support Board Revision 100. • Updated Figure 1, Figure 2, and Figure 4. • Removed Figure 6 and renumbered remaining figures. • Added missing greater than/less than symbols for Section 3.3 bullets. • Replaced second sentence of first paragraph in Section 3.4. • Added information regarding 100MHz to Section 3.5.1. July 2005 1.2 • Appended “Slots Diagram” to Figure 5 title. • Rewrote content of Section 3.5.3. • Reworded first bullet of Section 3.7. • Corrected first sentence of Section 3.7.1 regarding use for on-board voltage generation. • Added DS9 information to Section 4.1.2. • Replaced bill of materials in Section 5. March 2.0 • Completely revised to support Board Revision 202. 2006 September • Updated Section 3.7.3. 3.0 2006 • Completely revised to support Board Revision 300. • Updated to reflect use of PEX 8114BB device. November • Miscellaneous changes and enhancements throughout manual. 4.0 2006 • Added new section, “Frequently Asked Questions.” • Removed references to Non-Transparent mode. March • Updated to reflect use of PEX 8114BC device. 4.1 2007 • Updated the schematics. February • Updated to reflect use of PEX 8114BD device. 4.2 2008 • Updated the schematics.

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The PLX PEX 8114RDK-F is a Rapid Development Kit based on the PLX ExpressLane™ PEX 8114 PCI Express-to-PCI/PCI-X bridge device implementing Forward Bridge mode. The PEX 8114RDK-F is a complete hardware and software development platform to facilitate getting designs up and running quickly, lowering risk and time-to-market. The PEX 8114RDK-F allows the upstream PCI Express port of the PEX 8114 bridge device to be connected to a host system slot by way of a standard PCI Express board edge connector; the PEX 8114RDK-F is designed to plug into a PCI Express motherboard slot. The PEX 8114RDK-F also allows for up to four PCI or PCI-X adapters to be plugged into the downstream bus, by way of four standard PCI/PCI-X Slots located on the PEX 8114RDK-F.

Figure 1. PEX 8114RDK-F – Component Side View

PEX 8114RDK-F Hardware Reference Manual, Version 4.2 © 2008 PLX Technology, Inc. All Rights Reserved. 1 1.1 PEX 8114 Features Supports Forward and Reverse Bridging Note: The PEX 8114RDK-F is for Forward Bridge mode designs. For Reverse Bridge mode designs, refer to the PEX 8114RDK-R. Single PCI Express port capable of x4, x2, or x1 link width Single PCI-X Bus segment supporting PCI-X protocol at 64-bit/133MHz and/or PCI Local Bus Specification, Revision 3.0 Standard 256-ball PBGA package (17x17mm2) Advanced PCI Express features supported include Advanced Flow Control, Advanced Error Reporting, Integrated Hot Plug, ECRC and Poison Bit, Automatic Polarity, and Lane Reversal Fully integrated PCI Express PHY with 8b/10b encoding, hardware link training, and low-power programmable SerDes Compliant to the following specifications: PCI Local Bus Specification, Revision 3.0 PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0 PCI Express Base Specification, Revision 1.0a

1.2 PEX 8114RDK-F Features PLX PCI Express-to-PCI/PCI-X bridge device Form factor based on PCI Express Card Electromechanical (CEM) Specification, Revision 1.1 Single x4 PCI Express board edge connector for insertion into standard PCI Express Slot of x4 or greater link width Note: A mechanical connector is available to adapt the PEX 8114RDK-F to an x1 slot. Contact your local PLX Sales Representative, if this is required. Four downstream 64-bit PCI or PCI-X Slots on secondary side Socketable serial EEPROM for easy configuration Lane Status Indicator LEDs for easy visual inspection of PCI Express link and lane status ATX connector for additional power requirements DIP switches for PEX 8114 hardware configuration Indicator LEDs for easy visual inspection of DIP switch settings On-board probing points On-board manual Reset switches

The PEX 8114RDK-F assists customers in evaluating PLX Technology’s PEX 8114 PCI Express-to- PCI/PCI-X bridge device, and facilitates early development of customer designs with the PEX 8114. The usage configuration is forward bridging between a PCI Express baseboard and PCI/PCI-X add-in boards. The PEX 8114RDK-F is designed to showcase all features of the PEX 8114 when operating in Forward Bridge mode. The PEX 8114RDK-F’s form factor is based on the PCI Express Card Electromechanical (CEM) Specification, Revision 1.1. The PCI/PCI-X interface supports up to 64-bit transfers, at up to 133MHz. (Refer to Figure 2.) The PEX 8114RDK-F has four PCI/PCI-X slot (female) connectors – one straddle- mount and three baseboard mounts. Table 1 defines the slot usage when the PEX 8114RDK-F is operating at different clock frequencies. Four INTx# and four REQ#/GNT# pairs are supported, one for each slot. Each PCI-X signal trace has a test-point (TP) via with an easily readable silkscreen label. The PCI Express interface supports up to four lanes, with each lane capable of up to 2.5 Gbps. PEX 8114RDK-F power is generated from +3.3 VDC, provided through the PCI Express board edge connector. PCI/PCI-X Bus power is generated on-board or supplied from a 20-pin ATX header for larger current draws.

Table 1. Clock Frequency and Slot Usage

Clock Frequency Slot Usage Slots 1, 2, and 3 are isolated by Q-switches 100 to 133MHz Only Slot 0 is used Slots 2 and 3 are isolated by Q-switches 66 to 100MHz Only Slots 0 and 1 are used 66MHz and below All four slots can be loaded

Figure 2. PEX 8114RDK-F Functional Block Diagram

There are several subsystems on the PEX 8114RDK-F. Among them are a power system that powers the PEX 8114, a power system that powers the PCI/PCI-X Bus, and controls and indicators. The following sections describe each PEX 8114RDK-F subsystem.

3.1 PEX 8114 Bridge Device The PEX 8114 is housed in a 17x17mm2 256-ball PBGA package. Ball pitch is 1.0 mm. No additional cooling is required.

3.2 JTAG Interface The PEX 8114 has a JTAG interface, which is connected to a 2x5 header. (Refer to Figure 3.) The PEX 8114 JTAG interface can also be connected to the PCI Express board edge connector JTAG pins through 0-Ohm resistors. There is no “standard” JTAG header pin arrangement; therefore, JTAG header type and pin assignments are somewhat arbitrary. The header and pin assignments chosen for the PEX 8114RDK-F are compatible with the Corelis JTAG single TAP cable (AS00790050-A0). Pin 1 - TRST# Pin 3 - TDI Pin 5 - TDO Pin 7 - TMS Pin 9 - TCK

Figure 3. JTAG (JP1) Header (Viewed from Top)

3.3 Serial EEPROM Interface The PEX 8114 has an SPI EEPROM interface, which can be used to load Configuration data from a serial EEPROM at power-up. This interface is connected to an 8-pin DIP socket (U65), which houses the serial EEPROM. Jumper JP14 (refer to Figure 1), adjacent to this DIP socket, indicates to the PEX 8114 that the serial EEPROM is present when the jumper is inserted. 1 KB of serial EEPROM storage is sufficient. If the application requires Expansion ROM space, up to a 64-KB serial EEPROM can be used. The serial EEPROM must complete loading within 10 ms, and must be capable of being clocked at 7.8MHz (the clock frequency output by the PEX 8114). Serial EEPROM I/O signaling levels must meet the following values, to be compatible with the PEX 8114 TTL I/O levels:

VIL < 0.4V

VIH > 2.4V

VOL < 0.8V

VOH > 2.0V The Atmel AT25xxxA family of serial EEPROMs is one possible family of serial EEPROMs that can be used. The PEX 8114RDK-F includes a pre-programmed AT25640A serial EEPROM.

3.3.1 Serial EEPROM Contents Refer to the PEX 8114BC/BD Data Book, Appendix A, “Serial EEPROM Map.”

PEX 8114RDK-F Hardware Reference Manual, Version 4.2 © 2008 PLX Technology, Inc. All Rights Reserved. 5 3.4 Strapping Switches – SW9 and SW10 The PEX 8114 has several balls used for functional mode setup of the bridge device. The Strapping balls that are user-selectable are controlled by DIP switches on SW9. Figure 4 describes the circuitry for controlling the Strapping balls (using SW9) and PCI/PCI-X clock frequency (using SW10), and indicates the default switch settings. A table listing the SW10 switch combinations is silkscreened on the PEX 8114RDK-F, and is provided below in Figure 4. LEDs indicate switch settings and PCI/PCI-X clock frequency.

Strapping Switches CLOSED = Low OPEN = High OPEN PLL BYPASS# PLL BYPASS# Internal PLL Bypassed Internal PLL Used, LED Off CLOSED PCLK-FDBK OPEN TRAN PCLK-FDBK PCI CLK feedback Off PCI CLK feedback On, LED On ARBITER OPEN TRAN - (always OPEN) Transparent bridge, LED On SW9 ARBITER Internal Arbiter Off Internal Arbiter On, LED On

PCIXCAP PCI-SEL OPEN CLOSED CLOSED Switches PCIX-SEL DON’T-CARE OPEN CLOSED

CLOSED PCI-SEL M66EN PCI-SEL100 OPEN PCIX-SEL OPEN M66EN CLOSED CLOSED PCI-33 PCIX-66 PCIX-133 CLOSED PCI-SEL100 CLOSED = Low, CLOSED OPEN PCI-25 PCIX-50 PCIX-100 OPEN = High SW10 OPEN CLOSED PCI-66 PCIX-66 PCIX-133

OPEN OPEN PCI-50 PCIX-50 PCIX-100

PCI-SEL 3.3VDC PCIXCAP_PU PIN Low

1K 56K High PCIXCAP PIN Low 0.01 uF 10K

High PCIX-SEL

Figure 4. Strapping (SW9) and PCI/PCI-X Clock Frequency (SW10) Control Circuitry

PEX 8114RDK-F Hardware Reference Manual, Version 4.2 6 © 2008 PLX Technology, Inc. All Rights Reserved. 3.5 PCI/PCI-X Interface The PCI/PCI-X interface is set up as a four-slot motherboard. Each slot has its own REQ/GNT pair, which can be arbitrated by the PEX 8114. The PEX 8114 also drives individual PCI_CLKO signals to each slot.

3.5.1 Slot Connectors The PEX 8114RDK-F has four female PCI/PCI-X slots. (Refer to Figure 5.) Slot 3 is a straddle-mount connector, so that any board plugged into Slot 3 will be in-plane with the bridge board. The remaining three slots are baseboard connectors. All four slots are capable of running up to 64-bit data and are strictly 3.3V. All four slots support up to 66-MHz transfers; however, only Slots 0 and 1 support up to 100-MHz transfers, and only Slot 0 supports up to 133MHz transfers. When operating faster than 66MHz, Slots 2 and 3 are isolated from the bus by Q-switches. When operating faster than 100MHz, Slots 1, 2, and 3 are isolated from the bus by Q-switches. (Refer to Table 2.)

Table 2. Supported Clock Frequencies, by Slot

Clock Frequency (MHz) Slot Up to 66 Up to 100 Up to 133 (JP15 and JP16 Installed) (JP15 Installed) (Neither Jumper Installed) 0 4 4 4 1 4 4 2 4 3 4

Figure 5. PCI/PCI-X Bus Arrangement Slots Diagram

PEX 8114RDK-F Hardware Reference Manual, Version 4.2 © 2008 PLX Technology, Inc. All Rights Reserved. 7 3.5.2 PCI Terminations The upper 32-bit transfer lines are pulled up to PCI_3P3 by way of 8.2K-Ohm resistors, to hold the upper lines to known values when not being driven. The four REQ# lines (PCI_REQ[3:0]#) are also pulled up by way of 8.2K-Ohm resistors, to hold these lines for unpopulated slots.

3.5.3 PCI CLK The PEX 8114 is capable of driving four separate PCI_CLKO signals (PCI_CLKO[3:0]), which are point- to-point routed and length-matched to each of the four PCI/PCI-X slots.

3.5.4 Probing Points All PCI/PCI-X signals are associated with a Test-Point Via (TPV). Each via has a silkscreen label clearly identifying its associated signal. (Refer to Figure 5.)

3.6 PCI Express Interface The PCI Express interface is a male board edge connector, based on the PCI Express Card Electromechanical (CEM) Specification, Revision 1.1, for an x4 interface. This connector provides +12 VDC and +3.3 VDC, RefClk, and PERST#. The PCI Express lanes are laid out as 100-Ohm, controlled-impedance, stripline-differential pairs. Within-pair trace-length mismatch is not greater than 0.127 mm (0.005 inches). Layer stackup is ground plane – signal plane – ground plane.

3.6.1 RefClk PCI Express RefClk enters the PEX 8114RDK-F through the PCI Express board edge (male) connector. RefClk is laid out as a 100-Ohm, controlled-impedance, stripline-differential pair. Trace-length mismatch is not greater than 0.127 mm (0.005 inches). RefClk must, and does, pass through AC-coupling capacitors before entering the PEX 8114. Valid values for the AC-coupling capacitors are the same as for the PCI Express Base Specification, Revision 1.0a recommendation (75 to 200 nF, with package sizes of 0603 or 0402). The PEX 8114RDK-F uses 0.1 µF values in 0402 packages.

3.6.2 PERST# PERST# into the PEX 8114 is generated by ANDing three signals: PEX 8114 Power Good signal from the Power Sequencer PERST# from the PCI Express board edge connector Manual PERST# generated by the SW7 pushbutton

Red LED DS3 indicates PERST# assertion, and momentarily blinks On when the PEX 8114RDK-F is first powered up.

3.6.3 Lane Status LED Indicators Four green surface-mount LEDs (DS6, DS2, DS4, and DS5) are attached to the four PEX 8114 PEX_LANE_GOOD[3:0]# balls, respectively, to indicate lane status. A lane is active when its LED is turned On.

3.6.4 Hot Plug PCI Express Hot Plug is not supported on the PEX 8114RDK-F. This is because the PEX 8114RDK-F is meant to plug into a PCI Express baseboard, so the RDK cannot control power to other PCI Express slots. PCI Express Hot Plug is supported, however, on the Reverse Bridge RDK board, PEX 8114RDK-R. (Refer to the PEX 8114RDK-R Hardware Reference Manual.) Additionally, the PEX 8114 does not support PCI-X Hot Plug.

PEX 8114RDK-F Hardware Reference Manual, Version 4.2 8 © 2008 PLX Technology, Inc. All Rights Reserved. 3.7 Power The PEX 8114RDK-F has three power domains: PEX 8114RDK-F board power supplied by the PCI Express board edge connector PEX 8114 bridge device power PCI/PCI-X Bus power

3.7.1 Board Power +3.3 VDC from the PCI Express board edge connector is used to generate voltages for the PEX 8114, and power the Power Sequencer IC (U14) used to turn On voltages to the PEX 8114. This voltage also powers circuitry that is not directly connected to the PEX 8114. If voltages are applied to the PEX 8114 +3.3 VDC VIO balls (such as PCI signals, Strapping balls, and so forth) without the PEX 8114 VDD33 balls being powered, the internal power ring begins to energize and a value of approximately +1.8V appears at the VDD33 balls. This is not known to cause a problem; however, the PEX 8114RDK-F ensures that this condition never occurs.

3.7.2 PEX 8114 Bridge Device Power PEX 8114 power consists of: VDD Core +1.0 ±0.1 VDC VTT +1.35 to +1.8 VDC VIO +3.3 ±0.3 VDC

3.7.2.1 PEX 8114 Voltage Generation VDD10 and VDD10S are tied together and supplied by the +1.0 VDC power plane. +3.3 VDC is provided to the PEX 8114RDK-F by way of the PCI Express board edge connector and passed to VIO. +3.3 VDC is also used to generate VDD Core and VTT. The PEX 8114 VTT voltage is jumper-selectable (JP7) and can be fixed at +1.5 VDC (jumper pins 1 and 2), or adjustable by way of a potentiometer (R91) (jumper pins 2 and 3). The two PEX 8114 analog voltages, VDD33A and VDD10A, power internal core and SerDes PLLs. These voltages are delivered to the PEX 8114 from the VIO and VDD Core voltages, through LC filtering circuits. 3.7.2.2 PEX 8114 Voltage Sequencing All three voltages (+3.3 VDC, VTT, and +1.0 VDC) can be sequentially turned On by the Power Sequencer IC (U14), which controls three MOSFET switches (Q5, Q6, and Q7). Optimal power sequence is from lowest to highest voltage. The Power Sequencer monitors under-voltage conditions, and turns Off PEX 8114 power when a fault is detected. Power-up sequencing is initiated by a one-shot Supervisor IC (U16) with a 3-ms timeout, powered by the +3.3 VDC from the PCI Express board edge connector. Power sequencing can also be manually initiated, using pushbutton SW8. Red LED DS8 indicates when the PEX 8114RDK-F is receiving +3.3 VDC; however, the sequencer is not enabled. This LED momentarily blinks On when the PEX 8114RDK-F is first powered up. Alternatively, the Power Sequencer can be bypassed by removing the Q5, Q6, and Q7 MOSFET switches and installing fuses F10, F9, and F3, respectively. To date, this power-up method has been successfully implemented without experiencing problems. If current draw measurements are needed, F10, F9, and F3 can be populated with current sense resistors instead.

PEX 8114RDK-F Hardware Reference Manual, Version 4.2 © 2008 PLX Technology, Inc. All Rights Reserved. 9 3.7.3 PCI/PCI-X Bus Power Per the PCI Local Bus Specification, Revision 3.0,PCI/PCI-X Bus power consists of four voltages: +12 VDC ±5% +5 VDC ±5% +3.3 VDC ± 0.3V -12 VDC ±10%

These voltages can be provided by two sources – on-board generation or from a 20-pin ATX header (P16). For on-board generation, the 20-pin ATX header cannot be connected. PCI_5P0 and PCI_N12P0 are generated from +12 VDC, provided through the PCI Express board edge connector. +12 VDC and +3.3 VDC from the PCI Express board edge connector are passed through to provide PCI_3P3 and PCI_12P0. +12 VDC from the PCI Express board edge connector also powers a PCI-X Hot Plug Controller (U128), which is used to turn On power to the PCI/PCI-X Bus and monitor over-current/under- voltage fault conditions. When the PEX 8114RDK-F and PEX 8114 are powered on, U128 is enabled to energize the PCI/PCI-X Bus. The 20-pin ATX header is intended for use when PCI/PCI-X Bus power demands are heavy, requiring an external ATX power supply. When an ATX power supply is plugged into this header, on-board PCI/PCI-X voltage generation and delivery is automatically disabled – no additional switch/jumper settings are needed. The ATX supply’s ENABLE# pin (pin 14) is used such that the external ATX supply is intended to be switched On at all times, but does not deliver power to the PEX 8114RDK-F until the PEX 8114RDK-F and PEX 8114 are both fully powered up.

Figure 6 illustrates the PEX 8114RDK-F board and component placement.

Figure 6. PEX 8114RDK-F Component Placement (Primary Component Side)

PEX 8114RDK-F Hardware Reference Manual, Version 4.2 © 2008 PLX Technology, Inc. All Rights Reserved. 11 4.1 Monitoring Point, LED Indicator, and Control Summary This section summarizes the PEX 8114RDK-F interfaces that are used for monitoring, indicating, and controlling PEX 8114 performance.

4.1.1 Monitoring Points

Table 3. PEX 8114RDK-F Monitoring Points

Footprint/ Silkscreen Function Label Test Point via at this footprint can be used to monitor PEX 8114_1P0_CORE F3 voltage to the PEX 8114. Test Point via at this footprint can be used to monitor PEX 8114_VTT voltage F9 to the PEX 8114. F10 Test Point via at this footprint can be used to monitor V3.3 voltage to the PEX 8114. Eight ground posts, scattered around the PEX 8114RDK-F, that provide probe GND reference points. Test Point via at this footprint can be used to monitor PEX 8114_1P0A voltage L1 to the PEX 8114. L2 Test Point via at this footprint can be used to monitor V3.3A voltage to the PEX 8114. P16 PCI/PCI-X Bus power can be monitored at this header. All PCI/PCI-X signals have a clearly labeled Test Point Via (TPV), to allow scope

probing. (Refer to Figure 5 and Section 8)

Table 4. PEX 8114RDK-F LED Indicators Location/ Color Function Silkscreen Label Turned On when PERST# to PEX 8114 is active (asserted). Momentarily DS3 Red blinks On when the PEX 8114RDK-F is first powered up. DS6, DS2, PEX_LANE_GOOD[3:0]# status indicators for Lanes 3, 2, 1, or 0, Green DS4, DS5 respectively. Turned On when the associated lane is active. DS7 Green Power Good indicator. Turned On when PCI/PCI-X Bus power is good. Turned On when the PEX 8114RDK-F is receiving +3.3 VDC, but the DS8 Red Power Sequencer is turned Off. DS9 Green Power Good indicator. Turned On when PEX 8114 power is good. DS11, DS12, Green PCI/PCI-X slot active indicators for Slots 0, 1, 2, and 3, respectively. DS13, DS14 STRAP_ARB Strapping ball status indicator. Turned On when SW9, pin 4 is DS15 Green Open. (Refer to Section 3.4, "Strapping Switches – SW9 and SW10.”) STRAP_TRAN Strapping ball status indicator. Turned On when SW9, pin 3 DS16 Green is Open. (Refer to Section 3.4, "Strapping Switches – SW9 and SW10.”) STRAP PCLK-FDBK Strapping ball status indicator. Turned On when SW9, DS17 Green pin 2 is Open. (Refer to Section 3.4, "Strapping Switches – SW9 and SW10.”) STRAP_PLL_BYPASS# Strapping ball status indicator. Turned On when DS18 Green SW9, pin 1 is Closed. (Refer to Section 3.4, "Strapping Switches – SW9 and SW10.”) DS19 Green Turned on when the PEX 8114 is operating in PCI-X mode at 50MHz. DS20 Green Turned on when the PEX 8114 is operating in PCI-X mode at 66MHz. DS21 Green Turned on when the PEX 8114 is operating in PCI-X mode at 100MHz. DS22 Green Turned on when the PEX 8114 is operating in PCI-X mode at 133MHz. DS23 Green Turned on when the PEX 8114 is operating in PCI mode at 50MHz. DS24 Green Turned on when the PEX 8114 is operating in PCI mode at 66MHz. DS25 Green Turned on when the PEX 8114 is operating in PCI mode at 25MHz. DS26 Green Turned on when the PEX 8114 is operating in PCI mode at 33MHz.

PEX 8114RDK-F Hardware Reference Manual, Version 4.2 © 2008 PLX Technology, Inc. All Rights Reserved. 13 4.1.3 Controls Table 5. PEX 8114RDK-F Controls Location/ Function Silkscreen Label SW7 • Manual PERST# to the PEX 8114. Momentary SPST pushbutton control. • Manual initiation of the PEX 8114 power-up sequence. Momentary SPST SW8 pushbutton control. • DIP switch control of the PEX 8114 Strapping balls. (Refer to Section 3.4, SW9 "Strapping Switches – SW9 and SW10.”) • DIP switch control of the PCI/PCI-X Clock Frequency Strapping balls SW10 to the PEX 8114. (Refer to Section 3.4, "Strapping Switches – SW9 and SW10.”) • PEX 8114 VTT voltage is jumper-selectable and can be fixed at +1.5 VDC JP7, R91 (jumper JP7, pins 1 and 2), or adjustable by way of a potentiometer (jumper JP7, pins 2 and 3 and potentiometer R91). JP14 • Jumper selection to select serial EEPROM present (assert EE_PR#).

JP15, JP16 • Jumper selection to select a 4-, 2-, or 1-slot PCI/PCI-X Bus. • Jumper must be across pins 1 and 2 for standard operation. When the jumper is across pins 2 and 3, access is provided JP18 • to test fixtures for measuring PCI/PCI-X timing parameters. (Refer to Section 8, Sheet 8.)

4.2.1 Trace Routing Design Rules The characteristic trace impedances are within PCI Express Base Specification, Revision 1.0a-defined spec (100 Ohm ±5%) for differential, and within the PCI-X Electrical and Mechanical Addendum to the PCI Local Bus Specification, r2.0a-defined spec (57 Ohm ±5%) for single-ended.

4.2.2 Power Decoupling Power decoupling is provided by two means – plane capacitance (provided by the PCB stackup) and discrete decoupling capacitors. Plane capacitance filters noise above approximately 100MHz. The footprints for the discrete decoupling capacitors are designed such that the inductance between the pad and plane is reduced by careful via placement. (Refer to Figure 7.)

Figure 7. Decoupling Capacitor Footprints

PEX 8114RDK-F Hardware Reference Manual, Version 4.2 © 2008 PLX Technology, Inc. All Rights Reserved. 15 4.2.3 PCB Layer Stackup The PEX 8114RDK-F is a 10-layer, 63-mil thick PCB, as illustrated in Figure 8. The target signal impedance for all routing layers is 57 Ohm ±5% single-ended impedance and 100 Ohm ±5% differential. This PCB stackup was chosen for the following reasons: Power/ground plane arrangement provides capacitance to filter supply voltage noise above 100MHz Differential pair routing layers and plane layers arrangement provides shielding for the PCI Express signals

SOLDERMASK

L1, SIGNAL 1

Controlled Impedance microstripline PREPREG

L2, GROUND

LAMINATE

Controlled Impedance stripline L3, SIGNAL 2

PREPREG

L4, V3.3

High Frequency V3.3 Decoupling LAMINATE

L5, GROUND

PREPREG

L6, SIGNAL 3 Controlled Impedance stripline

LAMINATE

L7, GROUND

PREPREG

L8, SIGNAL 4 Controlled Impedance stripline

LAMINATE

L9, GROUND

Controlled Impedance microstripline PREPREG

L10, SIGNAL 5

SOLDERMASK

Figure 8. PEX 8114RDK-F 10-Layer PCB Stackup

This section provides the PCI/PCI-X (Table 6) and PCI Express (Table 7) signal trace netlengths.

Table 6. PCI/PCI-X Signal Trace Netlengths

PEX 8114 2nd 1st to 2nd PEX 8114 to to 1st Q-Switches PEX 8114 Signal Q-Switch Q-Switches 2nd Q-Switch Q-Switches to End to End (S1_ADxx) Q-Switches (ADxx) (S2_ADxx) AD0 1966 200 629 2795 200 935 3930 AD1 1853 200 658 2711 200 860 3771 AD2 2016 200 635 2851 200 994 4045 AD3 1909 200 626 2735 200 852 3787 AD4 2088 200 645 2933 200 848 3981 AD5 1995 200 625 2820 200 866 3886 AD6 2107 200 633 2940 200 849 3989 AD7 1986 200 666 2852 200 904 3956 AD8 1668 200 690 2558 200 919 3677 AD9 2433 200 751 3384 200 900 4484 AD10 1971 200 769 2940 200 900 4040 AD11 2384 200 678 3262 200 861 4323 AD12 1923 200 652 2775 200 877 3852 AD13 2401 200 654 3255 200 871 4326 AD14 2005 200 632 2837 200 853 3890 AD15 2391 200 612 3203 200 830 4233 AD16 2253 200 632 3085 200 836 4121 AD17 2230 200 689 3119 200 908 4227 AD18 2412 200 679 3291 200 892 4383 AD19 2136 200 743 3079 200 967 4246 AD20 2450 200 737 3387 200 877 4464 AD21 2307 200 1058 3565 200 992 4757 AD22 2281 200 721 3202 200 1151 4553 AD23 2286 200 680 3166 200 1084 4450 AD24 2506 200 646 3352 200 859 4411 AD25 2457 200 928 3585 200 877 4662 AD26 2551 200 647 3398 200 1220 4818 AD27 2435 200 645 3280 200 1195 4675 AD28 2661 200 639 3500 200 850 4550 AD29 2516 200 704 3420 200 923 4543 AD30 2792 200 709 3701 200 906 4807 AD31 2613 200 722 3535 200 1044 4779 AD32 3430 200 728 4358 200 978 5536 AD33 3594 200 716 4510 200 874 5584 AD34 3331 200 663 4194 200 866 5260 AD35 3496 200 640 4336 200 874 5410 AD36 3288 200 642 4130 200 909 5239 AD37 3424 200 633 4257 200 845 5302 AD38 3216 200 622 4038 200 835 5073 AD39 3303 200 637 4140 200 856 5196

PEX 8114RDK-F Hardware Reference Manual, Version 4.2 © 2008 PLX Technology, Inc. All Rights Reserved. 17 PEX 8114 2nd 1st to 2nd PEX 8114 to to 1st Q-Switches PEX 8114 Signal Q-Switch Q-Switches 2nd Q-Switch Q-Switches to End to End (S1_ADxx) Q-Switches (ADxx) (S2_ADxx) AD40 3228 200 632 4060 200 879 5139 AD41 3379 200 670 4249 200 877 5326 AD42 3144 200 723 4067 200 881 5148 AD43 3277 200 701 4178 200 906 5284 AD44 3133 200 696 4029 200 876 5105 AD45 3241 200 627 4068 200 849 5117 AD46 3058 200 648 3906 200 833 4939 AD47 3140 200 635 3975 200 850 5025 AD48 2981 200 649 3830 200 852 4882 AD49 3140 200 672 4012 200 872 5084 AD50 2876 200 639 3715 200 839 4754 AD51 3012 200 721 3933 200 881 5014 AD52 2692 200 641 3533 200 850 4583 AD53 2818 200 700 3718 200 909 4827 AD54 2726 200 857 3783 200 966 4949 AD55 2751 200 873 3824 200 1042 5066 AD56 2696 200 802 3698 200 921 4819 AD57 2675 200 749 3624 200 901 4725 AD58 2545 200 677 3422 200 892 4514 AD59 2574 200 670 3444 200 871 4515 AD60 2504 200 655 3359 200 876 4435 AD61 2543 200 623 3366 200 850 4416 pAD62 490 TVAL length AD62+ 2466 200 605 3271 200 831 4302 pAD62 AD63 2593 200 632 3425 200 840 4465 CBE0# 2307 200 686 3193 200 850 4243 CBE1# 2037 200 628 2865 200 863 3928 CBE2# 2162 200 662 3024 200 900 4124 CBE3# 2354 200 651 3205 200 854 4259 CBE4# 2581 200 644 3425 200 872 4497 CBE5# 2171 200 691 3062 200 863 4125 CBE6# 2501 200 637 3338 200 873 4411 CBE7# 2119 200 705 3024 200 854 4078 PAR 2069 200 646 2915 200 877 3992 REQ64# 2248 200 732 3180 200 870 4250 ACK64# 2126 200 673 2999 200 889 4088 PAR64 2096 200 625 2921 200 862 3983 MIN 1668 2558 3677 MAX 3594 4510 5584 DELTA 1926 1952 1907

PEX 8114RDK-F Hardware Reference Manual, Version 4.2 18 © 2008 PLX Technology, Inc. All Rights Reserved. PEX 8114 2nd 1st to 2nd PEX 8114 to to 1st Q-Switches PEX 8114 Signal Q-Switch Q-Switches 2nd Q-Switch Q-Switches to End to End (S1_ADxx) Q-Switches (ADxx) (S2_ADxx) FRAME# 2647 200 627 3474 200 867 4541 IRDY# 2425 200 635 3260 200 856 4316 TRDY# 2370 200 627 3197 200 856 4253 STOP# 2320 200 735 3255 200 859 4314 DEVSEL# 2309 200 626 3135 200 866 4201 PERR# 2113 200 743 3056 200 956 4212 SERR# 2024 200 675 2899 200 885 3984 MIN 2024 2899 3984 MAX 2647 3474 4541 DELTA 623 575 557 PCI_REQ#_ REQ#_ R16 TOTAL REQ0# REQ0# REQ0# 211 60 5268 5539 MIN 3650 REQx# MAX 5539 REQ1# 3650 3650 DELTA 1889 REQ2# 5405 5405 REQ3# 5055 5055 PCI_GNT#_ GNT#_ R38 GNT0# GNT0# GNT0# 685 60 3675 4420 PCI_GNT1# R17 GNT1# GNT1# 342 60 4009 4411 PCI_GNT2# R18 GNT2# GNT2# 314 60 4595 4969 PCI_GNT3# R19 GNT3# GNT3# 262 60 4939 5261 PCLKs PCI_CLKO0 R32 pPCLK TOTAL CLKO0 417 60 5406 5883 MIN 5816 PCI_CLKO1 R30 pPCLK1 MAX 5968 CLKO1 374 60 5382 5816 DELTA 152 PCI_CLKO2 R28 pPCLK2 CLKO2 435 60 5473 5968 PCI_CLKO3 R25 pPCLK3 CLKO3 143 60 5758 5961 PCLK_OUT R109 PCLK_IN

PCLK-FDBK 2951 60 2950 5961

PEX 8114 2nd 1st to 2nd PEX 8114 to to 1st Q-Switches PEX 8114 Signal Q-Switch Q-Switches 2nd Q-Switch Q-Switches to End to End (S1_ADxx) Q-Switches (ADxx) (S2_ADxx) PERn3 4062 PERp3 4066 DELTA 4

PERn2 4096 PERp2 4099 DELTA 3

PERn1 4127 PERp1 4129 DELTA 2

PERn0 4175 PERp0 4168 DELTA 7

PETxx CAP PB_PETxx TOTAL PETn3 339 40 3582 3961 PETp3 336 40 3584 3960 DELTA 3 2 1

PETn2 331 40 3604 3975 PETp2 328 40 3609 3977 DELTA 3 5 2

PETn1 325 40 3634 3999 PETp1 323 40 3638 4001 DELTA 2 4 2

PETn0 318 40 3681 4039 PETp0 317 40 3679 4036 DELTA 1 2 3

REFCLKn 324 40 3681 4045 REFCLKp 326 40 3678 4044 DELTA 2 3 1

1. When I turn On the computer, it fails to boot. Not even the monitor turns On. Power to the PCI/PCI-X Bus cannot be turned On. Check whether LED DS11 is turned On – if it is not On, then the +3.3 VDC for the PCI/PCI-X Bus is not present. This voltage is required to pull-up the upper 32-bit lines of the PCI/PCI-X Bus; otherwise, these lines have no valid value and the PEX 8114 gets hung. 2. The PCI/PCI-X Bus Clock Frequency switch settings (SW10) and LED indicators (DS19 through DS26) indicate one clock frequency, but when I probe the bus, it is operating at a lower frequency. The PCI/PCI-X Bus Clock Frequency switch settings and LED indicators set/indicate the maximum possible clock frequency. However, an add-in board on the bus can advertise that it must operate at a lower clock frequency. Should this occur, the PEX 8114 adjusts the clock frequency to accommodate the lowest common denominator.

The following is a list of documentation to provide further details. PLX Technology, Inc. 870 W Maude Avenue, Sunnyvale, CA 94085 USA Tel: 800 759-3735 or 408 774-9060, Fax: 408 774-2169, http://www.plxtech.com PEX 8114BC/BD Data Book, Version 3.1 or higher PEX 8114BD Errata, Revision 1.0 or higher PEX 8114BB Design Checklist Application Note, Version 1.0 or higher PEX 8114RDK-R Hardware Reference Manual PCI Special Interest Group (PCI-SIG) 3855 SW 153rd Drive, Beaverton, OR 97006 USA Tel: 503 619-0569, Fax: 503 644-6708, http://www.pcisig.com PCI Local Bus Specification, Revision 2.3 PCI Local Bus Specification, Revision 3.0 PCI Express Card Electromechanical (CEM) Specification, Revision 1.1 PCI to PCI Bridge Architecture Specification, Revision 1.1 PCI Bus Power Management Interface Specification, Revision 1.2 PCI Express Base Specification, Revision 1.0a PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0 PCI-X Addendum to PCI Local Bus Specification, Revision 1.0b PCI-X Addendum to PCI Local Bus Specification, Revision 2.0a PCI-X Electrical and Mechanical Addendum to the PCI Local Bus Specification, Revision 2.0a

This section replicates the PEX 8114RDK-F Bill of Materials and Schematics.

Mfgr Package Component Dist Item # Qty Mfgr Des. Dist. Part Part # Type Designator(s) Part # SURFACE MOUNT COMPONENTS C1, C2, C130, C176, C197, C65, C66, C67, C68, C320, C321, C322, C323, C324, C325, C326, C327, C328, C329, C330, C331, C332, C345, C347, C348, C349, C350, C351, C352, C353, C354, C355, CAP, SMD, C356, C357, C358, C359, C0603C1 399- CER, 0.1UF, C360, C361, C362, C363, 1 78 Kemet 04K3RAC SMT, 0603 Digi-Key 1281- 0.1uF 25V, X7R, C364, C365, C366, C367, TU 1-ND 0603 C368, C369, C370, C371, C372, C373, C374, C375, C376, C377, C378, C379, C380, C381, C382, C383, C384, C385, C386, C387, C388, C389, C390, C391, C392, C393, C394, C395, C396, C397, C398, C399, C400, C401 CAP .10UF C0402C1 399- 10V C4, C5, C6, C7, C8, C9, 2 10 Kemet 04K8PAC SMT, 0402 Digi-Key 3027- 0.1uF CERAMIC C10, C11, C12, C13 TU 2-ND X5R 0402 CAP C3, C196, C333, C334, C0603C1 399- 0.01UF, 50V C335, C336, C337, C338, 3 14 Kemet 03K5RAC SMT, 0603 Digi-Key 1091- 0.01uF CERAMIC C339, C340, C341, C342, TU 1-ND X7R 0603 C343, C344 CAP 1UF ECJ- PCC21 10V 4 1 Panasonic 1VB1A10 SMT, 0603 C81 Digi-Key 74CT- 1uF CERAMIC 5K ND 0603 X5R CAP, C0805C1 CERAMIC, 5 1 Kemet SMT, 0805 C24 1uF 05K4RAC 1UF, 16V, 10%, X7R CAP ECJ- PCC17 1000PF 50V C42, C73, C74, C79, C80, 6 7 Panasonic 1VB1H10 SMT, 0603 Digi-Key 72CT- 1000pF CERAMIC C99, C134 2K ND X7R 0603 Cap, C279, C280, C281, C283, Ceramic, C284, C285, C286, C287, 399- C0402C1 7 18 Kemet 1000pF, SMT, 0402 C288, C289, C290, C291, Digi-Key 1031- 1000pF 02K3RAC 25V, 10%, C292, C293, C294, C295, 1-ND X7R C296, C298 CAP, SMD, 293D475 Vishay ELECT, Bcase- 8 1 X0016B2 C25 4.7uF Sprague 4.7UF 16V, 3528eia T 20% CAP, SMD, 293D106 Vishay ELECT, Bcase- 9 1 X0016B2 C26 10uF Sprague 10UF, 16V, 3528eia T B CASE C41, C45, C46, C49, C50, C51, C52, C53, C54, C55, C56, C57, C58, C59, C60, CAP 10UF C61, C63, C64, C86, C87, ECJ- PCC22 16V C88, C89, C90, C91, C92, 10 46 Panasonic 3YB1C10 SMT, 1206 Digi-Key 27CT- 10uF CERAMIC C93, C94, C95, C96, C97, 6M ND X5R 1206 C98, C100, C101, C102, C103, C104, C105, C106, C107, C108, C109, C110, C111, C112, C113, C114

PEX 8114RDK-F Hardware Reference Manual, Version 4.2 © 2008 PLX Technology, Inc. All Rights Reserved. 23 Mfgr Package Component Dist Item # Qty Mfgr Des. Dist. Part Part # Type Designator(s) Part # CAP CER 47UF 16V X5R 20% 445- C5750X5 SMT, 2220, 11 2 TDK 2220 C82, C83 Digi-Key 1452- 47uF R1C476M LoVolt LOVOLT 1-ND FOOTPRIN T CAP ECJ- PCC17 2200PF 50V 12 2 Panasonic 1VB1H22 SMT, 0603 C129, C136 Digi-Key 76CT- 2200pF CERAMIC 2K ND X7R 0603 CAP ECJ- PCC17 1500PF 50V 13 2 Panasonic 1VB1H15 SMT, 0603 C133, C135 Digi-Key 74CT- 1500pF CERAMIC 2K ND X7R 0603 CAP ECJ- PCC17 3300PF 50V 14 1 Panasonic 1VB1H33 SMT, 0603 C137 Digi-Key 78CT- 3300pF CERAMIC 2K ND X7R 0603 CAP, SMD, C300, C301, C302, C303, ECJ- CER, C304, C305, C306, C307, PCC21 15 19 Panasonic 0EB1C22 22000PF, SMT, 0402 C308, C309, C310, C311, Digi-Key 38CT- 0.022uF 3K 16V, 10%, C312, C313, C315, C316, ND X7R, 0402 C317, C318, C319 CAP 100PF ECJ- PCC17 25V 16 1 Panasonic 0EB1E10 SMT, 0402 C405 Digi-Key 02CT- 100pF CERAMIC 1K ND X7R 0402 CAP .033UF ECJ- PCC22 50V 17 3 Panasonic 1VB1H33 SMT, 0603 C406, C407, C408 Digi-Key 84CT- 0.033uF CERAMIC 3K ND X7R 0603 CAP C0402C1 399- CERAMIC 18 1 Kemet 00J5GAC SMT, 0402 C413 Digi-Key 1011- 10 pF 10PF 50V TU 1-ND NP0 0402 DS2, DS4, DS5, DS6, DS7, DS9, DS11, DS12, LED DS13, DS14, DS15, LNJ308G GREEN SS P521C 19 22 Panasonic SMT, 0603 DS16, DS17, DS18, Digi-Key Green 8LRA TYPE LOW T-ND DS19, DS20, DS21, CUR SMD DS22, DS23, DS24, DS25, DS26 LED RED HI LNJ208R BRT SS P524C 20 2 Panasonic SMT, 0603 DS3, DS8 Digi-Key RED LED 8ARA TYPE LO T-ND CUR SM DIODE, Schottky, On MBRS120 If=1A, MBRS120 21 1 Semicond SMB D6 T3 Vr=20V, T3 uctor Vf=0.55V max PCI/PCI- CONN, PCI- X_FEMALE PCI-X, RT-HD3- X 1.0, _STRADDL FM, 22 1 Raycon GT- Female, SM, J13 E- Straddle- 184AECN Straddle- MOUNT_92 mount mount POS Ferrite, 200mA, 120 BLM21A 490- ohm at 100 Ferrite 23 3 MuRata G121SN1 SMT, 0805 L1, L2, L11 Digi-Key 1038- MHz, Bead D 1-ND DCR=0.15o hm IND, 10uH, DCR=0.182 24 2 Sumida CR43-100 ohm, CR43 L3, L5 10uH I=1.04A, 20%

PEX 8114RDK-F Hardware Reference Manual, Version 4.2 24 © 2008 PLX Technology, Inc. All Rights Reserved. Mfgr Package Component Dist Item # Qty Mfgr Des. Dist. Part Part # Type Designator(s) Part # MOSFET, Internatio N-CHAN, IRF747 25 2 nal IRF7470 10A, SO8 Q2, Q3 Digi-Key IRF7470 0-ND Rectifier Rds=13 mohm MOSFET, FDN339A N-CHAN, 34C01 FDN339A 26 3 Fairchild SuperSOT-3 Q5, Q6, Q7 Newark N 3A, Rds=50 38 N mohm Fairchild IC, N- 27 1 Semicond BSS138 channel SOT-23 Q9 BSS138 uctor MOSFET MMBT NPN, GPSS, MMBT39 3904L MMBT39 28 1 ON Semi MMBT3904, SOT23-3 Q10 Digi-Key 04LT1 T1OSC 04LT1 SOT23 T-ND RESNET, CTS MF, 5.1 742C0 742-083- 742-CTS- 29 2 Resistor KOHM NIL RN1, RN2 Digi-Key 83512J 5.1K 512-J RN-8 Products 5%, CT-ND ISOLATED RESNET, CTS MF, 8.2 R345, R346, R347, R348, 742C0 742-083- 742-CTS- 30 12 Resistor KOHM NIL R353, R354, R355, R356, Digi-Key 83822J 8.2K 822-J RN-8 Products 5%, R361, R363, R365, R545 CT-ND ISOLATED RES, VAR, 50 KOHM 3224W-1- MULTI- BOURNS- 31 1 Bourns R91 Arrow 50K 503E TURN, 4mm 3224W SMD, TOP ADJ R4, R5, R6, R7, R8, R16, RES 0.0 R25, R28, R30, R32, R62, 9C06031 311- OHM 1/10W R63, R84, R85, R86, R87, 32 25 Yageo A0R00JL SMT, 0603 Digi-Key 0.0GC 0 5% 0603 R109, R146, R159, R160, HFT T-ND SMD R168, R253, R341, R343, R574 RES ERJ- CURRENT P5.0T 33 2 Panasonic M1WSJ5 SEN .005 SMT, 2512 R164, R165 Digi-Key 0.005 CT-ND M0U OHM 1W 0.5% RES 36 ERJ- OHM 1/10W P36GC 34 5 Panasonic 3GEYJ36 SMT, 0603 R17, R18, R19, R27, R38 Digi-Key 36 5% 0603 T-ND 0V SMD R12, R13, R15, R23, R24, RES 390 R39, R94, R107, R108, ERJ- OHM 1/10W R556, R557, R558, R559, P390G 35 25 Panasonic 3GEYJ39 SMT, 0603 Digi-Key 390 5% 0603 R560, R561, R562, R563, CT-ND 1V SMD R564, R565, R566, R567, R569, R570, R571, R572 RES 1.0K ERJ- P1.0K OHM 1/10W 36 4 Panasonic 3GEYJ10 SMT, 0603 R9, R20, R21, R22 Digi-Key GCT- 1K 5% 0603 2V ND SMD RES 1.00K ERJ- P1.00K OHM 1/16W 37 2 Panasonic 2RKF100 SMT, 0402 R110, R111 Digi-Key LCT- 1.00K 1% 0402 1X ND SMD RES 1.00K ERJ- P1.00K OHM 1/16W 38 1 Panasonic 3EKF100 SMT, 0603 R101 Digi-Key HCT- 1.00K 1% 0603 1V ND SMD RES 1.47K ERJ- P1.47K OHM 1/16W 39 1 Panasonic 3EKF147 SMT, 0603 R90 Digi-Key HCT- 1.47K 1% 0603 1V ND SMD

PEX 8114RDK-F Hardware Reference Manual, Version 4.2 © 2008 PLX Technology, Inc. All Rights Reserved. 25 Mfgr Package Component Dist Item # Qty Mfgr Des. Dist. Part Part # Type Designator(s) Part # RES 1.5K ERJ- P1.5K OHM 1/10W 40 1 Panasonic 3GEYJ15 SMT, 0603 R33 Digi-Key GCT- 1.5K 5% 0603 2V ND SMD RES 3.16K ERJ- P3.16K OHM 1/16W 41 2 Panasonic 3EKF316 SMT, 0603 R100, R106 Digi-Key HCT- 3.16K 1% 0603 1V ND SMD RES 3.3K R46, R48, R157, R158, ERJ- P3.3K OHM 1/10W R161, R162, R163, R170, 42 13 Panasonic 3GEYJ33 SMT, 0603 Digi-Key GCT- 3.3K 5% 0603 R255, R534, R535, 2V ND SMD R536, R537 RES, CF, ERJ- P5.1K 5.1K OHM, 43 1 Panasonic 3GEYJ51 SMT, 0603 R325 Digi-Key GCT- 5.1K 1/16W, 5%, 2V ND 0603 SMD RES 6.04K ERJ- P6.04K OHM 1/16W 44 1 Panasonic 3EKF604 SMT, 0603 R166 Digi-Key HCT- 6.04K 1% 0603 1V ND SMD RES 7.50K ERJ- P7.50K OHM 1/16W 45 3 Panasonic 3EKF750 SMT, 0603 R93, R98, R104 Digi-Key HCT- 7.50K 1% 0603 1V ND SMD RES, 8.2K ERJ- OHM, R349, R350, R351, R352, P8.2KJ 46 8 Panasonic 2GEJ822 SMT, 0402 Digi-Key 8.2K 1/16W, 5% R357, R358, R359, R360 CT-ND X 0402 SMD RES 9.09K ERJ- P9.09K OHM 1/16W 47 1 Panasonic 3EKF909 SMT, 0603 R102 Digi-Key HCT- 9.09K 1% 0603 1V ND SMD RES 10K ERJ- OHM 1/10W P10KG 48 3 Panasonic 3GEYJ10 SMT, 0603 R1, R2, R40 Digi-Key 10K 5% 0603 CT-ND 3V SMD RES 10.0K MCR03E RHM1 OHM 1/10W 49 2 Rohm ZPFX100 SMT, 0603 R14, R26 Digi-Key 0.0KH 10.0K 1% 0603 2 CT-ND SMD RES 12.4K ERJ- P12.4K OHM 1/16W 50 1 Panasonic 3EKF124 SMT, 0603 R89 Digi-Key HCT- 12.4K 1% 0603 2V ND SMD RES 18K ERJ- OHM 1/10W P18KG 51 1 Panasonic 3GEYJ18 SMT, 0603 R546 Digi-Key 18K 5% 0603 CT-ND 3V SMD RES 28.0K ERJ- P28.0K OHM 1/16W 52 1 Panasonic 3EKF280 SMT, 0603 R105 Digi-Key HCT- 28.0K 1% 0603 2V ND SMD RES 49.9K ERJ- P49.9K OHM 1/16W 53 1 Panasonic 3EKF499 SMT, 0603 R103 Digi-Key HCT- 49.9K 1% 0603 2V ND SMD RES 56K ERJ- OHM 1/10W P56KG 54 1 Panasonic 3GEYJ56 SMT, 0603 R11 Digi-Key 56K 5% 0603 CT-ND 3V SMD RES 56K ERJ- OHM 1/16W P56KJ 55 1 Panasonic 2GEJ563 SMT, 0402 R364 Digi-Key 56K 5% 0402 CT-ND X SMD RES 75K ERJ- OHM 1/10W P75KG 56 1 Panasonic 3GEYJ75 SMT, 0603 R544 Digi-Key 75K 5% 0603 CT-ND 3V SMD ERJ- Res. 1/16W, P84.5K 57 1 Panasonic 3EKF845 84.5K ohm, SMT, 0603 R29 Digi-Key HCT- 84.5K 2V 1% ND

PEX 8114RDK-F Hardware Reference Manual, Version 4.2 26 © 2008 PLX Technology, Inc. All Rights Reserved. Mfgr Package Component Dist Item # Qty Mfgr Des. Dist. Part Part # Type Designator(s) Part # SWITCH TACT 6MM SW416 58 2 Omron B3S-1002 SW7, SW8 Digi-Key B3S-1002 SMD MOM -ND 230GF IC, PCI Express- PCIX bridge, PLX PEX8114- Forward/Rev 59 1 Technolog PBGA256 U1 PEX 8114 BD13BI erse, single y x4 port, PCIX 133 MHz DC/DC converter, Linear Inverting, - LT1931E LT1931E 60 1 Technolog 12V at 150 SOT23-5 U8 S5 S5 y mA, Fsw=1.2MH z IC, V-REG, MIC4930 MIC4930 61 1 Micrel 3A, ADJ, SPak5 U9 Arrow 0BR 0 SPak5 IC, V-REG, MAX1806 500 mA, 62 1 Maxim uMAX8 U13 MAX1806 EUA15 ADJ 0.8- 4.5V IC, Power ISL6123I 63 1 Intersil Sequencer, QFN24 U14 Arrow ISL6123 R 4 channel IC, Reset controller, MAX6412 2.9V 64 1 Maxim SOT23-5 U15 MAX6412 UK29-T threshold, Adj. reset timeout IC, Reset controller, MAX6414 2.9V 65 1 Maxim SOT23-5 U16 MAX6414 UK29-T threshold, Adj. reset timeout IC, Bus U98, U99, U100, U101, Switch, 8 U102, U103, U104, U105, Bit, Ron=4 U106, U107, U108, U109, IDTQS3V IDTQS3V 66 28 IDT ohm, QSOP20 U110, U111, U112, U113, H245Q H245Q Cio=4pF, U114, U115, U116, U117, BW=500 U118, U119, U120, U121, MHz U122, U123, U124, U125 IC, DC/DC, Non- Isolated, 10- 14 VDC In, Power- YNS12S1 16A, 0.75- YNS12S1 67 1 U127 One 6-D 5.5 VDC 6-D Out, Sense, On/Off active low, SMD IC, Hot Plug HIP1011A 68 1 Intersil Controller, SOIC16 U128 Arrow HIP1011A CB PCI IC, Analog 69 1 Fairchild FSA1256 Switch, Dual uPAK8 U133 FSA1256 SPST, NO NC7SZ04 IC, NOT NC7SZ04 70 4 Fairchild SC70-5 U136, U137, U138, U139 P5X GATE P5X On MC14556 IC, Dual 2:4 MC14556 71 1 Semicond SOIC16 U140 BD Demux BD uctor

PEX 8114RDK-F Hardware Reference Manual, Version 4.2 © 2008 PLX Technology, Inc. All Rights Reserved. 27 Mfgr Package Component Dist Item # Qty Mfgr Des. Dist. Part Part # Type Designator(s) Part # IC GATE NC7SZ NC7SZ08 AND 2- NC7SZ08 72 1 Fairchild SC70-5 U141 Digi-Key 08P5X P5X INPUT UHS P5X CT-ND SC70-5 THROUGH-HOLE COMPONENTS CONN HEADER A2626 JTAG 100 1 Amp 103308-1 LOPRO 0.1" 2x5 JP1 Digi-Key 7-ND Header STR 10POS 15AU HEADER, 1x3 929400- JUMPER 101 2 3M VERTICAL, . SIP-3 JP7, JP18 01-36 3 1in THRU- HOLE HEADER, 1x2 929400 929400- 102 3 3M VERTICAL, . SIP-2 JP14, JP15, JP16 Digi-Key -01-36- JUMPER 01-36 1in THRU- ND HOLE CONN, PCI- PCI/PCI-X_ X 1.0, FEMALE_T PCI-X, 145165 103 3 Amp 145165-4 Female, HRU- J10, J11, J12 Digi-Key FM, Thru- -4-ND Thru-hole, HOLE_92P hole VERT. OS Header, 39-29- ATX, 20 ATX_20 104 1 Molex ATX20_ST P16 9202 position, ST ST dual-row SWITCH 4POS DIP GH110 105 2 Grayhill 76SB04 DIP8 SW9, SW10 Digi-Key SW DIP-4 EXT ROCK 4-ND UNSEALD TERM, PIN, 76201- PRESS- TP13, TP14, TP15, TP16, 106 8 FCI Stakepin 023 FIT, .025inS TP17, TP18, TP19, TP22 q, .230Lng Socket, 210-93- EEPROM EEPROM, ED600 107 1 Mill-Max 308-41- DIP8 U65 Digi-Key 8 Pin DIP DIP8, Thru- 00-ND 001000 Socket hole MANUALLY INSERTED COMPONENTS AT256 AT25640 IC SRL EE 40A- AT25640 200 1 Atmel A-10PI- 64K 2.7V DIP-8 U65 Digi-Key 10PI- A 2.7 8DIP 2.7-ND SHUNT LP JP7, JP14, JP15, A2624 201 5 Amp 881545-2 W/HANDLE Digi-Key JP16, JP18 2-ND 2 POS 30AU MISCELLANEOUS COMPONENTS Bracket, 300 1 Keystone 9203 PCI, blank PEX 8114 PLX Forward 90-0052- 301 1 Technolog Bridge RDK 300-A y PCB Rev 300 PARTS THAT SHOULD NOT BE ASSEMBLED FUSE, very fast acting, 400 3 Littelfuse 0433 1.75 SMT, 1206 F3, F9, F10 NL 1.75A, 63V, 1206 RES 0.0 9C06031 311- OHM 1/10W R167, R254, R340, 401 5 Yageo A0R00JL SMT, 0603 Digi-Key 0.0GC NL 5% 0603 R342, R554 HFT T-ND SMD RES 0.0 9C08052 311- OHM 1/8W 402 1 Yageo A0R00JL SMT, 0805 R553 Digi-Key 0.0AC NL 5% 0805 HFT T-ND SMD

PEX 8114RDK-F Hardware Reference Manual, Version 4.2 28 © 2008 PLX Technology, Inc. All Rights Reserved. Mfgr Package Component Dist Item # Qty Mfgr Des. Dist. Part Part # Type Designator(s) Part # IC, zero delay clock buffer, 25-134MHz, PI6C2401 403 1 Pericom PLL bypass SOIC-8 U130 PI6C2401 W capable, source termination on-chip IC, Delay Line, Adjustable, VDA- VDA- 404 1 Elmec 0-7.5ns, VDA-8P U129 ES7R5 ES7R5 0.5ns steps, Fmax= 133 MHz

PLX Part # 91-0052-300-B Product Name: PEX 8114RDK-F

J13 PCI/PCI-X SLOT 3 - 66 MHZ

J12 PCI/PCI-X SLOT 2 - 66 MHZ

D D SLOT ISOLATION SWITCHES

J11 PCI/PCI-X SLOT 1 - 100 MHZ

SLOT ISOLATION SWITCHES

J10 PCI/PCI-X SLOT 0 - 133 MHZ

Schematic Table of Contents

Sheet # Title PCI/PCI-X Bus 1 Functional Block Diagram 64 bit, up to CLKO[3:0] 2 Board Layout Information 133 MHz 3 PEX 8114 C 4 PCI Slot 0 PCI Clk C 5 PCI Slot 1 Delay 6 PCI Slot 2 7 PCI Slot 3 8 PCI Termination ATX header EEPROM 9 PCI Power for External 10 PCI Express Connector PCI-X Bus 11 Switches/Indicators Power JTAG PEX 8114 12 Power Interface 13 Power Decoupling Strapping switches PCI-X Power Enable

Bus Power -12 +5 +12 +3.3 8114_PERST# VDC VDC VDC VDC 3.3 1.5 1.0 Voltage On VDC VDC VDC Controller

B Power Up B Sequencer

PERST#_PG X4 PCI REF Express CLK MAN_PERST# PCI-X Bus Voltage PEX 8114 Voltage Regulators Regulators 3P3 to V1.0_CORE_EARLY 12P0 to PCIN12P0 3P3 to VTT_EARLY 12P0 to PCI5P0

Revision History 12P0 3P3 PERST#_CONN Rev. # Date Reason for Revision 000 January 31, 2005 Distributed for Comprehensive Design Review 001February 3, 2005 Results of Comprehensive Design Review PCI Express Connector, X4 A 100 April 2, 2005 PCI Clock schematic page removed. IDSEL assignments A changed. R546, R40, DS9 added. Footprints for U14, C82, C83 changed. Silkscreen labels added. 200October 13, 2005 Modified for PEX8114BA. Distributed for Comprehensive Design Review. PLX Technology, Inc. 201 November 3, 2005 Results of Comprehensive Design Review 870 Maude Avenue 202December 3, 2005 Results of 2nd Comprehensive Design Review Sunnyvale, CA 94085 www.plxtech.com TPV test points added to PCI clock lines. 300 April 6, 2006 Minor layout modifications. Correcting PB_PERST# TitleTitle generation. PEX 8114 Forward Bridge RDK - Functional Block Diagram SizeSize Document Document Number Number Rev Rev C 91-0052-300-A 300

Date:Date:Tuesday, December 18, 2007 Sheet Sheet 113of 5 4 3 2 1 5 4 3 2 1

D 207.95 D

Board = 63 mils Thickness

LAYER STACKUP

SOLDERMASK, Er=3.0, x.x mils L1, SIGNAL 1 PREPREG, Er=4.0, x.x mils L2, GND LAMINATE, Er=4.0, 6.2 mils

L3, SIGNAL 2 PCI_12P0, PCI_N12P0 PREPREG, Er=4.0, x.x mils C L4, V3.3 C LAMINATE, Er=4.0, 6.2 mils

L5, GND PREPREG, Er=4.0, x.x mils L6, SIGNAL 3 PCI_3P3, P-BRIDGE_1P0_CORE LAMINATE, Er=4.0, 6.2 mils

L7, GND PREPREG, Er=4.0, x.x mils L8, SIGNAL 4 PCI_5P0, 3P3, 12P0 LAMINATE, Er=4.0, 6.2 mils

L9, GND 79.30 PREPREG, Er=4.0, x.x mils L10, SIGNAL 5 SOLDERMASK, Er=3.0, x.x mils

57.15

B B PEX 8114 voltages are carried on V3.3, P-BRIDGE_1P0_CORE, and VTT. VTT is carried on a wide trace. 45.01 41.36

33.36

OUTER TRACES 15.25 15.0 WIDTH = 5.0 mils Cu = 1.50 oz Trace Zo = 57 ohm DIFF Trace Zo = 100 ohm 0.00 INNER TRACES

WIDTH = 4.0 mils Cu = 0.50 oz Trace Zo = 57 ohm DIFF Trace Zo = 100 ohm 0.00 90.0 186.5

A A All dimensions in mm.

NL = No Load PLX Technology, Inc. 870 Maude Avenue Sunnyvale, CA 94085 www.plxtech.com

TitleTitle PEX 8114 Forward Bridge RDK - Board Layout Information

SizeSize Document Document Number Number Rev Rev C 91-0052-300-A 300

Date:Date:Tuesday, December 18, 2007 Sheet Sheet 213of 5 4 3 2 1 5 4 3 2 1

V3.3 V3.3 PBRIDGE_1P0_CORE L11 PBRIDGE_1P0_CORE PBRIDGE_VTT V3.3 C197 C196 L2 L1 Ferrite Bead Ferrite Bead Ferrite Bead 0.1uF 0.01uF

0.1uF C1

0.1uF C2 U129 U1 N4 E12 F2 G15 H5 H12 J2 L12 M3 M15 P12 E6 E8 E9 E11 F5 F12 G5 G12 J5 J12 K5 K12 M6 M10 M12 B2 B8 B12 B15 E5 E7 E10 P8 R4 R6 R8 R10 R12 P4 M8 T6 T10 1 IN VCC 8 2 GND OUT 3 4 GND GND 7

5 6 VSSA VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD10 VDD10 VDD10 VDD10 VDD10 VDD10 VDD10 VDD10 VDD10 VDD10 VDD10 VDD10 VDD10 VDD10 VDD10 GND GND VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 D VDA-LS15 TPV1 VDD10S VDD10S VDD10S VDD10S VDD10S VDD10S VDD33A VDD10A D

V3.3 VTT_PEX[0] VTT_PEX[1] AD[63:0] {4,5,8} L14 AD32 PCI_AD[32] AD33 PCI_AD[33] L16 PCLK_OUT N3 K14 AD34 3 2 PCI_CLKO_DLY_FBK PCI_AD[34] R325 K16 AD35 R109 5.1K PLX PEX8114BD-PBGA256 PCI_AD[35] AD36 PCI_AD[36] K13 0 Shunt U130 K15 AD37 PCI_AD[37] AD38 7 VCC AVCC 2 PCI_AD[38] J14 8 J16 AD39 PCLK_IN 1 FB_IN PCI_AD[39] AD40 4 CLK_OUT CLK_IN 1 PCI_AD[40] J13 5 V3.3 J15 AD41 S PCI_AD[41] AD42 6 GND AGND 3 P14 HP_PERST# PCI_AD[42] H14 R14 H16 AD43 PCLK_IN goes to HP_CLKEN# PCI_AD[43] AD44 PI6C2401 N14 HP_PWREN# PCI_AD[44] H13 ball J1 of U1 on R553 Load to 3.3K R158 N13 H15 AD45 NL disable HP_PWRFLT# PCI Express Hot-Plug PCI_AD[45] AD46 M13 HP_PWRLED# PCI_AD[46] G14 this page. PLL T14 G16 AD47 R159 0 HP_ATNLED# PCI_AD[47] AD48 R13 HP_MRL# PCI_AD[48] G13 R160 0 P13 F16 AD49 3.3K R161 HP_PRSNT# PCI_AD[49] AD50 T13 HP_BUTTON# PCI_AD[50] F14 PCI/PCI-X 64-Bit E16 AD51 PCI_AD[51] AD52 Bus Extension PCI_AD[52] F13 E15 AD53 V3.3 PCI_AD[53] AD54 PCI_AD[54] E14 D16 AD55 3.3K R535 PCI_AD[55] AD56 R2 STRAP_TESTMODE[0] PCI_AD[56] E13 3.3K R534 T2 C16 AD57 STRAP_TESTMODE[1] PCI_AD[57] AD58 {11} STRAP_PLL_BYPASS# P3 D15 3.3K R537 STRAP_PLL_BYPASS# PCI_AD[58] AD59 L4 STRAP_CLK_MST PCI_AD[59] B16 3.3K R536 P16 Strapping Pins D14 AD60 STRAP_FWD PCI_AD[60] AD61 {11} STRAP_ARB L5 A16 STRAP_ARB PCI_AD[61] pAD62 {11} STRAP_TRAN P15 C15 pAD62 {8} V3.3 STRAP_TRAN PCI_AD[62] AD63 {11} PCI_SEL100 M4 PCI_SEL100 PCI_AD[63] A15 AD63 {4,5,8} CBE#[7:0] {4,5,8} B14 CBE#4 PCI_C/BE[4]# CBE#5 PCI_C/BE[5]# D13 C EE_PR# CBE#6 C L13 EE_PR# PCI_C/BE[6]# A14 EE_SK R4 0 PB_EE_SK M14 C13 CBE#7 EE_DI R5 0 PB_EE_DI EE_SK PCI_C/BE[7]# M16 C14 pPAR64 {4,5,8} R1 R2 R157 EE_DO R6 0 PB_EE_DO EE_DI PCI_PAR64 N16 D12 pREQ64# {4,5,8} 10K 10K EE_CS# R7 0 PB_EE_CS# EE_DO PCI_REQ64# 3.3K N15 EE_CS# EEPROM Interface PCI_ACK64# A13 pACK64# {4,5,8} U65 8 PCI_M66EN B9 M66EN {4,5,6,7,8,11} VCC PCI_PAR D7 pPAR {4,5,8} 5 SI SO 2 PCI_SERR# A6 pSERR# {4,5,8} PCI_PERR# B6 pPERR# {4,5,8} 6 SCK PCI_STOP# C6 pSTOP# {4,5,8} 3 A5 PCIXCAP WP/ 1 PCI_PCIXCAP PCIXCAP {11} 7 Install C5 PCIXCAP_PU 1K R9 HOLD/ JP14 PCI_PCIXCAP_PU 1 CS/ jumper to PCI_DEVSEL# A4 pDEVSEL# {4,5,8} JUMPER D6 GND PCI_TRDY# pTRDY# {4,5,8} assert PCI/PCI-X B4 V3.3 EEPROM 8 Pin DIP Socket 2 EE_PR# PCI_IRDY# pIRDY# {4,5,8} D5 pFRAME# {4,5,8} 4 Control Signals PCI_FRAME# 3.3K R162 PCI_IDSEL E4 CBE#0 PCI_C/BE[0]# D10 B7 CBE#1 PCI_C/BE[1]# CBE#2 PCI_C/BE[2]# A3 C1 CBE#3 PCI_C/BE[3]# AD0 PCI_AD[0] C12 A12 AD1 PCI_AD[1] AD2 PCI_AD[2] C11 A11 AD3 PCI_AD[3] AD4 PCI_AD[4] D11 B11 AD5 PCI_AD[5] AD6 PCI_AD[6] C10 A10 AD7 PCI_AD[7] AD8 PCI_AD[8] B10 D9 AD9 PCI_AD[9] AD10 PCI_AD[10] A9 C8 AD11 PCI_AD[11] AD12 PCI_AD[12] A8 D8 AD13 B PCI_AD[13] B R16 A7 AD14 {11} LANE_GOOD3# PEX_LANE_GOOD[3]# PCI_AD[14] AD15 {11} LANE_GOOD2# T16 PEX_LANE_GOOD[2]# PCI_AD[15] C7 R15 C4 AD16 {11} LANE_GOOD1# PEX_LANE_GOOD[1]# PCI/PCI-X 32-Bit PCI_AD[16] AD17 {11} LANE_GOOD0# T15 PEX_LANE_GOOD[0]# PCI_AD[17] B3 Bus D4 AD18 PCI_AD[18] AD19 {10} PB_PERn3 M11 A2 PEX_PERn[3] PCI_AD[19] AD20 {10} PB_PERp3 N11 C3 PEX_PERp[3] PCI_AD[20] AD21 PCI_AD[21] A1 C4 0.1uF PETn3 T11 C2 AD22 {10} PB_PETn3 PETp3 PEX_PETn[3] PCI_AD[22] AD23 {10} PB_PETp3 R11 PEX_PETp[3] PCI_AD[23] B1 C5 0.1uF D3 AD24 PCI_AD[24] AD25 {10} PB_PERn2 M9 D2 PEX_PERn[2] PCI_AD[25] AD26 {10} PB_PERp2 N9 E3 PEX_PERp[2] PCI_AD[26] AD27 PCI_AD[27] D1 C6 0.1uF PETn2 T9 F4 AD28 {10} PB_PETn2 PETp2 PEX_PETn[2] PCI_AD[28] AD29 {10} PB_PETp2 R9 PEX_PETp[2] PCI_AD[29] E1 C7 0.1uF F3 AD30 PCI_AD[30] AD31 {10} PB_PERn1 M7 PEX_PERn[1] PCI_AD[31] F1 {10} PB_PERp1 N7 PEX_PERp[1] PME# 0 R62 PCI Express x4 Port PCI_PME# G4 pPME# {4,5,6,7,8} C8 0.1uF PETn1 T7 {10} PB_PETn1 PETp1 PEX_PETn[1] PCI_GNT#_GNT#0 36 R38 R7 G3 GNT#_GNT#0 {4,8} {10} PB_PETp1 C9 0.1uF PEX_PETp[1] PCI_GNT#/GNT[0]# PCI_REQ#_REQ#0 0 R16 G2 REQ#_REQ#0 {4,8} V3.3 PCI_REQ#/REQ[0]# REQ#1 {10} PB_PERn0 M5 G1 REQ#1 {5,8} PEX_PERn[0] PCI_REQ[1]# PCI_GNT#1 36 R17 {10} PB_PERp0 N5 H3 PEX_PERp[0] PCI_GNT[1]# REQ#2 GNT#1 {5,8} PCI_REQ[2]# H2 REQ#2 {6,8} C10 0.1uF PETn0 T5 J4 PCI_GNT#2 36 R18 {10} PB_PETn0 PETp0 PEX_PETn[0] PCI_GNT[2]# REQ#3 GNT#2 {6,8} {10} PB_PETp0 R5 PEX_PETp[0] PCI/PCI-X PCI_REQ[3]# H1 REQ#3 {7,8} C11 0.1uF J3 PCI_GNT#3 36 R19 R20 R21 R22 C12 0.1uF PCI_GNT[3]# GNT#3 {7,8} {10} REFCLK_n R3 Arbiter 1K 1K 1K PEX_REFCLKn {10} REFCLK_p T3 H4 JP1 C13 0.1uF PEX_REFCLKp PCI_RST# PCI_RST# {4,5,6,7,8} {11} PB_PERST# T1 PEX_PERST# PCLK_IN J1 TPV2 PCI_CLK PCLK_FDBK 10 9 P1 N6 PCLK_FDBK {11} GND TCK JTAG_TCK STRAP_EXT_CLK_SEL PCI_CLKO3 0 R25 8 GND TMS 7 P2 JTAG_TMS PCI_CLKO[3] L1 pPCLK3 {7} 6 5 36 R27 N1 L2 PCI_CLKO2 0 R28 GND TDO JTAG_TDO PCI_CLKO[2] PCI_CLKO1 0 R30 pPCLK2 {6} 4 GND TDI 3 N2 JTAG_TDI PCI_CLKO[1] K1 pPCLK1 {5} A 2 1 R1 K3 PCI_CLKO0 0 R32 A GND TRST# JTAG_TRST# JTAG Interface PCI_CLKO[0] pPCLK {4} PCI/PCI-X pINTD# M2 pINTD# {4,5,6,7,8} JTAG Header PCI_INT[D]# pINTC# K4 pINTC# {4,5,6,7,8} R33 Clocks PCI_INT[C]# pINTB# M1 pINTB# {4,5,6,7,8} 1.5K PCI_INT[B]# pINTA# PCI_INT[A]# L3 pINTA# {4,5,6,7,8} PCI/PCI-X PLX Technology, Inc. {10} JTAG_TCK 870 Maude Avenue {10} JTAG_TMS Interrupts Sunnyvale, CA 94085

{10} JTAG_TDO VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS www.plxtech.com {10} JTAG_TDI {10} JTAG_TRST# J6 J7 J8 J9

L6 L7 L8 L9 Title F6 F7 F8 F9 T4 T8

B5 E2 K2 K6 K7 K8 K9 P5 P6 P7 P9 Title C9 H6 H7 H8 H9 N8 G6 G7 G8 G9 J10 J11 L10 L11 L15 F10 F11 F15 T12 B13 K10 K11 P10 P11 H10 H11 N10 N12 G10 G11 PEX 8114 Forward Bridge RDK - PEX 8114

SizeSize Document Document Number Number Rev Rev C 91-0052-300-A 300

Date:Date:Tuesday, December 18, 2007 Sheet Sheet 313of 5 4 3 2 1 5 4 3 2 1

PCI SLOT 0

PCI_3P3

DS11 R556 390 AD[63:0] {3,5,8} Green AD63 D J10 AD62 D PCI_5P0 94A 94B AD61 RSV GND AD60 93A GND RSV 93B 92A 92B AD59 AD32 RSV RSV AD58 91A AD[32] GND 91B 90A 90B AD33 AD57 AD34 GND AD[33] AD35 AD56 3 1 5 3 1 5 3 1 3 1 3 1 3 1 89A AD[34] AD[35] 89B C86 C87 C345 C347 C348 C349 AD36 88A 88B AD55 AD[36] +VIO(3.3V) AD37 AD54 87A GND AD[37] 87B 10uF 10uF 0.1uF 0.1uF 0.1uF 0.1uF AD38 86A 86B AD39 AD53 4 2 6 4 2 6 4 2 4 2 4 2 4 2 AD40 AD[38] AD[39] AD52 85A AD[40] GND 85B 84A 84B AD41 AD51 AD42 +VIO(3.3V) AD[41] AD43 AD50 83A AD[42] AD[43] 83B AD44 82A 82B AD49 AD[44] GND AD45 AD48 81A GND AD[45] 81B AD46 80A 80B AD47 AD47 AD48 AD[46] AD[47] AD46 79A AD[48] +VIO(3.3V) 79B 78A 78B AD49 AD45 AD50 GND AD[49] AD51 AD44 77A AD[50] AD[51] 77B PCI_3P3 AD52 76A 76B AD43 AD[52] GND AD53 AD42 75A +VIO(3.3V) AD[53] 75B AD54 74A 74B AD55 AD41 AD56 AD[54] AD[55] AD40 73A AD[56] GND 73B 72A 72B AD57 AD39 AD58 GND AD[57] AD59 AD38 3 1 5 3 1 5 3 1 5 3 1 3 1 3 1 3 1 3 1 3 1 3 1 3 1 71A AD[58] AD[59] 71B C89 C90 C91 C358 C359 C360 C361 C354 C355 C356 C357 AD60 70A 70B AD37 AD[60] +VIO(3.3V) AD61 AD36 69A GND AD[61] 69B 10uF 10uF 10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF AD62 68A 68B AD63 AD35 4 2 6 4 2 6 4 2 6 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 AD[62] AD[63] pPAR64 67A 67B AD34 PAR64 GND CBE#4 AD33 66A +VIO(3.3V) C/BE[4]# 66B CBE#5 65A 65B CBE#6 AD32 CBE#7 C/BE[5]# C/BE[6]# AD31 64A C/BE[7]# GND 64B 63A 63B AD30 PCI_5P0 GND RSV PCI_5P0 AD29 KEYWAY AD28 62A 62B AD27 +5V +5V AD26 61A +5V +5V 61B C pREQ64# pACK64# AD25 C 60A REQ64# ACK64# 60B PCI_12P0 PCI_N12P0 59A 59B AD24 AD0 +VIO(3.3V) +VIO(3.3V) AD1 AD23 58A AD[00] AD[01] 58B AD2 57A 57B AD22 AD[02] GND AD3 AD21 56A GND AD[03] 56B AD4 55A 55B AD5 AD20 AD6 AD[04] AD[05] AD19 3 1 5 3 1 3 1 5 3 1 54A AD[06] +3.3V 54B C88 C362 C92 C363 53A 53B AD7 AD18 CBE#0 +3.3V AD[07] AD8 AD17 52A C/BE[0]# AD[08] 52B 10uF 0.1uF 10uF 0.1uF 51A 51B AD16 4 2 6 4 2 4 2 6 4 2 GND GND AD15 50A GND GND 50B AD9 49A 49B M66EN AD14 AD[09] M66EN AD10 AD13 48A GND AD[10] 48B AD11 47A 47B AD12 AD12 AD13 AD[11] AD[12] AD11 46A AD[13] GND 46B 45A 45B AD14 AD10 AD15 +3.3V AD[14] CBE#1 AD9 44A AD[15] C/BE[1]# 44B pPAR 43A 43B AD8 PAR +3.3V pSERR# AD7 42A GND SERR# 42B Place caps as close to connector power pins as possible 41A 41B AD6 SMBDAT +3.3V pPERR# AD5 40A SMBCLK PERR# 40B 39A 39B pLOCK# AD4 pSTOP# +3.3V LOCK# pPCIXCAP AD3 38A STOP# PCIXCAP 38B 37A 37B pDEVSEL# AD2 pTRDY# GND DEVSEL# AD1 36A TRDY# +3.3V 36B 35A 35B pIRDY# AD0 pFRAME# GND IRDY# 34A 34B CBE#[7:0] {3,5,8} FRAME# GND CBE#2 CBE#7 33A +3.3V C/BE[2]# 33B AD16 32A 32B AD17 CBE#6 AD18 AD[16] AD[17] CBE#5 31A AD[18] +3.3V 31B 30A 30B AD19 CBE#4 AD20 GND AD[19] AD21 CBE#3 29A AD[20] AD[21] 29B AD22 28A 28B CBE#2 AD[22] GND AD23 CBE#1 27A +3.3V AD[23] 27B S0_IDSEL 26A 26B CBE#3 CBE#0 AD24 IDSEL C/BE[3]# 25A AD[24] +3.3V 25B 24A 24B AD25 AD26 GND AD[25] AD27 pPAR64 23A 23B pPAR64 {3,5,8} B AD28 AD[26] AD[27] pACK64# B 22A 22B pACK64# {3,5,8} AD[28] GND AD29 pREQ64# 21A 21B pREQ64# {3,5,8} AD30 +3.3V AD[29] AD31 20A AD[30] AD[31] 20B pPME# 19A 19B PME# +VIO(3.3V) REQ#_REQ#0 pDEVSEL# 18A 18B pDEVSEL# {3,5,8} GNT#_GNT#0 GND REQ# pSERR# 17A 17B pSERR# {3,5,8} GNT# GND pPCLK pPERR# 16A 16B pPERR# {3,5,8} PCI_RST# +VIO(3.3V) CLK pPAR 15A 15B pPAR {3,5,8} RST# GND pLOCK# 14A 14B pLOCK# {5,8} 3.3Vaux RSV PCI_N12P0 pSTOP# pSTOP# {3,5,8} PCI_12P0 KEYWAY pFRAME# pFRAME# {3,5,8} pTRDY# 11A 11B pTRDY# {3,5,8} RSV PRSNT2# pIRDY# 10A +VIO(3.3V) RSV 10B pIRDY# {3,5,8} 9A 9B RSV PRSNT1# pINTD# REQ#_REQ#0 8A 8B REQ#_REQ#0 {3,8} pINTC# +5V INTD# pINTB# GNT#_GNT#0 7A INTC# INTB# 7B GNT#_GNT#0 {3,8} pINTA# 6A 6B INTA# +5V C333 C334 pINTD# 5A 5B pINTD# {3,5,6,7,8} AD20 R168 0 S0_IDSEL +5V +5V (1) (1) pINTC# IDSEL0 4A 4B pINTC# {3,5,6,7,8} AD24 R167 NL TDI TDO 0.01uF 0.01uF pINTB# 3A 3B pINTB# {3,5,6,7,8} TMS GND pINTA# 2A +12V TCK 2B pINTA# {3,5,6,7,8} 1A PCI-X, FM, Thru-hole 1B TRST# -12V PCI_RST# PCI_RST# {3,5,6,7,8} pPME# pPME# {3,5,6,7,8} pPCLK PPCLK pPCLK {3} pPCIXCAP pPCIXCAP {5,6,7,8,11} M66EN M66EN {3,5,6,7,8,11} Place within 0.25 inch of connector C335 (2) 0.01uF

A (1) PCI Specification, Rev 2.3, Section 4.3.7 A

(2) PCI Specification, Rev 2.3, Section 7.7.7

PLX Technology, Inc. 870 Maude Avenue Sunnyvale, CA 94085 www.plxtech.com

TitleTitle PEX 8114 Forward Bridge RDK - PCI Slot 0

SizeSize Document Document Number Number Rev Rev C 91-0052-300-A 300

Date:Date:Tuesday, December 18, 2007 Sheet Sheet 413of 5 4 3 2 1 5 4 3 2 1

PCI SLOT 1 PCI_3P3 DS12 R557 390 Green JP15 AD[63:0] {3,4,8} 1 2 SLOT1_EN# AD63 SLOT1_EN# {6} AD62 {6} S1_AD[63:0] S1_AD63 JUMPER AD61 S1_AD62 AD60 S1_AD61 PCI_3P3 PCI_3P3 AD59 S1_AD60 AD58 D S1_AD59 AD57 D S1_AD58 AD56 S1_AD57 U98 U99 AD55 S1_AD56 1 20 1 20 AD54 S1_AD55 AD32 NC VCC NC VCC AD53 2 A0 OE# 19 2 A0 OE# 19 S1_AD54 3 18 3 18 AD33 AD52 S1_AD53 AD34 A1 B0 A1 B0 AD35 AD51 4 A2 B1 17 4 A2 B1 17 S1_AD52 AD36 5 16 5 16 AD50 S1_AD51 A3 B2 A3 B2 AD37 AD49 6 Solder Side 15 6 Component15 Side S1_AD50 A4 B3 PCI_3P3 A4 B3 AD39 AD48 7 A5 B4 14 7 A5 B4 14 S1_AD49 AD38 8 13 Component Side 8 13 AD47 S1_AD48 AD40 A6 B5 A6 B5 AD41 AD46 9 A7 B6 12 9 A7 B6 12 S1_AD47 10 11 10 11 AD43 AD45 S1_AD46 GND B7 GND B7 AD44 J11 S1_AD45 IDTQS3VH245Q IDTQS3VH245Q AD43 S1_AD44 94A 94B AD42 S1_AD43 RSV GND AD41 U100 93A GND RSV 93B U101 S1_AD42 92A 92B AD40 S1_AD41 S1_AD32 RSV RSV AD39 1 NC VCC 20 91A AD[32] GND 91B 1 NC VCC 20 S1_AD40 AD42 2 19 90A 90B S1_AD33 2 19 AD38 S1_AD39 AD44 A0 OE# S1_AD34 GND AD[33] S1_AD35 A0 OE# AD45 AD37 3 A1 B0 18 89A AD[34] AD[35] 89B 3 A1 B0 18 S1_AD38 4 17 S1_AD36 88A 88B 4 17 AD47 AD36 S1_AD37 AD46 A2 B1 AD[36] +VIO(3.3V) S1_AD37 A2 B1 AD35 5 A3 B2 16 87A GND AD[37] 87B 5 A3 B2 16 S1_AD36 AD48 6 15 S1_AD38 86A 86B S1_AD39 6 15 AD49 AD34 S1_AD35 A4 B3 S1_AD40 AD[38] AD[39] A4 B3 AD51 AD33 7 A5 B4 14 85A AD[40] GND 85B 7 A5 B4 14 S1_AD34 AD50 8 13 84A 84B S1_AD41 8 13 AD32 S1_AD33 AD52 A6 B5 S1_AD42 +VIO(3.3V) AD[41] S1_AD43 A6 B5 AD53 AD31 9 A7 B6 12 83A AD[42] AD[43] 83B 9 A7 B6 12 S1_AD32 10 11 S1_AD44 82A 82B 10 11 AD55 AD30 S1_AD31 GND B7 AD[44] GND S1_AD45 GND B7 AD29 81A GND AD[45] 81B S1_AD30 IDTQS3VH245Q S1_AD46 80A 80B S1_AD47 IDTQS3VH245Q AD28 S1_AD29 S1_AD48 AD[46] AD[47] AD27 79A AD[48] +VIO(3.3V) 79B S1_AD28 78A 78B S1_AD49 AD26 S1_AD27 U103 S1_AD50 GND AD[49] S1_AD51 AD25 77A AD[50] AD[51] 77B S1_AD26 1 20 S1_AD52 76A 76B AD24 S1_AD25 AD54 NC VCC AD[52] GND S1_AD53 AD23 2 A0 OE# 19 75A +VIO(3.3V) AD[53] 75B U102 S1_AD24 AD56 3 18 S1_AD54 74A 74B S1_AD55 AD22 S1_AD23 AD58 A1 B0 S1_AD56 AD[54] AD[55] AD21 4 A2 B1 17 73A AD[56] GND 73B 1 NC VCC 20 C S1_AD22 AD60 S1_AD57 AD20 C 5 A3 B2 16 72A GND AD[57] 72B 2 A0 OE# 19 S1_AD21 AD62 6 15 S1_AD58 71A 71B S1_AD59 3 18 AD57 AD19 S1_AD20 pPAR64 A4 B3 S1_AD60 AD[58] AD[59] A1 B0 AD59 AD18 7 A5 B4 14 70A AD[60] +VIO(3.3V) 70B 4 A2 B1 17 S1_AD19 CBE#5 8 13 69A 69B S1_AD61 5 16 AD17 S1_AD18 CBE#7 A6 B5 S1_AD62 GND AD[61] S1_AD63 A3 B2 AD61 AD16 9 A7 B6 12 68A AD[62] AD[63] 68B 6 A4 B3 15 S1_AD17 10 11 S1_PAR64 67A 67B 7 14 AD63 AD15 S1_AD16 GND B7 PAR64 GND S1_CBE#4 A5 B4 AD14 66A +VIO(3.3V) C/BE[4]# 66B 8 A6 B5 13 S1_AD15 IDTQS3VH245Q S1_CBE#5 S1_CBE#6 CBE#4 AD13 65A C/BE[5]# C/BE[6]# 65B 9 A7 B6 12 S1_AD14 S1_CBE#7 64A 64B 10 11 CBE#6 AD12 S1_AD13 C/BE[7]# GND GND B7 AD11 U104 63A GND RSV 63B S1_AD12 PCI_5P0 PCI_5P0 IDTQS3VH245Q AD10 S1_AD11 KEYWAY AD9 1 NC VCC 20 S1_AD10 pREQ64# 2 19 62A 62B AD8 S1_AD9 A0 OE# +5V +5V U105 AD7 3 A1 B0 18 61A +5V +5V 61B S1_AD8 AD0 4 17 S1_REQ64# 60A 60B S1_ACK64# 1 20 AD6 S1_AD7 AD2 A2 B1 REQ64# ACK64# NC VCC AD5 5 A3 B2 16 59A +VIO(3.3V) +VIO(3.3V) 59B 2 A0 OE# 19 S1_AD6 AD4 6 15 S1_AD0 58A 58B S1_AD1 3 18 pACK64# AD4 S1_AD5 AD6 A4 B3 S1_AD2 AD[00] AD[01] A1 B0 AD3 7 A5 B4 14 57A AD[02] GND 57B 4 A2 B1 17 S1_AD4 8 13 56A 56B S1_AD3 5 16 AD1 AD2 S1_AD3 CBE#0 A6 B5 S1_AD4 GND AD[03] S1_AD5 A3 B2 AD3 AD1 9 A7 B6 12 55A AD[04] AD[05] 55B 6 A4 B3 15 S1_AD2 10 11 S1_AD6 54A 54B 7 14 AD5 AD0 S1_AD1 GND B7 AD[06] +3.3V S1_AD7 A5 B4 53A +3.3V AD[07] 53B 8 A6 B5 13 CBE#[7:0] {3,4,8} S1_AD0 IDTQS3VH245Q S1_CBE#0 S1_AD8 AD7 CBE#7 52A C/BE[0]# AD[08] 52B 9 A7 B6 12 51A 51B 10 11 AD8 CBE#6 {6} S1_CBE#[7:0] S1_CBE#7 GND GND GND B7 CBE#5 U106 50A GND GND 50B S1_CBE#6 S1_AD9 M66EN IDTQS3VH245Q CBE#4 49A AD[09] M66EN 49B S1_CBE#5 1 20 48A 48B S1_AD10 CBE#3 S1_CBE#4 AD9 NC VCC S1_AD11 GND AD[10] S1_AD12 CBE#2 2 A0 OE# 19 47A AD[11] AD[12] 47B U107 S1_CBE#3 3 18 S1_AD13 46A 46B CBE#1 S1_CBE#2 AD11 A1 B0 AD[13] GND S1_AD14 CBE#0 4 A2 B1 17 45A +3.3V AD[14] 45B 1 NC VCC 20 S1_CBE#1 AD13 5 16 S1_AD15 44A 44B S1_CBE#1 2 19 S1_CBE#0 A3 B2 S1_PAR AD[15] C/BE[1]# A0 OE# AD10 6 A4 B3 15 43A PAR +3.3V 43B 3 A1 B0 18 AD15 7 14 42A 42B S1_SERR# 4 17 AD12 A5 B4 GND SERR# A2 B1 AD14 pPAR64 8 13 41A 41B 5 16 pPAR64 {3,4,8} S1_PAR64 pPAR A6 B5 SMBDAT +3.3V S1_PERR# A3 B2 CBE#1 pACK64# 9 12 40A 40B 6 15 pACK64# {3,4,8} {6} S1_PAR64 S1_ACK64# A7 B6 SMBCLK PERR# S1_LOCK# A4 B3 pREQ64# 10 11 39A 39B 7 14 pREQ64# {3,4,8} {6} S1_ACK64# S1_REQ64# GND B7 S1_STOP# +3.3V LOCK# pPCIXCAP A5 B4 pSERR# {6} S1_REQ64# 38A STOP# PCIXCAP 38B 8 A6 B5 13 IDTQS3VH245Q 37A 37B S1_DEVSEL# 9 12 pPERR# B S1_TRDY# GND DEVSEL# A7 B6 pLOCK# pDEVSEL# B 36A 36B 10 11 pDEVSEL# {3,4,8} S1_DEVSEL# TRDY# +3.3V S1_IRDY# GND B7 pSERR# 35A 35B pSERR# {3,4,8} {6} S1_DEVSEL# S1_SERR# U109 S1_FRAME# GND IRDY# pPERR# {6} S1_SERR# 34A 34B IDTQS3VH245Q pPERR# {3,4,8} S1_PERR# FRAME# GND S1_CBE#2 pPAR {6} S1_PERR# 1 20 33A 33B pPAR {3,4,8} S1_PAR pSTOP# NC VCC S1_AD16 +3.3V C/BE[2]# S1_AD17 pLOCK# {6} S1_PAR 2 19 32A 32B pLOCK# {4,8} S1_LOCK# A0 OE# S1_AD18 AD[16] AD[17] U108 pSTOP# {6} S1_LOCK# 3 18 31A 31B pSTOP# {3,4,8} S1_STOP# pTRDY# A1 B0 AD[18] +3.3V S1_AD19 pFRAME# 4 17 30A 30B 1 20 pFRAME# {3,4,8} {6} S1_STOP# S1_FRAME# A2 B1 S1_AD20 GND AD[19] S1_AD21 NC VCC pTRDY# 5 16 29A 29B 2 19 pTRDY# {3,4,8} {6} S1_FRAME# S1_TRDY# pFRAME# A3 B2 S1_AD22 AD[20] AD[21] A0 OE# pDEVSEL# pIRDY# {6} S1_TRDY# 6 15 28A 28B 3 18 pIRDY# {3,4,8} S1_IRDY# A4 B3 AD[22] GND S1_AD23 A1 B0 {6} S1_IRDY# 7 A5 B4 14 27A +3.3V AD[23] 27B 4 A2 B1 17 AD16 8 13 S1_IDSEL 26A 26B S1_CBE#3 5 16 pIRDY# REQ#1 AD18 A6 B5 S1_AD24 IDSEL C/BE[3]# A3 B2 CBE#2 GNT#1 REQ#1 {3,8} 9 A7 B6 12 25A AD[24] +3.3V 25B 6 A4 B3 15 GNT#1 {3,8} 10 11 24A 24B S1_AD25 7 14 AD17 GND B7 S1_AD26 GND AD[25] S1_AD27 A5 B4 pINTD# 23A 23B 8 13 pINTD# {3,4,6,7,8} S1_AD28 AD[26] AD[27] A6 B5 AD19 pINTC# IDTQS3VH245Q 22A 22B 9 12 pINTC# {3,4,6,7,8} AD[28] GND S1_AD29 A7 B6 AD21 pINTB# 21A 21B 10 11 pINTB# {3,4,6,7,8} S1_AD30 +3.3V AD[29] S1_AD31 GND B7 pINTA# U110 20A AD[30] AD[31] 20B pINTA# {3,4,6,7,8} pPME# 19A 19B IDTQS3VH245Q PME# +VIO(3.3V) REQ#1 PCI_RST# 1 20 18A 18B PCI_RST# {3,4,6,7,8} AD20 NC VCC GNT#1 GND REQ# pPME# 2 A0 OE# 19 17A GNT# GND 17B U111 pPME# {3,4,6,7,8} AD22 3 18 16A 16B pPCLK1 A1 B0 PCI_RST# +VIO(3.3V) CLK pPCLK1 4 A2 B1 17 15A RST# GND 15B 1 NC VCC 20 PPCLK1 pPCLK1 {3} AD24 5 16 14A 14B 2 19 pPCIXCAP A3 B2 3.3Vaux RSV PCI_N12P0 A0 OE# AD23 pPCIXCAP {4,6,7,8,11} 6 A4 B3 15 3 A1 B0 18 AD26 7 14 PCI_12P0 KEYWAY 4 17 CBE#3 AD28 A5 B4 A2 B1 M66EN 8 13 11A 11B 5 16 M66EN {3,4,6,7,8,11} AD30 A6 B5 RSV PRSNT2# A3 ComponentB2 Side AD25 9 A7 B6 12 10A +VIO(3.3V) RSV 10B 6 A4 B3 15 10 11 9A 9B 7 14 AD27 C336 Place within 0.25 GND B7 RSV PRSNT1# pINTA# A5 B4 8A +5V INTD# 8B 8 A6 B5 13 (2) inch of connector IDTQS3VH245Q pINTD# pINTC# AD29 0.01uF 7A INTC# INTB# 7B 9 A7 B6 12 pINTB# 6A 6B 10 11 AD31 Solder Side INTA# +5V C337 C338 GND B7 5A +5V +5V 5B 4A 4B (1) (1) IDTQS3VH245Q S1_AD21 R253 0 S1_IDSEL TDI TDO 0.01uF 0.01uF IDSEL1 3A 3B S1_AD25 R254 NL TMS GND 2A +12V TCK 2B 1A PCI-X, FM, Thru-hole 1B TRST# -12V (1) PCI Specification, Rev 2.3, Section 4.3.7 A Place caps as close to connector power pins as possible A

PCI_5P0 PCI_3P3 PCI_12P0 PCI_N12P0 (2) PCI Specification, Rev 2.3, Section 7.7.7

PLX Technology, Inc. 3 1 5 3 1 5 3 1 3 1 3 1 3 1 3 1 5 3 1 5 3 1 5 3 1 3 1 3 1 3 1 3 1 3 1 3 1 3 1 3 1 5 3 1 3 1 5 3 1 C93 C94 C350 C351 C352 C353 C95 C96 C97 C368 C369 C370 C371 C364 C365 C366 C367 C100 C373 C98 C372 870 Maude Avenue Sunnyvale, CA 94085 10uF 10uF 0.1uF 0.1uF 0.1uF 0.1uF 10uF 10uF 10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 10uF 0.1uF 10uF 0.1uF www.plxtech.com 4 2 6 4 2 6 4 2 4 2 4 2 4 2 4 2 6 4 2 6 4 2 6 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 6 4 2 4 2 6 4 2 TitleTitle PEX 8114 Forward Bridge RDK - PCI Slot 1

SizeSize Document Document Number Number Rev Rev C 91-0052-300-A 300

Date:Date:Tuesday, December 18, 2007 Sheet Sheet 513of 5 4 3 2 1 5 4 3 2 1 PCI_3P3 PCI SLOT 2 R255 3.3K

{7} S2_AD[63:0] JP16 S1_AD[63:0] {5} S2_AD63 1 2 SLOT2_3_EN# S1_AD63 S2_AD62 S1_AD62 S2_AD61 JUMPER PCI_3P3 S1_AD61 S2_AD60 S1_AD60 S2_AD59 PCI_3P3 DS13 PCI_3P3 S1_AD59 S2_AD58 R558 390 S1_AD58 D S2_AD57 Green S1_AD57 D S2_AD56 S1_AD56 S2_AD55 U112 DS14 U113 S1_AD55 S2_AD54 R559 390 S1_AD54 1 NC VCC 20 1 NC VCC 20 S2_AD53 S1_AD32 2 19 Green 2 19 S1_AD53 S2_AD52 A0 OE# A0 OE# S1_AD33 S1_AD52 {5} SLOT1_EN# 3 18 3 18 S2_AD51 S1_AD34 A1 B0 A1 B0 S1_AD35 S1_AD51 4 A2 B1 17 4 A2 B1 17 S2_AD50 S1_AD36 5 16 5 16 S1_AD50 S2_AD49 A3 B2 A3 B2 S1_AD37 S1_AD49 6 Solder Side 15 Component6 Side 15 S2_AD48 A4 B3 PCI_3P3 A4 B3 S1_AD39 S1_AD48 7 A5 B4 14 7 A5 B4 14 S2_AD47 S1_AD38 8 13 8 13 S1_AD47 S2_AD46 S1_AD40 A6 B5 A6 B5 S1_AD41 S1_AD46 9 A7 B6 12 9 A7 B6 12 S2_AD45 10 11 10 11 S1_AD43 S1_AD45 S2_AD44 GND B7 GND B7 S1_AD44 J12 S2_AD43 IDTQS3VH245Q IDTQS3VH245Q S1_AD43 S2_AD42 94A 94B S1_AD42 S2_AD41 RSV GND S1_AD41 U115 93A GND RSV 93B U114 S2_AD40 92A Component Side 92B S1_AD40 S2_AD39 S2_AD32 RSV RSV S1_AD39 1 NC VCC 20 91A AD[32] GND 91B 1 NC VCC 20 S2_AD38 S1_AD42 2 19 90A 90B S2_AD33 2 19 S1_AD38 S2_AD37 S1_AD44 A0 OE# S2_AD34 GND AD[33] S2_AD35 A0 OE# S1_AD45 S1_AD37 3 A1 B0 18 89A AD[34] AD[35] 89B 3 A1 B0 18 S2_AD36 4 17 S2_AD36 88A 88B 4 17 S1_AD47 S1_AD36 S2_AD35 S1_AD46 A2 B1 AD[36] +VIO(3.3V) S2_AD37 A2 B1 S1_AD35 5 A3 B2 16 87A GND AD[37] 87B 5 A3 B2 16 S2_AD34 S1_AD48 6 15 S2_AD38 86A 86B S2_AD39 6 15 S1_AD49 S1_AD34 S2_AD33 A4 B3 S2_AD40 AD[38] AD[39] A4 B3 S1_AD51 S1_AD33 7 A5 B4 14 85A AD[40] GND 85B 7 A5 B4 14 S2_AD32 S1_AD50 8 13 84A 84B S2_AD41 8 13 S1_AD32 S2_AD31 S1_AD52 A6 B5 S2_AD42 +VIO(3.3V) AD[41] S2_AD43 A6 B5 S1_AD53 S1_AD31 9 A7 B6 12 83A AD[42] AD[43] 83B 9 A7 B6 12 S2_AD30 10 11 S2_AD44 82A 82B 10 11 S1_AD55 S1_AD30 S2_AD29 GND B7 AD[44] GND S2_AD45 GND B7 S1_AD29 81A GND AD[45] 81B S2_AD28 IDTQS3VH245Q S2_AD46 80A 80B S2_AD47 IDTQS3VH245Q S1_AD28 S2_AD27 S2_AD48 AD[46] AD[47] S1_AD27 79A AD[48] +VIO(3.3V) 79B S2_AD26 78A 78B S2_AD49 S1_AD26 S2_AD25 U116 S2_AD50 GND AD[49] S2_AD51 S1_AD25 77A AD[50] AD[51] 77B S2_AD24 1 20 S2_AD52 76A 76B S1_AD24 S2_AD23 S1_AD54 NC VCC AD[52] GND S2_AD53 S1_AD23 2 A0 OE# 19 75A +VIO(3.3V) AD[53] 75B U117 S2_AD22 S1_AD56 3 18 S2_AD54 74A 74B S2_AD55 S1_AD22 S2_AD21 S1_AD58 A1 B0 S2_AD56 AD[54] AD[55] S1_AD21 4 A2 B1 17 73A AD[56] GND 73B 1 NC VCC 20 C S2_AD20 S1_AD60 S2_AD57 S1_AD20 C 5 A3 B2 16 72A GND AD[57] 72B 2 A0 OE# 19 S2_AD19 S1_AD62 6 15 S2_AD58 71A 71B S2_AD59 3 18 S1_AD57 S1_AD19 S2_AD18 S1_PAR64 A4 B3 S2_AD60 AD[58] AD[59] A1 B0 S1_AD59 S1_AD18 7 A5 B4 14 70A AD[60] +VIO(3.3V) 70B 4 A2 B1 17 S2_AD17 S1_CBE#5 8 13 69A 69B S2_AD61 5 16 S1_AD17 S2_AD16 S1_CBE#7 A6 B5 S2_AD62 GND AD[61] S2_AD63 A3 B2 S1_AD61 S1_AD16 9 A7 B6 12 68A AD[62] AD[63] 68B 6 A4 B3 15 S2_AD15 10 11 S2_PAR64 67A 67B 7 14 S1_AD63 S1_AD15 S2_AD14 GND B7 PAR64 GND S2_CBE#4 A5 B4 S1_AD14 66A +VIO(3.3V) C/BE[4]# 66B 8 A6 B5 13 S2_AD13 IDTQS3VH245Q S2_CBE#5 S2_CBE#6 S1_CBE#4 S1_AD13 65A C/BE[5]# C/BE[6]# 65B 9 A7 B6 12 S2_AD12 S2_CBE#7 64A 64B 10 11 S1_CBE#6 S1_AD12 S2_AD11 C/BE[7]# GND GND B7 S1_AD11 U118 63A GND RSV 63B S2_AD10 PCI_5P0 PCI_5P0 IDTQS3VH245Q S1_AD10 S2_AD9 KEYWAY S1_AD9 1 NC VCC 20 S2_AD8 S1_REQ64# 2 19 62A 62B S1_AD8 S2_AD7 A0 OE# +5V +5V U119 S1_AD7 3 A1 B0 18 61A +5V +5V 61B S2_AD6 S1_AD0 4 17 S2_REQ64# 60A 60B S2_ACK64# 1 20 S1_AD6 S2_AD5 S1_AD2 A2 B1 REQ64# ACK64# NC VCC S1_AD5 5 A3 B2 16 59A +VIO(3.3V) +VIO(3.3V) 59B 2 A0 OE# 19 S2_AD4 S1_AD4 6 15 S2_AD0 58A 58B S2_AD1 3 18 S1_ACK64# S1_AD4 S2_AD3 S1_AD6 A4 B3 S2_AD2 AD[00] AD[01] A1 B0 S1_AD3 7 A5 B4 14 57A AD[02] GND 57B 4 A2 B1 17 S2_AD2 8 13 56A 56B S2_AD3 5 16 S1_AD1 S1_AD2 S2_AD1 S1_CBE#0 A6 B5 S2_AD4 GND AD[03] S2_AD5 A3 B2 S1_AD3 S1_AD1 9 A7 B6 12 55A AD[04] AD[05] 55B 6 A4 B3 15 S2_AD0 10 11 S2_AD6 54A 54B 7 14 S1_AD5 S1_AD0 GND B7 AD[06] +3.3V S2_AD7 A5 B4 {7} S2_CBE#[7:0] 53A +3.3V AD[07] 53B 8 A6 B5 13 S1_CBE#[7:0] {5} S2_CBE#7 IDTQS3VH245Q S2_CBE#0 S2_AD8 S1_AD7 S1_CBE#7 52A C/BE[0]# AD[08] 52B 9 A7 B6 12 S2_CBE#6 51A 51B 10 11 S1_AD8 S1_CBE#6 S2_CBE#5 GND GND GND B7 S1_CBE#5 U120 50A GND GND 50B S2_CBE#4 S2_AD9 49A 49B M66EN IDTQS3VH245Q S1_CBE#4 S2_CBE#3 AD[09] M66EN S2_AD10 S1_CBE#3 1 NC VCC 20 48A GND AD[10] 48B S2_CBE#2 S1_AD9 2 19 S2_AD11 47A 47B S2_AD12 S1_CBE#2 S2_CBE#1 A0 OE# S2_AD13 AD[11] AD[12] U121 S1_CBE#1 3 A1 B0 18 46A AD[13] GND 46B S2_CBE#0 S1_AD11 4 17 45A 45B S2_AD14 1 20 S1_CBE#0 S1_AD13 A2 B1 S2_AD15 +3.3V AD[14] S2_CBE#1 NC VCC 5 A3 B2 16 44A AD[15] C/BE[1]# 44B 2 A0 OE# 19 6 15 S2_PAR 43A 43B 3 18 S1_AD10 S2_PAR64 S1_AD15 A4 B3 PAR +3.3V S2_SERR# A1 B0 S1_AD12 S1_PAR64 7 14 42A 42B 4 17 S1_PAR64 {5} {7} S2_PAR64 S2_ACK64# A5 B4 GND SERR# A2 B1 S1_AD14 S1_ACK64# 8 13 41A 41B 5 16 S1_ACK64# {5} {7} S2_ACK64# S2_REQ64# S1_PAR A6 B5 SMBDAT +3.3V S2_PERR# A3 B2 S1_CBE#1 S1_REQ64# {7} S2_REQ64# 9 12 40A 40B 6 15 S1_REQ64# {5} A7 B6 SMBCLK PERR# S2_LOCK# A4 B3 10 GND B7 11 39A +3.3V LOCK# 39B 7 A5 B4 14 S2_STOP# 38A 38B pPCIXCAP 8 13 S1_SERR# S2_DEVSEL# STOP# PCIXCAP S2_DEVSEL# A6 B5 S1_PERR# S1_DEVSEL# IDTQS3VH245Q 37A 37B 9 12 S1_DEVSEL# {5} B {7} S2_DEVSEL# S2_SERR# S2_TRDY# GND DEVSEL# A7 B6 S1_LOCK# S1_SERR# B {7} S2_SERR# 36A 36B 10 11 S1_SERR# {5} S2_PERR# TRDY# +3.3V S2_IRDY# GND B7 S1_PERR# {7} S2_PERR# 35A 35B S1_PERR# {5} S2_PAR U122 S2_FRAME# GND IRDY# S1_PAR {7} S2_PAR 34A 34B IDTQS3VH245Q S1_PAR {5} S2_LOCK# FRAME# GND S2_CBE#2 S1_LOCK# {7} S2_LOCK# 1 20 33A 33B S1_LOCK# {5} S2_STOP# S1_STOP# NC VCC S2_AD16 +3.3V C/BE[2]# S2_AD17 S1_STOP# 2 19 32A 32B S1_STOP# {5} {7} S2_STOP# S2_FRAME# A0 OE# S2_AD18 AD[16] AD[17] U123 S1_FRAME# 3 18 31A 31B S1_FRAME# {5} {7} S2_FRAME# S2_TRDY# S1_TRDY# A1 B0 AD[18] +3.3V S2_AD19 S1_TRDY# {7} S2_TRDY# 4 17 30A 30B 1 20 S1_TRDY# {5} S2_IRDY# A2 B1 S2_AD20 GND AD[19] S2_AD21 NC VCC S1_IRDY# 5 16 29A 29B 2 19 S1_IRDY# {5} {7} S2_IRDY# S1_FRAME# A3 B2 S2_AD22 AD[20] AD[21] A0 OE# S1_DEVSEL# 6 A4 B3 15 28A AD[22] GND 28B 3 A1 B0 18 7 14 27A 27B S2_AD23 4 17 REQ#2 S1_AD16 A5 B4 S2_IDSEL +3.3V AD[23] S2_CBE#3 A2 B1 S1_IRDY# GNT#2 REQ#2 {3,8} 8 A6 B5 13 26A IDSEL C/BE[3]# 26B 5 A3 B2 16 GNT#2 {3,8} S1_AD18 9 12 S2_AD24 25A 25B 6 15 S1_CBE#2 A7 B6 AD[24] +3.3V S2_AD25 A4 B3 S1_AD17 pINTD# 10 11 24A 24B 7 14 pINTD# {3,4,5,7,8} GND B7 S2_AD26 GND AD[25] S2_AD27 A5 B4 pINTC# 23A 23B 8 13 pINTC# {3,4,5,7,8} S2_AD28 AD[26] AD[27] A6 B5 S1_AD19 pINTB# IDTQS3VH245Q 22A 22B 9 12 pINTB# {3,4,5,7,8} AD[28] GND S2_AD29 A7 B6 S1_AD21 pINTA# 21A +3.3V AD[29] 21B 10 GND B7 11 pINTA# {3,4,5,7,8} S2_AD30 20A 20B S2_AD31 U124 pPME# AD[30] AD[31] PCI_RST# 19A 19B IDTQS3VH245Q PCI_RST# {3,4,5,7,8} PME# +VIO(3.3V) REQ#2 pPME# 1 NC VCC 20 18A GND REQ# 18B pPME# {3,4,5,7,8} S1_AD20 2 19 GNT#2 17A 17B S1_AD22 A0 OE# GNT# GND pPCLK2 U125 pPCLK2 3 18 16A 16B PPCLK2 pPCLK2 {3} A1 B0 PCI_RST# +VIO(3.3V) CLK pPCIXCAP 4 A2 B1 17 15A RST# GND 15B 1 NC VCC 20 pPCIXCAP {4,5,7,8,11} S1_AD24 5 16 14A 14B 2 19 A3 B2 3.3Vaux RSV PCI_N12P0 A0 OE# S1_AD23 6 A4 B3 15 3 A1 B0 18 S1_AD26 7 14 PCI_12P0 KEYWAY 4 17 S1_CBE#3 S1_AD28 A5 B4 A2 B1 M66EN 8 13 11A 11B 5 16 M66EN {3,4,5,7,8,11} S1_AD30 A6 B5 RSV PRSNT2# A3 B2 S1_AD25 9 A7 B6 12 10A +VIO(3.3V) RSV 10B 6 A4 B3 15 10 11 9A 9B 7 14 S1_AD27 C339 Place within 0.25 GND B7 RSV PRSNT1# pINTB# A5 B4 (2) inch of connector 8A +5V INTD# 8B 8 A6 B5 13 IDTQS3VH245Q pINTA# pINTD# S1_AD29 0.01uF 7A INTC# INTB# 7B 9 A7 B6 12 pINTC# 6A 6B 10 11 S1_AD31 Solder Side INTA# +5V C340 C341 GND B7 5A +5V +5V 5B (1) 4A 4B (1) IDTQS3VH245Q S2_AD22 R341 0 S2_IDSEL TDI TDO 0.01uF 0.01uF IDSEL2 3A 3B S2_AD26 R340 NL TMS GND 2A +12V TCK 2B PCI-X, FM, Thru-hole 1A TRST# -12V 1B (1) PCI Specification, Rev 2.3, Section 4.3.7 A Place caps as close to connector power pins as possible (2) PCI Specification, Rev 2.3, Section 7.7.7 A

PCI_5P0 PCI_3P3 PCI_12P0 PCI_N12P0

PLX Technology, Inc. 870 Maude Avenue 3 1 5 3 1 5 3 1 3 1 3 1 3 1 3 1 5 3 1 5 3 1 5 3 1 3 1 3 1 3 1 3 1 3 1 3 1 3 1 3 1 5 3 1 3 1 5 3 1 C103 C104 C376 C377 C378 C379 C105 C106 C107 C384 C385 C386 C387 C380 C381 C382 C383 C102 C375 C101 C374 Sunnyvale, CA 94085 www.plxtech.com 10uF 10uF 0.1uF 0.1uF 0.1uF 0.1uF 10uF 10uF 10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 10uF 0.1uF 10uF 0.1uF 4 2 6 4 2 6 4 2 4 2 4 2 4 2 4 2 6 4 2 6 4 2 6 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 6 4 2 4 2 6 4 2 TitleTitle PEX 8114 Forward Bridge RDK - PCI Slot 2

SizeSize Document Document Number Number Rev Rev C 91-0052-300-A 300

Date:Date:Tuesday, December 18, 2007 Sheet Sheet 613of 5 4 3 2 1 5 4 3 2 1

PCI SLOT 3

PCI_3P3 S2_AD[63:0] {6} S2_AD63 S2_AD62 S2_AD61 J13 S2_AD60 D S2_AD59 D 94A RSV GND 94B PCI_5P0 93A 93B S2_AD58 GND RSV S2_AD57 92A RSV RSV 92B S2_AD32 91A 91B S2_AD56 AD[32] GND S2_AD33 S2_AD55 90A GND AD[33] 90B S2_AD34 89A 89B S2_AD35 S2_AD54 S2_AD36 AD[34] AD[35] S2_AD53 3 1 5 3 1 5 3 1 3 1 3 1 3 1 88A AD[36] +VIO(3.3V) 88B C109 C110 C389 C397 C400 C401 87A 87B S2_AD37 S2_AD52 S2_AD38 GND AD[37] S2_AD39 S2_AD51 86A AD[38] AD[39] 86B 10uF 10uF 0.1uF 0.1uF 0.1uF 0.1uF S2_AD40 85A 85B S2_AD50 4 2 6 4 2 6 4 2 4 2 4 2 4 2 AD[40] GND S2_AD41 S2_AD49 84A +VIO(3.3V) AD[41] 84B S2_AD42 83A 83B S2_AD43 S2_AD48 S2_AD44 AD[42] AD[43] S2_AD47 82A AD[44] GND 82B 81A 81B S2_AD45 S2_AD46 S2_AD46 GND AD[45] S2_AD47 S2_AD45 80A AD[46] AD[47] 80B S2_AD48 79A 79B S2_AD44 AD[48] +VIO(3.3V) S2_AD49 S2_AD43 78A GND AD[49] 78B S2_AD50 77A 77B S2_AD51 S2_AD42 S2_AD52 AD[50] AD[51] S2_AD41 76A AD[52] GND 76B PCI_3P3 75A 75B S2_AD53 S2_AD40 S2_AD54 +VIO(3.3V) AD[53] S2_AD55 S2_AD39 74A AD[54] AD[55] 74B S2_AD56 73A 73B S2_AD38 AD[56] GND S2_AD57 S2_AD37 72A GND AD[57] 72B S2_AD58 71A 71B S2_AD59 S2_AD36 S2_AD60 AD[58] AD[59] S2_AD35 3 1 5 3 1 5 3 1 5 3 1 3 1 3 1 3 1 3 1 3 1 3 1 3 1 70A AD[60] +VIO(3.3V) 70B C112 C113 C114 C394 C395 C396 C398 C390 C391 C392 C393 69A 69B S2_AD61 S2_AD34 S2_AD62 GND AD[61] S2_AD63 S2_AD33 68A AD[62] AD[63] 68B 10uF 10uF 10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF S2_PAR64 67A 67B S2_AD32 4 2 6 4 2 6 4 2 6 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 PAR64 GND S2_CBE#4 S2_AD31 66A +VIO(3.3V) C/BE[4]# 66B S2_CBE#5 65A 65B S2_CBE#6 S2_AD30 S2_CBE#7 C/BE[5]# C/BE[6]# S2_AD29 64A C/BE[7]# GND 64B 63A 63B S2_AD28 PCI_5P0 GND RSV PCI_5P0 S2_AD27 KEYWAY S2_AD26 S2_AD25 62A +5V +5V 62B 61A 61B S2_AD24 S2_REQ64# +5V +5V S2_ACK64# S2_AD23 60A REQ64# ACK64# 60B C S2_AD22 C 59A +VIO(3.3V) +VIO(3.3V) 59B PCI_12P0 PCI_N12P0 S2_AD0 58A 58B S2_AD1 S2_AD21 S2_AD2 AD[00] AD[01] S2_AD20 57A AD[02] GND 57B 56A 56B S2_AD3 S2_AD19 S2_AD4 GND AD[03] S2_AD5 S2_AD18 55A AD[04] AD[05] 55B S2_AD6 54A 54B S2_AD17 AD[06] +3.3V S2_AD7 S2_AD16 3 1 5 3 1 3 1 5 3 1 53A +3.3V AD[07] 53B C111 C399 C108 C388 S2_CBE#0 52A 52B S2_AD8 S2_AD15 C/BE[0]# AD[08] S2_AD14 51A GND GND 51B 10uF 0.1uF 10uF 0.1uF 50A 50B S2_AD13 4 2 6 4 2 4 2 6 4 2 GND GND S2_AD9 49A 49B M66EN S2_AD12 AD[09] M66EN S2_AD10 S2_AD11 48A GND AD[10] 48B S2_AD11 47A 47B S2_AD12 S2_AD10 S2_AD13 AD[11] AD[12] S2_AD9 46A AD[13] GND 46B 45A 45B S2_AD14 S2_AD8 S2_AD15 +3.3V AD[14] S2_CBE#1 S2_AD7 44A AD[15] C/BE[1]# 44B S2_PAR 43A 43B S2_AD6 PAR +3.3V S2_SERR# S2_AD5 42A GND SERR# 42B 41A 41B S2_AD4 SMBDAT +3.3V S2_PERR# S2_AD3 40A SMBCLK PERR# 40B Place caps as close to connector power pins as possible 39A 39B S2_LOCK# S2_AD2 S2_STOP# +3.3V LOCK# pPCIXCAP S2_AD1 38A STOP# PCIXCAP 38B 37A 37B S2_DEVSEL# S2_AD0 S2_TRDY# GND DEVSEL# 36A 36B S2_CBE#[7:0] {6} TRDY# +3.3V S2_IRDY# S2_CBE#7 35A GND IRDY# 35B S2_FRAME# 34A 34B S2_CBE#6 FRAME# GND S2_CBE#2 S2_CBE#5 33A +3.3V C/BE[2]# 33B S2_AD16 32A 32B S2_AD17 S2_CBE#4 S2_AD18 AD[16] AD[17] S2_CBE#3 31A AD[18] +3.3V 31B 30A 30B S2_AD19 S2_CBE#2 S2_AD20 GND AD[19] S2_AD21 S2_CBE#1 29A AD[20] AD[21] 29B S2_AD22 28A 28B S2_CBE#0 AD[22] GND S2_AD23 27A +3.3V AD[23] 27B S3_IDSEL 26A 26B S2_CBE#3 S2_AD24 IDSEL C/BE[3]# S2_PAR64 25A 25B S2_PAR64 {6} AD[24] +3.3V S2_AD25 S2_ACK64# 24A 24B S2_ACK64# {6} S2_AD26 GND AD[25] S2_AD27 S2_REQ64# 23A AD[26] AD[27] 23B S2_REQ64# {6} S2_AD28 22A 22B B AD[28] GND B 21A 21B S2_AD29 S2_AD30 +3.3V AD[29] S2_AD31 S2_DEVSEL# 20A 20B S2_DEVSEL# {6} pPME# AD[30] AD[31] S2_SERR# 19A 19B S2_SERR# {6} PME# +VIO(3.3V) REQ#3 S2_PERR# 18A 18B S2_PERR# {6} GNT#3 GND REQ# S2_PAR 17A 17B S2_PAR {6} GNT# GND pPCLK3 S2_LOCK# 16A 16B S2_LOCK# {6} PCI_RST# +VIO(3.3V) CLK S2_STOP# 15A 15B S2_STOP# {6} RST# GND S2_FRAME# 14A 14B S2_FRAME# {6} 3.3Vaux RSV PCI_N12P0 S2_TRDY# S2_TRDY# {6} PCI_12P0 KEYWAY S2_IRDY# S2_IRDY# {6} 11A RSV PRSNT2# 11B 10A 10B REQ#3 +VIO(3.3V) RSV GNT#3 REQ#3 {3,8} 9A RSV PRSNT1# 9B GNT#3 {3,8} 8A 8B pINTC# pINTB# +5V INTD# pINTA# pINTD# 7A 7B pINTD# {3,4,5,6,8} pINTD# INTC# INTB# pINTC# 6A 6B pINTC# {3,4,5,6,8} INTA# +5V C342 C343 pINTB# 5A 5B pINTB# {3,4,5,6,8} +5V +5V (1) (1) pINTA# 4A 4B pINTA# {3,4,5,6,8} S2_AD23 R343 0 S3_IDSEL TDI TDO 0.01uF 0.01uF IDSEL3 3A 3B S2_AD27 R342 NL TMS GND PCI_RST# 2A +12V TCK 2B PCI_RST# {3,4,5,6,8} PCI-X,FM, Straddle-mount pPME# 1A TRST# -12V 1B pPME# {3,4,5,6,8} pPCLK3 PPCLK3 pPCLK3 {3} pPCIXCAP pPCIXCAP {4,5,6,8,11}

M66EN Place within 0.25 M66EN {3,4,5,6,8,11} inch of connector C344 (2)

0.01uF

(1) PCI Specification, Rev 2.3, Section 4.3.7

A (2) PCI Specification, Rev 2.3, Section 7.7.7 A

PLX Technology, Inc. 870 Maude Avenue Sunnyvale, CA 94085 www.plxtech.com

TitleTitle PEX 8114 Forward Bridge RDK - PCI Slot 3

SizeSize Document Document Number Number Rev Rev C 91-0052-300-A 300

Date:Date:Tuesday, December 18, 2007 Sheet Sheet 713of 5 4 3 2 1 5 4 3 2 1

PCI_3P3 PCI_3P3

Side B Side A

{3,4,5} AD[63:0] AD63 R346 AD63 R345 AD62 AD33 AD32 AD62 1 8 4 5 D AD61 AD35 AD34 D AD61 2 7 3 6 AD60 AD37 AD36 AD60 3 6 2 7 AD59 AD39 AD38 AD59 4 5 1 8 AD58 AD58 AD57 8.2K AD57 8.2K AD56 AD56 AD55 R347 AD55 AD54 AD40 AD54 R348 4 5 AD53 AD41 AD42 AD53 1 8 3 6 AD52 AD43 AD44 AD52 2 7 2 7 AD51 AD45 AD46 AD51 3 6 1 8 AD50 AD47 AD50 4 5 AD49 8.2K AD49 AD48 8.2K AD48 AD47 AD48 R350 8.2K AD47 AD46 AD49 R349 8.2K AD46 AD45 AD50 R352 8.2K AD45 AD44 AD51 R351 8.2K AD44 AD43 AD43 AD42 AD42 AD41 AD41 AD40 R355 AD40 AD39 AD52 AD39 R353 4 5 AD38 AD53 AD54 AD38 1 8 3 6 AD37 AD55 AD56 AD37 2 7 2 7 AD36 AD57 AD58 AD36 3 6 1 8 AD35 AD59 AD35 4 5 AD34 8.2K AD34 AD33 AD33 8.2K AD32 R356 AD32 AD31 AD60 AD31 R354 4 5 AD30 AD61 AD62 AD30 1 8 3 6 AD29 AD63 pPAR64 AD29 {3,4,5} AD63 2 7 2 7 AD28 CBE#4 CBE#5 AD28 3 6 1 8 AD27 CBE#6 AD27 4 5 AD26 8.2K AD26 AD25 AD25 8.2K AD24 CBE#7 R357 8.2K C AD24 C AD23 AD23 AD22 pREQ64# R359 8.2K AD22 AD21 pACK64# R358 8.2K AD21 AD20 AD20 AD19 AD19 AD18 AD18 AD17 AD17 AD16 M66EN R360 8.2K AD16 AD15 AD15 AD14 AD14 R361 AD13 pSERR# AD13 1 8 AD12 pPERR# AD12 2 7 AD11 pLOCK# AD11 3 6 AD10 pSTOP# V3.3 AD10 4 5 AD9 AD9 AD8 AD8 8.2K AD7 AD7 AD6 AD6 AD5 R110 AD5 AD4 JP18 1.00K AD4 2 3 AD3 1 1% AD3 R363 AD2 pDEVSEL# AD2 1 8 AD1 pTRDY# AD62 TVAL AD1 2 7 AD0 pIRDY# AD0 3 6 pFRAME# {3,4,5} CBE#[7:0] 4 5 CBE#7 R111 CBE7# CBE#6 R574 C413 1.00K CBE6# 8.2K CBE#5 NL 10 pF 1% CBE5# CBE#4 CBE4# CBE#3 CBE3# CBE#2 CBE2# CBE#1 pPME# R364 56K CBE1# {3} pAD62 CBE#0 CBE0#

pPAR64 {3,4,5} pPAR64 PAR64 pACK64# NOTE: If the TVAL test fixture is not going to be {3,4,5} pACK64# ACK64# R365 B pREQ64# pINTD# B {3,4,5} pREQ64# REQ64# 1 8 used, JP18 is not populated and R574 is populated. pINTC# 2 7 pINTB# 3 6 pDEVSEL# pINTA# {3,4,5} pDEVSEL# DEVSEL# 4 5 pSERR# {3,4,5} pSERR# SERR# pPERR# {3,4,5} pPERR# PERR# 8.2K pPAR {3,4,5} pPAR PAR pLOCK# {4,5} pLOCK# LOCK# pSTOP# {3,4,5} pSTOP# STOP# pFRAME# {3,4,5} pFRAME# FRAME# pTRDY# {3,4,5} pTRDY# TRDY# R545 pIRDY# REQ#_REQ#0 {3,4,5} pIRDY# IRDY# 1 8 REQ#1 2 7 REQ#_REQ#0 REQ#2 {3,4} REQ#_REQ#0 REQ# 3 6 GNT#_GNT#0 REQ#3 {3,4} GNT#_GNT#0 GNT# 4 5 pINTD# {3,4,5,6,7} pINTD# INTD# 8.2K pINTC# {3,4,5,6,7} pINTC# INTC# pINTB# {3,4,5,6,7} pINTB# INTB# pINTA# {3,4,5,6,7} pINTA# INTA# pPME# {3,4,5,6,7} pPME# PME# PCI_RST# {3,4,5,6,7} PCI_RST# RST# M66EN {3,4,5,6,7,11} M66EN M66EN pPCIXCAP PCIXCAP {4,5,6,7,11} pPCIXCAP GNT#1 {3,5} GNT#1 GNT1# GNT#2 {3,6} GNT#2 GNT2# GNT#3 {3,7} GNT#3 GNT3# REQ#1 {3,5} REQ#1 REQ1# REQ#2 {3,6} REQ#2 REQ2# REQ#3 {3,7} REQ#3 REQ3#

A A

PLX Technology, Inc. 870 Maude Avenue Sunnyvale, CA 94085 www.plxtech.com

TitleTitle PEX 8114 Forward Bridge RDK - PCI Termination

SizeSize Document Document Number Number Rev Rev C 91-0052-300-A 300

Date:Date:Tuesday, December 18, 2007 Sheet Sheet 813of 5 4 3 2 1 5 4 3 2 1

D If an ATX power supply is plugged in to P16, D PCI_3P3 PCI_5P0 PCI_N12P0 PCI_12P0 PCI_ONBRD_PWR_OFF# is pulled low and the on-board PCI power generation circuitry is turned off.

V3.3 P16

11 1 12 2 R170 V3.3 13 3 3.3K 14 4

D 15 5 Q9 16 6 PCI_ONBRD_PWR_OFF# BSS138 17 7 G 18 8

S 19 9 R40 20 10 10K -12V ATX_20 ST L3 10uH C24 1uF L5 10uH 150 mA PCIN12P0

U8 ATX POWER CONNECTOR

R29 10uF

5 VIN SW 1

+ C25 + 84.5K + C26 PCI_5P0 4.7uF 4 3 1 SHDN# NFB D6 PCI_N12P0

R26 C GND 10.0K MBRS120T3 3P3 C 2

2 1% Q2 LT1931ES5 0.005 Q3 R164 1 5 0.005 S D R165 2 S D 6 1 S D 5 0.5% 3 7 2 6 S D 0.5% S D D 8 3 S D 7 4 G D 8 4 G IRF7470 IRF7470 12P0

12P0 U128 PCIN12P0 1 16 M12VIN M12VO C406 0.033uF 2 FLTN M12VG 15 3 3V5VG 12VG 14 4 VCC GND 13 3 1 5 3 1 5 5 12 C407 0.033uF C82 C83 12VIN 12VO 6 3VISEN 5VISEN 11 7 10 47uF 47uF 3VS 5VS 8 OCSET PWRON 9 NOTE: If YNS12S16-0 4 2 6 4 2 6 HIP1011A is used for U127, C408 R166 6.04K Do Not install Q10 0.033uF 1% C405 PCI_POWRGD {11} and R546, and U127 5V Install R554. R544 6 2 16 Amp 100pF 75K VIN SENSE

PCI5P0 R554 NL 1 ON#/OFF VOUT 4 R546 18K 3 1 Q10 B MMBT3904LT1 B 5 GND TRIM 3 2 YNS12S16-D R90 1.47K 1%

PCI_ONBRD_PWR_OFF#

A A

PLX Technology, Inc. 870 Maude Avenue Sunnyvale, CA 94085 www.plxtech.com Title Title SizePEX Document 8114 Forward Number Bridge RDK - PCI Power Rev Size Document Number Rev C Date:91-0052-300-A Sheet 300 Date:Tuesday, December 18, 2007 Sheet 913of 5 4 3 2 1 5 4 3 2 1

D D

3P3 12P0

C C

P17 TP1 B32 GND RSVD A32 1 B31 A31 TP2 PRSNT2# GND 1 B30 RSVD PERn3 A30 PB_PETn3 {3} B29 GND PERp3 A29 PB_PETp3 {3} {3} PB_PERn3 B28 PETn3 GND A28 {3} PB_PERp3 B27 PETp3 GND A27 B26 GND PERn2 A26 PB_PETn2 {3} B25 GND PERp2 A25 PB_PETp2 {3} {3} PB_PERn2 B24 PETn2 GND A24 B23 A23 R146 {3} PB_PERp2 PETp2 GND B22 A22 PB_PETn1 {3} 0 GND PERn1 B21 GND PERp1 A21 PB_PETp1 {3} B20 A20 {3} PB_PERn1 PETn1 GND TP3 {3} PB_PERp1 B19 PETp1 RSVD A19 1 B18 GND GND A18 B17 PRSNT2# PERn0 A17 PB_PETn0 {3} B16 GND PERp0 A16 PB_PETp0 {3} {3} PB_PERn0 B15 PETn0 GND A15 {3} PB_PERp0 B14 PETp0 REFCLK- A14 REFCLK_n {3} B13 A13 TP4 GND REFCLK+ REFCLK_p {3} 1 B12 RSVD GND A12

B11 WAKE# PERST# A11 PERST#_CONN {11} B10 A10 R87 0 3.3Vaux +3.3V {3} JTAG_TRST# B9 TRST# +3.3V A9 B8 A8 R85 0 +3.3V TMS R63 0 JTAG_TMS {3} B7 GND TDO A7 JTAG_TDO {3} B6 A6 R84 0 SMDAT TDI R86 0 JTAG_TDI {3} B5 SMCLK TCK A5 JTAG_TCK {3} B4 A4 TP5 GND GND 1 B3 RSVD +12V A3 B2 +12V +12V A2 B1 A1 B +12V PRSNT1# B PCI Express x4 edge connector

PRSNT#

A A

PLX Technology, Inc. 870 Maude Avenue Sunnyvale, CA 94085 www.plxtech.com Title Title SizePEX Document8114 Forward Number Bridge RDK - PCI Express/AUX IO Rev Size Document Number Rev C Date:91-0052-300-A Sheet 300 Date:Tuesday, December 18, 2007 Sheet 10of 13 5 4 3 2 1 5 4 3 2 1

V3.3

{9} PCI_POWRGD 3P3 3P3 U137

ARBITER-ON 5 VCC NC 1 DS15 2 R24 R39 R560 390 NOT A 4 Y GND 3 390 390 NC7SZ04P5X Green

D 3P3 D U138 PCI Power On DS7 DS9 PEX 8114 Power On TRANSPARENT-MODE-ON 5 VCC NC 1 Green Green DS16 2 R561 390 NOT A 4 Y GND 3 NC7SZ04P5X Green

3P3 U139

PCLK-FDBK-ON 5 VCC NC 1 DS17 2 R562 390 NOT A V3.3 4 Y GND 3 NC7SZ04P5X V3.3 Green RN1 8 1 PLL-BYPASS-ON 7 2 DS18 6 3 DS6 R563 390 R23 390 5 4 {3} LANE_GOOD3# Green Green 5.1K DS2 R12 390 Solderside {3} LANE_GOOD2# Green

DS4 SW9 R13 390 {3} LANE_GOOD1# Green {3} STRAP_ARB 5 4 {3} STRAP_TRAN 6 3 7 2 DS5 {3} PCLK_FDBK R15 390 8 OPENOPEN 1 {3} LANE_GOOD0# {3} STRAP_PLL_BYPASS# Green SW DIP-4

C C

V3.3

V3.3 V3.3 R46 3.3K Normally Open switch U133 R107 8 {12} PERST#_PWRGD_MAN V3.3 390 1 7 1% R14 1S 1A 10.0K 3P3 2 VCC 6 V3.3 2B 1B

SW7 U15 2 RN2 3 5 2A GND 2S 1 4 3 5 DS3 V3.3 MR# VCC RED LED FSA1256 2 3 U141 8 1 4 PCI-X EM Specification, 7 2 B3S-1002 Rev 2.0, Section A.1.2. RESET# 1 1 A VCC 5 6 3 2 5 4 R11 B AND 1 56K PCIXCAP {3} 3 GND Y 4 PB_PERST# {3} 4 SRT GND 2 5.1K NC7SZ08P5X PCIXCAP R8 0 MAX6412 Solderside pPCIXCAP {4,5,6,7,8} C42 C3 1000pF SW10 0.01uF PCI_SEL 3 msec timeout 1 OPEN 8 3P3 3P3 2 7 PCIX_SEL B M66EN B {10} PERST#_CONN 3 6 PCI_SEL100 M66EN {3,4,5,6,7,8} 4 5 PCI_SEL100 {3} 16 PCI_50 DS23 390 R569 3P3 SW DIP-4 U140 Green M66EN PCI_66 DS24 390 R570 VDD PCIX_SEL Green 3 BA Q3A# 7 PCI_SEL100 2 6 PCI_25 DS25 390 R571 3P3 3P3 R108 AA Q2A# Green 1 EA# Q1A# 5 390 3P3 4 PCI_33 DS26 390 R572 Q0A# Green U136 PCIX_50 DS19 390 R564 13 BB Q3B# 9 R48 1 5 14 10 Green 2 NC VCC AB Q2B# PCI_SEL 2 15 11 PCIX_66 DS20 390 R565 3.3K A NOT EB# Q1B# DS8 3 4 12 Green SW8 U16 RED LED GND Y Q0B# PCIX_100 DS21 390 R566 GND 1 4 MAN_POWR_CYCLE 3 5 NC7SZ04P5X Green MR# VCC MC14556BD 2 3 PCIX_133 DS22 390 R567 8 Green B3S-1002 1 RESET# 1 PB_POWR_CYCLE {12}

4 SRT GND 2 MAX6414 C99

1000pF 3 msec timeout

A A TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP22 CLOSED=0 PCI_SEL OPEN CLOSED CLOSED PCIX_SEL DON'T CARE OPEN CLOSED OPEN=1 PLX Technology, Inc. M66EN PCI_SEL100 870 Maude Avenue Sunnyvale, CA 94085 CLOSED CLOSED PCI 33 PCIX 66 PCIX 133 Title Ground Reference Posts for Test Instruments. www.plxtech.com CLOSED OPEN PCI 25 PCIX 50 PCIX 100 Title Size Document Number Rev OPEN CLOSED PCI 66 PCIX 66 PCIX 133 PEX 8114 Forward Bridge RDK - Switches/Indicators Size Document Number Rev OPEN OPEN PCI 50 PCIX 50 PCIX 100 C Date:91-0052-300-A Sheet 300

Date:Tuesday, December 18, 2007 Sheet 11of 13 5 4 3 2 1 5 4 3 2 1

D D 3P3 V3.3

F10

NL Q5 S D G V3P3_VIO_ON BOARD POWER VTT_EARLY FDN339AN SEQUENCER 3P3 V1.0_CORE_EARLY

R105 R100 R106 28.0K 3.16K 3.16K 1% 1% 1%

PBRIDGE_1P0_CORE 3P3 V1.0_CORE_EARLY

R104 R98 R93 {11} PB_POWR_CYCLE 3.3V to 1.0V LINEAR C176 7.50K 7.50K 7.50K F3 1% 1% 1% REGULATOR 0.1uF U14 NL U9 Q7 23 20 MIC49300 VDD UVLO_A S UVLO_B 12 C C137 3300pF C 4 VIN VOUT 5 D 1 ENABLE UVLO_C 17 G V1P0_CORE_ON 11 14 4.29 msec NC UVLO_D 2 VBIAS ADJ 1 R101 FDN339AN 1.00K C129 2200pF DON_VIO 21 2 V3P3_VIO_ON THERM GND DLY_ON_A GATE_A 1% 2.86 msec DON_VTT 8 5 VTT_ON DON_CORE DLY_ON_B GATE_B V1P0_CORE_ON 16 DLY_ON_C GATE_C 6 6 3 15 7 C133 1500pF DLY_ON_D GATE_D 3P3 1.95 msec R102 DOFF_VIO 18 22 3.3K R163 9.09K DOFF_VTT DLY_OFF_A SYSRST# 13 DLY_OFF_B 1% C130 0.1uF DOFF_CORE 3 24 130 msec DLY_OFF_C RESET# PERST#_PWRGD_MAN {11} PIN 6 IS A THERMAL PAD 4 DLY_OFF_D NC 9 UNDERNEATH U9. 19 10 C134 1000pF NC GND THERM ISL6123 25 C135 1500pF VTT_EARLY PBRIDGE_VTT

F9 C136 2200pF PIN 25 IS A THERMAL PAD UNDERNEATH U12. NL Q6 3.3V to 1.5V LINEAR S D REGULATOR G VTT_ON 3

FDN339AN C41 2 R91 U13 10uF 50K MAX1806 B B 1 8 IN OUT 1 2 IN OUT 7 R94 390 3 POK SET 6 4 R89 SHDN# 12.4K GND 1% C81 1uF 5

R103 1 2 3 JUMPER3 49.9K JP7 1%

VTT can be adjustable, or set to 1.5 volts, by the jumper.

A A

PLX Technology, Inc. 870 Maude Avenue Sunnyvale, CA 94085 Title www.plxtech.com Title SizePEX Document 8114 Forward Number Bridge RDK - Power Rev Size Document Number Rev Date:C 91-0052-300-A Sheet 300

Date:Tuesday, December 18, 2007 Sheet 12of 13 5 4 3 2 1 5 4 3 2 1

D D CAP FOOTPRINTS

1206_LoVolt - 0.87 nH 12P0

3 1 5 3 1 5 3 1 3 1 3 1 3 1 C53 C54 C65 C66 C73 C74

10uF 10uF 0.1uF 0.1uF 1000pF 1000pF 4 2 6 4 2 6 4 2 4 2 4 2 4 2

1206_HiVolt 0603_2VIA 1206_HiVolt - 0.94 nH

3P3

3 1 5 3 1 5 3 1 3 1 3 1 3 1 C45 C46 C67 C68 C79 C80 0603_4VIA - 0.58 nH 10uF 10uF 0.1uF 0.1uF 1000pF 1000pF 4 2 6 4 2 6 4 2 4 2 4 2 4 2

C C 1206_LoVolt 0603_2VIA

0603_2VIA - 0.78 nH

PBRIDGE_1P0_CORE

3 1 5 3 1 5 3 1 5 3 1 3 1 3 1 C49 C50 C51 C320 C321 C322 C319 C303 C302 C301 C300 C281 C280 C279 C283

10uF 10uF 10uF 0.1uF 0.1uF 0.1uF 0.022uF 0.022uF 0.022uF 0.022uF 0.022uF 1000pF 1000pF 1000pF 1000pF 4 2 6 4 2 6 4 2 6 4 2 4 2 4 2

1206_LoVolt 0603_2VIA 0402

3 1 5 3 1 5 3 1 5 3 1 5 3 1 3 1 3 1 3 1 C52 C55 C56 C63 C323 C324 C325 C326 C308 C307 C306 C305 C304 C287 C286 C285 C284 C288

B 10uF 10uF 10uF 10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.022uF 0.022uF 0.022uF 0.022uF 0.022uF 1000pF 1000pF 1000pF 1000pF 1000pF B 4 2 6 4 2 6 4 2 6 4 2 6 4 2 4 2 4 2 4 2

1206_LoVolt 0603_2VIA 0402

V3.3

3 1 5 3 1 5 3 1 5 3 1 5 3 1 3 1 3 1 3 1 C57 C58 C59 C64 C327 C328 C329 C330 C313 C312 C311 C310 C309 C292 C291 C290 C289 C293

10uF 10uF 10uF 10uF 0.1uF 0.1uF 0.1uF 0.1uF 0.022uF 0.022uF 0.022uF 0.022uF 0.022uF 1000pF 1000pF 1000pF 1000pF 1000pF 4 2 6 4 2 6 4 2 6 4 2 6 4 2 4 2 4 2 4 2

1206_LoVolt 0603_2VIA 0402

PBRIDGE_VTT

3 1 5 3 1 5 3 1 3 1 C60 C61 C331 C332 C318 C317 C316 C315 C296 C295 C294 C298

10uF 10uF 0.1uF 0.1uF 0.022uF 0.022uF 0.022uF 0.022uF 1000pF 1000pF 1000pF 1000pF 4 2 6 4 2 6 4 2 4 2

1206_LoVolt 0603_2VIA 0402

A A

PLX Technology, Inc. 870 Maude Avenue Sunnyvale, CA 94085 Title www.plxtech.com Title SizePEX 8114 DocumentForward Bridge Number RDK - Power Decoupling Rev Size Document Number Rev C Date:91-0052-300-A Sheet 300

Date:Tuesday, December 18, 2007 Sheet 13of 13 5 4 3 2 1