Integration of Molecular Components Into Silicon Memory Devices

Integration of Molecular Components into Silicon Memory Devices

by Werner G. Kuhr

onsumer and business appetite for electronic devices drives the C semiconductor industry’s need for miniaturization. The state of the art of semiconductor devices now has critical feature dimensions substantially less than 0.1 µm.1 While many devices can be manufactured effectively at such dimensions through the continued extension and optimiza- tion of existing process technologies, it is uncertain at what point along the path of miniaturization such devices, which rely on the bulk properties of materials, will retain the required func- tional characteristics. Much work has been done in the field of molecular electronics, where many investigators have attempted to mimic transistor properties in molecular systems.1 While FIG. 1. DRAM array (left), with examples of trench and stacked cell geometries for the DRAM capacitor. the creation of a molecular transistor has received the lion’s share of atten- tion (and criticism),2 transistor fabrication is expected to scale to 10 nm dimensions, albeit with a great deal of stored in each device (which, in turn, is the memory industry to develop three- effort.3 Indeed, the component that is based on the voltage and the capaci- dimensional structures to provide most urgently in need of replacement tance available), and the leakage current, enough capacitive area to store sufficient for most semiconductor devices is the along with the number of memory ele- charge to allow reliable operation. With 2 charge storage device, i.e., the capacitor. ments that must be refreshed in each a SiO2 capacitor, almost 5 µm of surface Almost all existing memory devices cycle. Thus, a key design feature in the area is necessary to store ~100 fC of utilize charge storage as the mechanism miniaturization of DRAM circuit ele- charge. Two of the most commonly of information storage [including ments is the amount of available charge employed strategies to increase the effec- dynamic random access memory in each capacitor as feature size shrinks. tive area of the capacitor include trench (DRAM), FLASH RAM, and one-transis- There is increasing evidence that the or stacked structures (Fig. 1). In the tor static RAM (1T SRAM)]. In particu- materials used in existing devices are trench design, a hole is drilled into the lar, DRAM consists of large arrays of unable to scale effectively with the other silicon substrate at the critical dimen- storage cells, each of which consists of circuit elements used in DRAM circuits. sion, and the capacitor is built through one capacitor and one transistor, where For example, a DRAM capacitor in an deposition of the dielectric on the walls the charge stored on the capacitor indi- efficient memory array must occupy a of the cylindrical hole. This can increase cates the bit level (Fig. 1). Due to the surface area corresponding to less than the effective area to over 5 µm2 and pro- combination of stringent requirements 4F2 (allowing for a 6F2 total cell area), vide sufficient capacitance for a reliable for data fidelity for RAM (which where F is the minimum critical feature device, but at significant manufacturing impacts the minimum amount of sig- size of the device. In a 256 MB DRAM cost. In this device, the aspect ratio nal that must be available from each manufactured at the state of the art in a (depth/width) of the trench can be over cell for sensing, currently ~100 fC or production environment, F is 0.11 µm, 100, leading to tremendous process ~600,000 electrons) and that capacitors and this translates to a capacitor area of complexity and cost. Fabrication of the are imperfect, leaky devices (the charge roughly 0.048 µm2, and this cell must be DRAM capacitor in existing devices on an existing DRAM capacitor decays able to operate at less than 2 V. The most already requires over one-third of the rapidly, ~100 ms in existing devices), commonly used dielectric materials used process steps, and this process complexi- the data stored in each location must be for DRAM capacitors have a charge den- ty will increase even more as the aspect refreshed periodically by reading it and sity of 1-2 µC/cm2, and at these dimen- ratio becomes larger with even smaller then writing it back again. The frequen- sions hold only 1 fC, (roughly 6000 elec- devices. As critical dimensions continue cy at which this refresh must be repeat- trons). to shrink, it is likely that this process ed is determined by many factors, Therefore, a tremendous amount of cannot reasonably continue. As dis- including the magnitude of charge time and effort has been expended by cussed in this article, a DRAM based on

34 The Electrochemical Society Interface • Spring 2004 Table I. Criteria for Incorporation of Molecules in CMOS • The charge storage properties are dependent on the molecule, not Storage Devices. the underlying substrate.4-11 • The size of the device dictates the Property Implementation number of molecules (proportional to area). Chemical stability ...... Delocalized cationic charge • Charge is stored in stable redox states of molecules, leading to Thermal stability ...... Decomposition > 400° C high charge density (more than Endurance ...... Endurance > 1012 to 1015 cycles ten times higher than convention- al SiO capacitors).4-10 Read/write speed ...... t = 1/k < 10 ns 2 R/W eff • Charge-retention times are also a Charge retention ...... t1/2 > 10 s molecular property, not dependent on the leakage characteristics 2 Charge density...... µ = 10 µC/cm or higher of the gating device, and are in the Self-assembly and ...... Selective, covalent bond formation of range of minutes to hours self-alignment molecules to specific substrate (>10,000 times that of semiconductors).9 • Molecules can be attached at high surface coverage (in the range of 1.0 x 10-10 mol cm-2) using small amounts of materials.8-10 • Temperatures as high as 400°C can be used during fabrication with no degradation of the molecules. This result is of importance in that many processing steps in fabricat- ing complementary metal-oxide- semiconductor (CMOS) devices entail high-temperature processing, even at the back end of the line.4 • Devices using porphyrins applied in this manner have been tested for endurance, and no sign of degradation of any aspect of performance was observed after 1012 cycles.4 • Multiple bits can be stored in a given memory location using the distinct oxidation states of the molecules, which can lead to high- FIG. 2. Properties of molecules used for charge storage. er array densities.8 • This type of molecular memory should scale to near molecular dimensions, because electronic molecular properties is more suitable for adequate stability, endurance, and oper- properties are intrinsic to the mol- smaller feature sizes. ating properties to meet such require- ecular structure.4-11 ments, and only recently has it been Charge Storage in demonstrated that some molecular Attachment of Redox Monolayers materials may be able to withstand these Molecules to Silicon demanding criteria.4 Some redox sys- Devices Recently, molecules that may be suit- tems have been investigated for use in able for use in semiconductor devices the fabrication of molecular-based infor- The fabrication of stable and reliable have been the subject of much atten- mation storage systems. These systems CMOS/molecular devices requires the tion.4,5 To be able to serve in this role, employ metallocene, porphyrin, and covalent attachment of an electroactive molecular components must remain triple-decker sandwich coordination molecule (such as a porphyrin or a fer- robust under the same daunting condi- compounds as the charge-storage ele- rocene) to a device substrate (e.g., Si). tions that all existing semiconductor ments covalently attached to metals and Attachment of molecules to silicon is 4-11 materials already endure including high- device-grade silicon (Fig. 2). accomplished through covalent linkage temperature processing steps during These molecules exhibit redox char- chemistries involving the formation of 5-11 manufacture and demanding require- acteristics that make them amenable for Si-C or Si-O bonds. It is important ments for operation (see Table I). There use as multibit information-storage to emphasize that the stability of the has been considerable skepticism media. Some key aspects of this technol- bond formed between the substrate and whether molecular materials possess ogy are reviewed below. the redox molecule will dictate the

The Electrochemical Society Interface • Spring 2004 35 FIG. 3. Hybrid CMOS/molecular DRAM cell.

thermal and electrical stability of the lowed by deposition of a metal layer, charge-retention behavior on the sub- self-assembled monolayer (SAM). For which is evaporated or sputtered on to strate size or material, but a strong example, thiol/gold chemistry, which complete the cell (Fig. 3). This material dependence on the composition and size has been used extensively in many acad- can be any well-behaved electrochemical of the tether separating the redox site emic labs for the characterization of counter electrode material such as cop- from the surface.9,10 The charge reten- monolayer redox systems, does not proper, silver, etc. tion time could be increased by an order vide sufficient stability for a robust, man- of magnitude (to over 1000 s) for the ufacturable solution. A number of sim- Characterization of same redox species at the same surface, ple, rapid, material-conservative meth- Redox SAMs in Silicon merely by lengthening the tether by ods have been examined in our laborato- Devices three carbons.9 ries to attach electroactive molecules to The instantaneous current (Fig. 3, silicon and many other substrates.5-11 right) represents the instantaneous reduc- The electrochemical properties of The types of molecules and linkers span tion of the charge stored in the oxidized redox molecules attached to silicon a broad range (Fig. 2) and many of these SAM, and the time constant reflects either devices can easily be monitored with tra- procedures have been published previ- the t of the cell (as when an electrolyte ditional electrochemical methods such RC ously.7-10 The procedures vary consider- probe is used with a 10,000 µm2 cell, as cyclic voltammetry or ac impedance.9 ably depending on the type of molecule curve A) or the time constant of the A more relevant measurement for mem- and the substrate used for attachment. amplifier used for measurement (as ory devices involves the determination A prototype CMOS/molecular DRAM shown for the “stacked capacitor”, curve of the charge retention properties of the capacitor cell can be manufactured via a B). This signal can be integrated to calcu- molecular “capacitor”. In this measure- straightforward modification of the late the total charge remaining, which, in ment, the porphyrin SAM is oxidized DRAM architecture, where two metal or turn, is proportional to the number of with a short positive voltage pulse semiconductor layers are separated by an molecules that remain oxidized on the (similar to chronoamperometry; roughly electrolyte layer (see Fig. 3). Here, the surface while the circuit is open. This 5 RC time constant (t ) of the cell) active area of the molecules is lithograph- RC technique, termed open-circuit potential that is ~200 mV above the formal poten- ically defined by patterning a field oxide amperometry (OCPA),9 has been used to tial of the desired state. The applied region over the conductive substrate. measure charge-retention characteristics potential is disconnected from the Many redox systems, some comprised of of many redox species. This technique can counter electrode for a period of time surprisingly large molecular architectures, provide voltammetric information as well and this disconnection time is varied to have been found to form excellent quali- (OCPV),9 simply by stepping the write evaluate the charge-retention properties ty SAMs on silicon.8-10 Once the mole- voltage to incrementally larger potentials, of the cell. The charge-retention time can cules are attached, a standard electro- and measuring the charge retained (Fig. 3, be measured by successively changing chemical cell (which uses a liquid elec- left). As shown, the OCPV signal looks the disconnect time up to a point where trolyte and a silver reference electrode) much like a steady-state voltammogram, essentially all the molecules that were can be used for characterization.4-10 where the E of each state is clearly initially oxidized have decayed back to 1/2 Alternatively, we can create devices defined. In other experiments, we have the reduced state.5,9 Measurement of the which closely resemble capacitor struc- characterized the ultimate speed at which charge retention times of some redox tures by substituting a thin layer of poly- the charge can be written or read. For species has indicated several clear trends. mer electrolyte for the dielectric material most systems that we have studied, the There appears to be little dependence of conventionally used in capacitors, fol- intrinsic electron-transfer rate constant, or

36 The Electrochemical Society Interface • Spring 2004 FIG. 4. Photomicrograph of 1 MBit ZettaCore hybrid CMOS/molecular DRAM.

ko, is sufficiently fast to allow read/write ry cells in a row, while each bit line is must serve many purposes, i.e., demon- times of a few nanoseconds with a modest connected to the drains of the memory stration DRAM as well as R&D test plat- overpotential.9 cells in a column. Peripheral circuits, form. We want to examine characteris- consisting of row and column decoders, tics of many different molecules, for High-density hybrid voltage/current/timing generators, and example, by altering the length and type molecular-silicon DRAM sense amplifiers, are all implemented of linker to the porphyrin or by altering with CMOS to provide a sensing circuit the charge storage properties of the mol- The true commercial viability of any with timing in the nanosecond regime. It ecule. This device gives us tremendous alternative approach to traditional semi- is important to note that the area and flexibility in characterizing and optimiz- conductor process flow can be demon- the RC delay can be significantly reduced ing the properties of the charge storage strated only through fabrication of in future CMOS technologies, allowing molecules as well as the peripheral cir- devices at densities and scales that for even faster operation. While the cuitry, and should allow us ultimately to approach commercially relevant scales. process that creates the molecular mem- address many different memory devices We have fabricated a prototype 1 Mbit ory array is proprietary, it consists of less and configurations. DRAM chip, which incorporates 4 256 than 10% of the number of steps used in Kbit arrays of hybrid silicon/molecular the commercial fabrication of DRAM References capacitors (Fig. 4). While the CMOS cir- trench capacitors, and is completely cuits were fabricated on a 0.35 µm compatible with fabrication tools used in 1. K. S. Kwok and J. C. Ellenbogen, Materials Today, p. 28 (2002). process flow (to avoid the extremely high commercial foundries today. Each array within this device includes a row of stan- 2. R. F Service, Science, 302, 556 (2003). mask costs associated with smaller litho- 3. International Technology Roadmap for graphy nodes), the DRAM capacitors dard SiO2 capacitors, so that we can sim- Semiconductors (ITRS), Semiconductor within these arrays were designed with ulate, test, and compare their perfor- Industry Association, San Jose, CA (2002). an area of 0.5 µm2, roughly an order of mance with our molecular memory 4. Z. Liu, A. A. Yasseri, J. S. Lindsey, and D. F. magnitude smaller in area than those in structures. Full testing of this device is Bocian, Science, 302, 1543 (2003). existing commercial devices, yet are able currently underway (e.g., including 5. K. M. Roth, N. Dontha, R. B. Dabke, D. T. Shmoo to determine operating margins, Gryko, C. Clausen, J. S. Lindsey, D. F. Bocian, to store the same amount of charge as and W. G. Kuhr, J. Vac. Sci. Technol. B, 18, those larger devices. Because the under- bit maps to differentiate single bit defects 2359 (2000). lying substrate for a hybrid molecular-sil- from gross problems, validation on com- 6. C. Clausen, D. T. Gryko, A. A. Yasseri, J. R. icon DRAM can be constructed through mercial memory testers, and verification Diers, D. F. Bocian, W. G. Kuhr, and J. S. use of standard CMOS fabrication tech- of a large number of ac and dc parame- Lindsey, J. Org. Chem., 65, 7371 (2000). nology for all other circuit structures, the ters), and initial results are encouraging. 7. D. T. Gryko, P. C. Clausen, and J. S. Lindsey, J. Org. Chem., 64, 8635 (1999). only variation in the process occurs at The overall performance of the device is 8. D. T. Gryko, J. Li, J. R. Diers, K. M. Roth, D. the back end of the line, where the expected to be equivalent to or exceed F. Bocian, W. G. Kuhr, and J. S. Lindsey, J. hybrid molecular/silicon structures are high-speed DRAM devices on the market Mater. Chem., 11, 1162 (2001); K-H. formed. today. Schweikart, V. L. Malinovskii, J. R. Diers, A. The storage array consists of memory The fabrication of this kind of test A. Yasseri, D. F. Bocian, W. G. Kuhr, and J. S. cells arranged in a typical array of tran- device is an important step in the devel- Lindsey, J. Mater. Chem., 12, 808 (2002). 9. K. M. Roth, Z. Liu, D. T. Gryko, C. Clausen, sistors and capacitors used in DRAM, opment of any new technology, and rep- J. S. Lindsey, D. F. Bocian, and W. G. Kuhr, A. each accessed by activation of the proper resents the first step in the process of C. S. Symp. Series, 844, 51 (2003); K. M. Roth, set of word lines and bit lines (Fig. 4). commercial development. It is important J. S. Lindsey, D. F. Bocian, and W. G. Kuhr, Each word line is connected to the tran- to balance the flexibility and robustness Langmuir, 18, 4030 (2002); K. M. Roth, D. T. sistor gating the capacitors of the memo- of the approach, because this device Gryko, C. Clausen, J. Li, J. S. Lindsey, W. G.

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The Electrochemical Society Interface • Spring 2004 37 MOLECULAR COMPONENTS... (continued from previous page)

Kuhr, and D. F. Bocian, J. Phys. Chem. B., 106, 8639 (2002). 10. K. M. Roth, A. A. Yasseri, Z. Liu, V. Malinovskii, K.-H. Schweikart, L. Yu, H. Tiznado, F. Zaera, J. S. Lindsey, W. G. Kuhr, and D. F. Bocian, J. Amer. Chem. Soc., 125, 505 (2003). 11. Q. Li, G. Mathur, M. Homsi, S. Surthi, V. Misra, V. Malinovskii, K.-H. Schweikart, L. Yu, J. S. Lindsey, Z. Liu, R. B. Dabke, A. Yasseri, D. F. Bocian, and W. G. Kuhr, Appl. Phys. Lett., 81, 1494 (2002); Q. Li, S. Surthi, G. Mathur, S. Gowda, M. Kannan, S. Tamaru, J. S. Lindsey, Z. Liu, R. B. Dabke, A. Yasseri, D. F. Bocian, W. G. Kuhr, T. A. Sorenson, R. C. Tenent, and V. Misra, Appl. Phys. Lett., 83, 198 (2003).

About the Author

WERNER G. KUHR is currently Vice President of Research of ZettaCore, Inc. Dr. Kuhr was a member of the chemistry faculty at the University of California, Riverside from 1988 and was promoted to full professor in 1998. His research there focused on the development of micro- and nanoscale techniques for the design and characterization of electrochemical devices. Dr. Kuhr has published over 100 scientific papers, delivered over 100 invited lectures at confer- ences and universities across the world, and has been issued ten U.S. and international patents. He and two academic colleagues founded ZettaCore, Inc. in 1999, and he became Director of Research in 2002. He is also serving on the board of directors of the Society of Electroanalytical Chemistry, and he has been the recipient of a number of awards including a Presidential Young Investigator Award from the National Science Foundation (1989); a Young Investigator Award from the Society of Electroanalytical Chemistry (1993); and the Jubilee Silver Medal from the Chromatographic Society, England (1994). Dr. Kuhr may be contacted at [email protected].

38 The Electrochemical Society Interface • Spring 2004