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Microsoft Powerpoint RAM (Random Access Memory) Speaker: Lung -Sheng Chien Reference: [1] Bruce Jacob, Spencer W. Ng, David T. Wang, MEMORY SYSTEMS Cache, DRAM, Disk [2] Hideo Sunami, The invention and development of the first trench- capacitor DRAM cell, http://www.cmoset.com/uploads/4.1-08.pdf [3] JEDEC STANDARD: DDR2 SDRAM SPECIFICATION [4] John P. Uyemura, Introduction to VLSI circuits and systems [5] Benson, university physics OutLine • Preliminary - parallel-plate capacitor - RC circuit - MOSFET • DRAM cell • DRAM device • DRAM access protocol • DRAM timing parameter • DDR SDRAM SRAM Typical PC organization. Cache: use SRAM main memory : use DRAM Basic organization of DRAM internals DRAM versus SRAM Dynamic RAM Static RAM • Random access: each location in Cost Low High memory has a unique address. The Speed Slow Fast time to access a given location is # of transistors 1 6 independent of the sequence of Density High Low prior accesses and is constant. target Main memory Cache DRAM cell ( 1T1C cell ) Question 1 : what is capacitor? SRAM cell Question 2 : what is transistor? Electric flux electric flux = number of field lines passing though a surface 1 uniform electric field, electrical flux is defined by ΦE =E ⋅ A 2 if the surface is not flat or field is not uniform, then one must sum contributions of all tiny elements of area Φ≈E EAEA1 ⋅∆+ 1 2 ⋅∆+ 2 =∑ EAj ⋅∆→ j ∫ EdA ⋅ Gauss’s Law flux leaving surface = flux entering surface net flux is 0, say Φ=E ∫ E ⋅ dA = 0 Gauss’s Law : net flux through a closed surface is proportional to net charge enclosed by the surface Qenc Φ=E ∫ E ⋅ dA = ε 0 Qenc = net charge enclosed by a closed surface 2 −12 C ε 0 =8.85 × 10F / m permitivity in free space N⋅ m 2 Conductor • When a net charge is added to a conductor, free electrons will redistribute themselves in a short time ( ~1ps ) such that internal electrical field is 0 • If we draw a Gaussian surface (dashed line) inside a conductor, then zero flux implies zero charge inside conductor 1ps= 10 −12 s Gaussian pillbox Example : infinite conducting plate Φ=⋅=E∫ EdAE upper A upper + E down A down = EA Qenc = A σ σ = surface charge density Q σ enc ⇒ metal Φ=E ∫ EdA ⋅ = E = ε0 ε 0 Capacitor: parallel plate [1] Consider two parallel plate (metal) with total charge Q on each plate respectively Q / 2 surface charge density σ = A σ E = ε 0 +++++++++ +++++++++ +++++++++ +++++++++ σ +++++++++ +++++++++ ε 0 2σ d E = σ ε −−−−−−−− 0 ε 0 −−−−−−−− −−−−−−−− −−−−−−−− −−−−−−−− −−−−−−−− σ ε 0 Capacitor: parallel plate [2] In most cases, we don’t care about thickness of the plate. For simplicity we may assume plate has no thickness, say flat sheet , with total charge Q on each plate respectively. Then definition of surface charge density is different Q surface charge density σ = A +++++++++ +++++++++ σ d E = ε −−−−−−−− 0 −−−−−−−− Q Φ=E ∫ EdA ⋅= EA11 + EA 22 = ε 0 σ E1= E 2 = 2ε 0 Capacitance [1] Q( t ) dQ( t ) Kirchhoff’s voltage law: V= V + V V= It( ) ⋅ R V = I() t = R C R C C dt R (resistance) R + + + V C V C (capacitor) − − − T = 0 ,no charge on capacitor T > 0 ,capacitor has some charge V V V > 0 , I t < still charges capacitor V = 0 ,I () 0 = charges the capacitor C () C R R R T >> 1 ,capacitor contains maximum charge + + + + + doesn’t charge capacitor anymore VC = V ,I( t ) = 0 V − − − − − C Capacitance [2] +++++++++ σ d E = V= Ed ε C −−−−−−−− 0 Q ε A capacitance is defined by C = = 0 VC d capacitance is capability of storing charge Electric field is not uniform near edge, called fringe field Qenc 1 1 C ∝ ε 0 since from Gauss’s law Φ=E ∫ E ⋅ dA = , E ∝ ε 0 ε 0 1 2 C ∝ since if we fix total charge Q and area A, then d Q σ σ = is fixed ⇒ E= is fixed ⇒ VEdd= ∝ A ε 0 3 C∝ A since if we fix potential difference V and space d, then V σ E= is fixed ⇒ σ is fixed due to EQAA= ⇒ = σ ∝ d ε 0 Capacitance [3] Suppose we add an insulator into parallel metal plate, what happens on capacitor? dipole insulator +q + d −q − p= qd : dipole moment metal When charge is stored on capacitor, then electric field would separate positive and No charge on capacitor, nothing happens negative charge inside insulator. E0 : field produced by charge on capacitor ED : net field within insulator (dielectric) Ei : field induced by separate charge of insulator Capacitance [4] +q + dipole moment p= qd : dipole moment P = = polarization d unit volume −q − Constitutive equation: P= ε0 χ e E total χe : electric susceptibility P 1 1 EE⇒ E EE total= ext − total= ext ≡ ext ε r : dielectric constant ε0 1+ χe ε r material Dielectric constant Material Dielectric constant vacuum 1 Benzene ( 苯) 2.28 Silicon dioxide 3.9 Diamond 5.7 Ta2O5 25 Salt 5.9 BST >200 Silicon 11.8 TiO2 (Titanium dioxide) 85 Methanol ( 甲醇) 33 ZrO2 23 SrZrO3 30 Al2O3 9.1 La2O3 ( 氧化鑭 ) 16 HfO2 (Hafnium oxide) 25 water 80.1 BaTiO3 ( 鈦酸鋇) 3000~8000 KTaNbO3 34000 Capacitance [5] +++++++++ Q ε A d σ C = = 0 Eext = VC= E ext d 0 ε VC d −−−−−−−− 0 +++++++++ 1 Q ε A d E= E V= Ed C= =ε0 = ε C ε ext C Vr d r 0 −−−−−−−− r C Insulator (dielectric) 1 Keep all geometrical parameters, area A and height d, then we can add insulator to increase capacitance of capacitor 2 Insulator would induce polarization to cancel part of external field such that small voltage gap can store the same charge. In other words, capability of charge storage is increasing so that capacitance is also increasing Area of plate: A 3 Design parameters of a capacitor are Distance between two plate : d Dielectric constant : ε r RC circuit Q( t ) dQ( t ) Kirchhoff’s voltage law: V= V + V V= It( ) ⋅ R V = I() t = R C R C C dt dQ Q First order ODE: V= R + ICQ. (0 ) = q dt C R dQ Q 1 Charging: Q (0) = 0 with V= R + dt C t V C VC = V 1 − exp − RC R dQ Q 2 discharging: Q(0) = CV with 0 =R + dt C + + + + + t C V VC = V exp − − − − − − RC Typical time: T= RC (RC time constant) For discharging case, when t= RC , then VC = 0.37 V FET (Field-Effect Transistor, 場效電晶體) CMOS inverter truth table Logical symbol x x x= 0⇒ x = 1 x=1⇒ x = 0 current flow MOSFET (Metal-Oxide-Semiconductor) [1] top view polysilicon (poly) SiO 2 L: channel length, also called feature size, up to 45 nm so far pFET side view http://ezphysics.nchu.edu.tw/prophys/electron/lecturenote/7_5.pdf MOSFET [2] nFET cross section pFET cross section G (gate) S (source) D (drain) Typical thickness tox = 5 nm Typical gate capacitance ∼ −15 CG fF( femtofarad,10 F ) MOSFET operation [1] zero gate voltage open switch n+ n+ W L p + p − p V V No current − n n + n pn junction forward current reverse blocking = n p n two pn junction MOSFET operation [2] positive gate voltage closed switch n+ n+ W electron channel current flows through thin electron channel from source to drain high gate voltage negative gate voltage open switch closed switch CMOSFET layers MOSFET layers in an n-well process Metal interconnect layers OutLine • Preliminary • DRAM cell -1T1C structure - trench capacitor, stack capacitor - array structure - sense amplifier - read / write operation • DRAM device • DRAM access protocol • DRAM timing parameter • DDR SDRAM DRAM cell DRAM cell = cell transistor + storage capacitor 1 charging R V C R 2 leakage + + + C V − − − Scaling of memory cell and die size of DRAM Storage capacitance should be kept constant despite the cell scaling to provide adequate operational margin with sufficient signal-to-noise ratio 對於在製程微縮過程中電容所面臨問題的解決方式，為了增加平行電板的面積又 不至於增加細胞的尺寸，有兩種製程流派來維持電容值在容許的數值之上： 深溝電容（trench capacitor ）以及堆疊電容 （stack capacitor ）。 Popular model of DRAM cell 堆疊電容 （stack capacitor ） 深溝電容（trench capacitor ） A scaling limit of capacitor structure Dielectric film should be physically thin enough not fill up the trench. F: feature size Ti : dielectric film thickness 2Ti < F Cross-section of storage node DRAM capacity (bits/die) After K. Itoh, H. Sunami, K. Nakazato, and M. Horiguchi, ECS Spring Meeting, May 4, 1998 Objective : decrease feature size to increase density of DRAM cells material Dielectric constant Material Dielectric constant Silicon dioxide 3.9 Al2O3 9.1 Ta2O5 25 La2O3 ( 氧化鑭 ) 16 TiO2 (Titanium dioxide) 85 BaTiO3 ( 鈦酸鋇) 3000~8000 ZrO2 23 SrZrO3 30 HfO2 (Hafnium oxide) 25 KTaNbO3 34000 Read operation in DRAM [1] Suppose a DRAM cell is high voltage (data value is 1) in capacitor, when do read operation, address line (word line) is selected and value of capacitor would be extracted current flow out (dis-charging) 1 Precharge to reference voltage 2 Open transistor (world line is selected) off open ∆V Vdd Vdd Vref Vref Sense amplifier capacitor Sense amplifier capacitor ∆V > 0 Sense amplifier sets bit line as 1 capacitance of storage capacitor 1 = capacitance of bitline 10 Read operation in DRAM [2] 4 Turn off transistor, complete one read operation off current flow in Vdd (charging) Sense amplifier capacitor 3 Data restoration Question 3 : what do you think “if transistor is off, open then capacitor is isolated, no leakage current flows out” ? Vdd Vdd Sense amplifier capacitor Since when data is read out, then capacitor is discharging such that it can not be read again, hence data restoration is necessary. DRAM array structure Open bitline folded bitline area per cell = 8F 2 Differential sense amplifier use a pair of bitlines to sense the voltage value in DRAM cell area per cell = 6F 2 Functionality of sense amplifier • Sense the minute change in voltage - access transistor is turned on - storage capacitor places its charge on the bitline - sense amplifier compares voltage on that bitline against a reference voltage on a separate bitline • Restores the value of cell after the voltage on the bitline is
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