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A Circuit-Level 3D DRAM Area, Timing, And ABSTRACT PARK, JONG BEOM. 3D-DATE: A Circuit-Level Three-Dimensional DRAM Area, Timing, and Energy Model. (Under the direction of W. Rhett Davis and Paul D. Franzon.) Three-dimensional stacked DRAM technology has emerged recently. Many studies have shown that 3D DRAM is most promising solutions for future memory architecture to fulfill high bandwidth and high-speed operation with low energy consumption. It is necessary to explore 3D DRAM design space and find the optimum DRAM architecture in different system needs. However, a few studies have offered models for power and access latency calculations of DRAM designs in limited ranges. This has led to a growing gap in knowledge of the area, timing, and energy modeling of 3D DRAMs for utilization in the design process of processor architectures that could benefit from 3D DRAMs. This paper presents a circuit level DRAM Area, Timing, and Energy model (DATE) which supports 3D DRAM design with TSV. DATE provides front-end and back-end DRAM process roadmap from 90 nm to 16 nm node and provides a broader range 3D DRAM design model along with emerging transistor device. DATE is successfully validated against several commodity planar and 3D DRAMs and published prototype DRAMs with emerging device. Energy verification has a mean error of about -5% to 1%, with a standard deviation of up to 9.8%. Speed verification has a mean error of about -13% to -27% and a standard deviation of up to 24%. In the case of the area, the bank has a mean error of -3% and the whole die has a mean error of -1%. The standard deviation for area is up to 4.2%. In the case study, we demonstrate that 1Gb DDR3 DRAM designs achieve up to about 0.7 Gb/sec data throughput and energy efficiency of 510 bit/nJ using 3D design options with 16 nm DRAM technology. © Copyright 2018 by Jong Beom Park All Rights Reserved 3D-DATE: A Circuit-Level Three-Dimensional DRAM Area, Timing, and Energy Model by Jong Beom Park A dissertation submitted to the Graduate Faculty of North Carolina State University in partial fulfillment of the requirements for the Degree of Doctor of Philosophy Electrical Engineering Raleigh, North Carolina 2018 APPROVED BY: James Tuck Hans Hallen W. Rhett Davis Paul D. Franzon Co-chair of Advisory Committee Co-chair of Advisory Committee DEDICATION My Lord, Jesus My wife, Jina, and my family. ii BIOGRAPHY Jong Beom Park was born in Seoul, Korea in March 1978. He earned a Bachelors of Science at Hanyang University at Ansan in 2001. In 2003, he earned a Master of Science in Electronic, Electrical, Control and Instrumentation Engineering from Hanyang University at Seoul in 2003, with a thesis entitled "Implementation of the Multirate Viterbi Algorithm for IEEE 802.11a Wireless LAN System." After working in the industry for several years, Mr. Park entered the ECE graduate program at North Carolina State University in 2009, where he earned a Masters of Science in Computer Engineering from North Carolina State University in 2010. He initiated his Ph.D. studies in Electrical Engineering in 2011 working on the NSF’s Underwater Optical Communication program with Dr. John Muth. In 2012, Mr. Park switched his research focus to the circuit design area rather than embedded system. Thus, he joined Dr. Paul D. Franzon’s research group in 2012. He started working on the DARPA PERFECT program in 2012 and 2013, focusing on the design of a custom, low power memory. Mr. Park also maintains an active interest in computer architecture, digital VLSI design, and machine learning. iii ACKNOWLEDGEMENTS First, I would like to thank Dr. Paul D. Franzon, my advisor. I still remember the moment I first joined his research group. Dr. Franzon told me, "Welcome aboard" with a generous smile. It was a great fortune for me to be on his ship. Without his mentorship and guidance, this journey would not have been possible. I also would like to thank my co-advisor, Dr. W. Rhett Davis for being supportive on many occasions, his valuable comments on my research, and providing the research opportunity. In addition, I would like to thank the following faculty members: Dr. John Muth for giving me my first research opportunity at NC State; Dr. James Tuck for his mentoring on PERFECT projects and for being my committee; and Dr. Hans Hallen for his valuable comments on my research and for being my committee. I would like to thank the following people for their contributions that have made my dissertation possible: Joshua C. Schabel for motivating me and helping me to write this thesis with creative discussions; Kirti Bhanushali and Wenxu Zhao for being great colleagues throughout the research with discussions that made ambiguities clear; Randy and Weiyi Qi for sharing insights on modeling algorithms into the program; and Lee B. Baker for sharing insights on machine learning. Finally, I would like to thank my parents and parents-in-law who would be glad in Heaven with God, my wife Jina and two lovely daughters, Songee and Yuni. I appreciate their sacrifices, support, and patience. iv TABLE OF CONTENTS LIST OF TABLES .................................................. vii LIST OF FIGURES ................................................. ix Chapter 1 Introduction ........................................... 1 1.1 Motivation................................................ 1 1.2 Original Contributions....................................... 2 1.3 Related Work.............................................. 3 1.4 Organization of Dissertation................................... 5 1.5 Abbreviations.............................................. 5 Chapter 2 DRAM Process Roadmap .................................. 7 2.1 Transistor Model and Scaling .................................. 9 2.1.1 Gate Transistor Model and Scaling......................... 11 2.1.2 High-Voltage and Peripheral transistor...................... 17 2.2 Interconnect .............................................. 18 2.2.1 Wire............................................... 18 2.2.2 Through Silicon Via.................................... 24 2.3 Roadmap and discussion ..................................... 27 2.3.1 Gate Transistor....................................... 27 2.3.2 High Voltage and Peripheral Transistor...................... 31 2.3.3 Wire............................................... 35 2.3.4 Through Silicon Via.................................... 40 Chapter 3 DRAM Circuit Level Modeling .............................. 43 3.1 Component Modeling ....................................... 46 3.1.1 General Layout and Drain Capacitance ..................... 46 3.1.2 Digital Logic and Driving Buffer........................... 51 3.1.3 Repeater for Wire ..................................... 58 3.1.4 Address Decoder...................................... 60 3.1.5 Bitline and Bitline Sense Amplifier......................... 63 3.2 Architecture Level Modeling................................... 65 3.3 Validation ................................................ 72 3.4 Comparison with Other Models ................................ 79 Chapter 4 Case Study: DRAM Design Space Exploration .................. 82 4.1 Planar Design Space Exploration in 35 nm Node .................... 83 4.1.1 Single Bank Design Space ............................... 83 4.1.2 Multi-bank Design Space in 35 nm Node .................... 98 v 4.2 3D Design Space Exploration in 35 nm Node....................... 106 4.2.1 Area Efficiency ....................................... 107 4.2.2 Energy Efficiency ..................................... 109 4.2.3 Throughput ......................................... 111 4.2.4 Product of Design Metric................................ 113 4.2.5 Design Metric Comparison in Different Technology . 116 Chapter 5 Conclusion and Future Work ............................... 119 5.1 Summary of Contributions.................................... 119 5.2 Future Work............................................... 121 BIBLIOGRAPHY .................................................. 122 APPENDICES .................................................... 129 Appendix A Derivation of the Leakage Current Equation . 130 Appendix B TCAD Simulation Code.............................. 133 B.1 Sentaurus Structure Editor Code............................ 133 B.2 Sentaurus Device Code................................... 140 B.3 Inspect Code .......................................... 144 Appendix C Definition and Derivation of the Path Effort . 147 Appendix D Reference of Commodity DRAM Part.................... 150 Appendix E How to run DATE.................................. 153 E.1 Read-me First ......................................... 153 E.2 Executable file with comments............................. 154 vi LIST OF TABLES Table 2.1 Material and doping method of gate transistor................. 13 Table 2.2 Leakage Current Criterion (fA/cell) ......................... 15 Table 2.3 ITRS Saturation Current Roadmap of Supportive NMOSFET at 25 ◦C . 18 Table 2.4 Gate transistor roadmap................................. 29 Table 2.5 High voltage transistor roadmap........................... 33 Table 2.6 Peripheral transistor roadmap............................. 33 Table 2.7 DATE wire roadmap .................................... 34 Table 2.8 Wire comparison with commodity logic design process .......... 39 Table 2.9 ITRS TSV physical dimension roadmap...................... 41 Table 2.10 CACTI-3DD TSV physical dimension roadmap................. 41 Table 2.11 DATE TSV area, capacitance, and resistance roadmap............ 41 Table 2.12 ITRS TSV area, capacitance,
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