Integration of Molecular Components into Silicon Memory Devices by Werner G. Kuhr onsumer and business appetite for electronic devices drives the C semiconductor industry’s need for miniaturization. The state of the art of semiconductor devices now has critical feature dimensions substantially less than 0.1 µm.1 While many devices can be manufactured effectively at such dimensions through the continued extension and optimiza- tion of existing process technologies, it is uncertain at what point along the path of miniaturization such devices, which rely on the bulk properties of materials, will retain the required func- tional characteristics. Much work has been done in the field of molecular electronics, where many investigators have attempted to mimic transistor properties in molecular systems.1 While FIG. 1. DRAM array (left), with examples of trench and stacked cell geometries for the DRAM capacitor. the creation of a molecular transistor has received the lion’s share of atten- tion (and criticism),2 transistor fabrica- tion is expected to scale to 10 nm dimensions, albeit with a great deal of stored in each device (which, in turn, is the memory industry to develop three- effort.3 Indeed, the component that is based on the voltage and the capaci- dimensional structures to provide most urgently in need of replacement tance available), and the leakage current, enough capacitive area to store sufficient for most semiconductor devices is the along with the number of memory ele- charge to allow reliable operation. With 2 charge storage device, i.e., the capacitor. ments that must be refreshed in each a SiO2 capacitor, almost 5 µm of surface Almost all existing memory devices cycle. Thus, a key design feature in the area is necessary to store ~100 fC of utilize charge storage as the mechanism miniaturization of DRAM circuit ele- charge. Two of the most commonly of information storage [including ments is the amount of available charge employed strategies to increase the effec- dynamic random access memory in each capacitor as feature size shrinks. tive area of the capacitor include trench (DRAM), FLASH RAM, and one-transis- There is increasing evidence that the or stacked structures (Fig. 1). In the tor static RAM (1T SRAM)]. In particu- materials used in existing devices are trench design, a hole is drilled into the lar, DRAM consists of large arrays of unable to scale effectively with the other silicon substrate at the critical dimen- storage cells, each of which consists of circuit elements used in DRAM circuits. sion, and the capacitor is built through one capacitor and one transistor, where For example, a DRAM capacitor in an deposition of the dielectric on the walls the charge stored on the capacitor indi- efficient memory array must occupy a of the cylindrical hole. This can increase cates the bit level (Fig. 1). Due to the surface area corresponding to less than the effective area to over 5 µm2 and pro- combination of stringent requirements 4F2 (allowing for a 6F2 total cell area), vide sufficient capacitance for a reliable for data fidelity for RAM (which where F is the minimum critical feature device, but at significant manufacturing impacts the minimum amount of sig- size of the device. In a 256 MB DRAM cost. In this device, the aspect ratio nal that must be available from each manufactured at the state of the art in a (depth/width) of the trench can be over cell for sensing, currently ~100 fC or production environment, F is 0.11 µm, 100, leading to tremendous process ~600,000 electrons) and that capacitors and this translates to a capacitor area of complexity and cost. Fabrication of the are imperfect, leaky devices (the charge roughly 0.048 µm2, and this cell must be DRAM capacitor in existing devices on an existing DRAM capacitor decays able to operate at less than 2 V. The most already requires over one-third of the rapidly, ~100 ms in existing devices), commonly used dielectric materials used process steps, and this process complexi- the data stored in each location must be for DRAM capacitors have a charge den- ty will increase even more as the aspect refreshed periodically by reading it and sity of 1-2 µC/cm2, and at these dimen- ratio becomes larger with even smaller then writing it back again. The frequen- sions hold only 1 fC, (roughly 6000 elec- devices. As critical dimensions continue cy at which this refresh must be repeat- trons). to shrink, it is likely that this process ed is determined by many factors, Therefore, a tremendous amount of cannot reasonably continue. As dis- including the magnitude of charge time and effort has been expended by cussed in this article, a DRAM based on 34 The Electrochemical Society Interface • Spring 2004 Table I. Criteria for Incorporation of Molecules in CMOS • The charge storage properties are dependent on the molecule, not Storage Devices. the underlying substrate.4-11 • The size of the device dictates the Property Implementation number of molecules (proportion- al to area). Chemical stability ............................................Delocalized cationic charge • Charge is stored in stable redox states of molecules, leading to Thermal stability ..................................................Decomposition > 400° C high charge density (more than Endurance ................................................Endurance > 1012 to 1015 cycles ten times higher than convention- al SiO capacitors).4-10 Read/write speed ..........................................................t = 1/k < 10 ns 2 R/W eff • Charge-retention times are also a Charge retention ..........................................................................t1/2 > 10 s molecular property, not depen- dent on the leakage characteristics 2 Charge density......................................................µ = 10 µC/cm or higher of the gating device, and are in the Self-assembly and ............................Selective, covalent bond formation of range of minutes to hours self-alignment molecules to specific substrate (>10,000 times that of semicon- ductors).9 • Molecules can be attached at high surface coverage (in the range of 1.0 x 10-10 mol cm-2) using small amounts of materials.8-10 • Temperatures as high as 400°C can be used during fabrication with no degradation of the molecules. This result is of importance in that many processing steps in fabricat- ing complementary metal-oxide- semiconductor (CMOS) devices entail high-temperature processing, even at the back end of the line.4 • Devices using porphyrins applied in this manner have been tested for endurance, and no sign of degradation of any aspect of per- formance was observed after 1012 cycles.4 • Multiple bits can be stored in a given memory location using the distinct oxidation states of the molecules, which can lead to high- FIG. 2. Properties of molecules used for charge storage. er array densities.8 • This type of molecular memory should scale to near molecular dimensions, because electronic molecular properties is more suitable for adequate stability, endurance, and oper- properties are intrinsic to the mol- smaller feature sizes. ating properties to meet such require- ecular structure.4-11 ments, and only recently has it been Charge Storage in demonstrated that some molecular Attachment of Redox Monolayers materials may be able to withstand these Molecules to Silicon demanding criteria.4 Some redox sys- Devices Recently, molecules that may be suit- tems have been investigated for use in able for use in semiconductor devices the fabrication of molecular-based infor- The fabrication of stable and reliable have been the subject of much atten- mation storage systems. These systems CMOS/molecular devices requires the tion.4,5 To be able to serve in this role, employ metallocene, porphyrin, and covalent attachment of an electroactive molecular components must remain triple-decker sandwich coordination molecule (such as a porphyrin or a fer- robust under the same daunting condi- compounds as the charge-storage ele- rocene) to a device substrate (e.g., Si). tions that all existing semiconductor ments covalently attached to metals and Attachment of molecules to silicon is 4-11 materials already endure including high- device-grade silicon (Fig. 2). accomplished through covalent linkage temperature processing steps during These molecules exhibit redox char- chemistries involving the formation of 5-11 manufacture and demanding require- acteristics that make them amenable for Si-C or Si-O bonds. It is important ments for operation (see Table I). There use as multibit information-storage to emphasize that the stability of the has been considerable skepticism media. Some key aspects of this technol- bond formed between the substrate and whether molecular materials possess ogy are reviewed below. the redox molecule will dictate the The Electrochemical Society Interface • Spring 2004 35 FIG. 3. Hybrid CMOS/molecular DRAM cell. thermal and electrical stability of the lowed by deposition of a metal layer, charge-retention behavior on the sub- self-assembled monolayer (SAM). For which is evaporated or sputtered on to strate size or material, but a strong example, thiol/gold chemistry, which complete the cell (Fig. 3). This material dependence on the composition and size has been used extensively in many acad- can be any well-behaved electrochemical of the tether separating the redox site emic labs for the characterization of counter electrode material such as cop- from the surface.9,10 The charge reten- monolayer redox systems, does not pro- per, silver, etc.