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An Efficient Framework for Implementing Persistent Data Structures on Asymmetric NVM Architecture

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An Efficient Framework for Implementing Persistent Data Structures on Asymmetric NVM Architecture AsymNVM: An Efficient Framework for Implementing Persistent Data Structures on Asymmetric NVM Architecture Teng Ma Mingxing Zhang Kang Chen∗ [email protected] [email protected] [email protected] Tsinghua University Tsinghua University & Sangfor Tsinghua University Beijing, China Shenzhen, China Beijing, China Zhuo Song Yongwei Wu Xuehai Qian [email protected] [email protected] [email protected] Alibaba Tsinghua University University of Southern California Beijing, China Beijing, China Los Angles, CA Abstract We build AsymNVM framework based on AsymNVM ar- The byte-addressable non-volatile memory (NVM) is a promis- chitecture that implements: 1) high performance persistent ing technology since it simultaneously provides DRAM-like data structure update; 2) NVM data management; 3) con- performance, disk-like capacity, and persistency. The cur- currency control; and 4) crash-consistency and replication. rent NVM deployment with byte-addressability is symmetric, The key idea to remove persistency bottleneck is the use of where NVM devices are directly attached to servers. Due to operation log that reduces stall time due to RDMA writes and the higher density, NVM provides much larger capacity and enables efficient batching and caching in front-end nodes. should be shared among servers. Unfortunately, in the sym- To evaluate performance, we construct eight widely used metric setting, the availability of NVM devices is affected by data structures and two transaction applications based on the specific machine it is attached to. High availability canbe AsymNVM framework. In a 10-node cluster equipped with achieved by replicating data to NVM on a remote machine. real NVM devices, results show that AsymNVM achieves However, it requires full replication of data structure in local similar or better performance compared to the best possible memory — limiting the size of the working set. symmetric architecture while enjoying the benefits of disag- This paper rethinks NVM deployment and makes a case gregation. We found the speedup brought by the proposed for the asymmetric byte-addressable non-volatile memory optimizations is drastic, — 5∼12× among all benchmarks. architecture, which decouples servers from persistent data CCS Concepts • Computer systems organization → storage. In the proposed AsymNVM architecture, NVM de- Processors and memory architectures; • Information vices (i.e., back-end nodes) can be shared by multiple servers systems → Data centers; • Hardware → Non-volatile mem- (i.e., front-end nodes) and provide recoverable persistent data ory. structures. The asymmetric architecture, which follows the industry trend of resource disaggregation, is made possible Keywords memory architectures; persistent memory; RDMA due to the high-performance network (e.g., RDMA). At the ACM Reference Format: same time, AsymNVM leads to a number of key problems Teng Ma, Mingxing Zhang, Kang Chen, Zhuo Song, Yongwei Wu, such as, still relatively long network latency, persistency bot- and Xuehai Qian. 2020. AsymNVM: An Efficient Framework for Im- tleneck, and simple interface of the back-end NVM nodes. plementing Persistent Data Structures on Asymmetric NVM Archi- tecture. In Proceedings of the Twenty-Fifth International Conference ∗Corresponding Author. on Architectural Support for Programming Languages and Operating Permission to make digital or hard copies of all or part of this work for Systems (ASPLOS ’20), March 16–20, 2020, Lausanne, Switzerland. personal or classroom use is granted without fee provided that copies are not ACM, New York, NY, USA, 17 pages. https://doi.org/10.1145/3373376. made or distributed for profit or commercial advantage and that copies bear 3378511 this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to 1 Introduction redistribute to lists, requires prior specific permission and/or a fee. Request Emerging non-volatile memory (NVM) is blurring the line permissions from [email protected]. between memory and storage. These kinds of memories, such ASPLOS ’20, March 16–20, 2020, Lausanne, Switzerland © 2020 Association for Computing Machinery. as Intel Optane DC persistent memory [43], phase change ACM ISBN 978-1-4503-7102-5/20/03...$15.00 memory (PCM) [9, 54, 103], spin-transfer torque magnetic https://doi.org/10.1145/3373376.3378511 memory (STTM) [4], and memristor are byte-addressable, ASPLOS ’20, March 16–20, 2020, Lausanne, Switzerland Teng Ma, Mingxing Zhang, Kang Chen, Zhuo Song, Yongwei Wu, and Xuehai Qian and provide DRAM-like performance (300ns/100ns latency disaggregated resources that are not associated with any for read/write), high density (TB-scale), and persistency at server. It also improves the availability since the crash of a the same time [45, 99]. To unleash the potential of NVM, most server will not affect NVM devices. existing solutions attach NVM directly to processors [14, 28, The main principle of AsymNVM architecture is to use 62, 92, 94], enabling high-performance implementations of high-performance network (RDMA) to access remote NVM persistent data structures using load and store instructions and local DRAM as cache to ensure high performance. The on local memory. concrete design poses several key challenges. First, directly While accessing NVM via local memory provides promis- replacing local store and load instructions with RDMA_Write ing performance, it is not the most suitable setting in the and RDMA_Read still suffers from long network latency. Al- context of data center due to the desire of sharing NVM. Due though the throughput of RDMA over InfiniBand is compa- to the higher density, NVM can provide much larger ca- rable to the throughput of NVM, NIC still cannot provide pacity [45, 64], which may exceed the need of a single ma- enough IOPS for fine-grained data structure accesses. Second, chine [5]. In data center servers, the resources are often using local DRAM as cache should be carefully considered under utilized [19, 23], — Google’s study [29] shows the re- with the persistency semantics. Third, we need to ensure that source utilization lower than 40% on average. We expect that the interface of back-end nodes is both simple and efficient. persistent resource utilization will follow the same trend. Based on AsymNVM architecture, this paper builds Asym- To enable NVM sharing, recent work [81] builds a dis- NVM framework that implements byte-level data structures tributed shared persistent memory system, which provides updates with high performance and availability. To efficiently a global, shared, and persistent memory space for a pool of solve the three challenges, the framework efficiently imple- machines with NVMs attached to each at the main memory ments four components: 1) to remove persistency bottleneck, bus. This setting inherently affect availability: once an NVM high performance byte-level persistent data structure update device is attached to a specific machine, its data become un- is supported by operation log that reduces the stall due to available when the host machine goes down. One solution RDMA writes and enables efficient communication batch- to this problem is to replicate the data to a remote NVM [44]. ing and DRAM caching (Section4); 2) NVM data manage- However, it requires full replication of data structures in ment that handles non-volatile memory allocation and free, local memory, limiting the size of the working set. To access and metadata storage (Section5); 3) concurrency control that the replicated data, the lower-bound of network overhead is supports both lock-free and lock-based data structures (Sec- at least one network round-trip for each operation. tion6); and 4) crash-consistency and replication that ensures In essence, these challenges are due to the symmetric na- correct recovery and availability (Section7). Moreover, we ture of most of the current NVM deployment [44, 81, 83]. To apply several data structure specific optimizations to further fundamentally overcome the drawbacks, we rethink NVM improve performance (Section8). deployment and propose the byte-addressable asymmetric To evaluate the performance of AsymNVM framework, NVM architecture, in which NVM devices are not associ- we choose eight widely used data structures and two appli- ated with the individual machine and accessed at byte-level cations (TATP/SmallBank), and use traces of industry work- only passively via fast network. In AsymNVM architecture, loads. The data structures/applications are executed in a the number of NVM devices, which can be provided as spe- 10-node cluster, in which at most three machines are used as cialized “blades”, can be much smaller than the number of the back-end node and mirror nodes. The results show that machines. AsymNVM achieves similar or better performance compared AsymNVM architecture follows the recent trend of dis- to the best possible symmetric architecture while enjoying aggregation architecture, which was first proposed for ca- benefits of disaggregation. Speedup brought by the proposed pacity expansion and memory resource sharing by Lim et optimizations is drastic, — 5∼12× among all benchmarks. al. [59, 60]. As described by Gao et al. [26], disaggregated architecture is a paradigm shift from servers each tightly integrated with a small amount of various resources (e.g., CPU, memory [30, 67, 68], storage [65]) to the disaggregated 2 Background data center built as a pool of standalone resource blades and Single-Node Local NVM. In this setting, NVM device is interconnected using a network fabric. In industry, Intel’s directly accessed via the processor-memory bus using load- RSD [39] and HP’s “The Machine” [74] are state-of-the-art /store instructions. It avoids the overhead of legacy block- disaggregation architecture products. Such systems are not oriented file-systems/databases. Instead, it allows persistent limited by the capability of a single machine and can pro- data structure updates at byte level without the need for vide better resource utilization and the ease of hardware serialization.
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